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1 ========================================== |
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2 HP3562A Dynamic Signal Analyzer - Part 3 |
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3 ========================================== |
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4 |
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5 :Author: David Douard |
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6 :Category: Electronics |
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7 :Tags: HP3562A, repair, test equipment, DSA |
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8 :series: HP 3562A |
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9 :series_index: 3 |
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10 |
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11 This is the part 3 of the series about my |
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12 `HP 3562A Digital Signal Analyzer <{filename}hp3562a.rst>`_, |
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13 quickly describing the Analog Section of the instrument. |
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14 |
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15 |
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16 Analog Section |
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17 ============== |
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18 |
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19 The analog section consist in 6 boards: |
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20 |
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21 - A30: Analog Source |
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22 - A31: Trigger |
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23 - A32, A34: Input ADCs |
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24 - A33, A35: Input |
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25 |
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26 Analog Source |
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27 ------------- |
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28 |
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29 .. image:: {filename}images/hp3562a/hp3562a_a30_block_diagram.png |
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30 |
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31 This board is mainly a DAC converting signal signal from the Digital |
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32 Source board (for sin waves). It also generates Pseudo Random Noise |
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33 and square waves (used for input calibration). |
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34 |
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35 The analog signal produced by the DAC is filtered by a 100kHz low pass |
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36 filter, then pass throught a step attenuator (5mV per step). The way |
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37 this is implemented is quite interesting: the analog signal from the |
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38 main DAC is used a reference voltage for a multiplying DAC. |
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39 |
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40 .. image:: {filename}images/hp3562a/a30_analog_source.jpg |
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41 |
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42 .. image:: {filename}images/hp3562a/a30_analog_source_dac.jpg |
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43 |
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44 Trigger |
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45 ------- |
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46 |
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47 A first section of this board produces the trigger signal (for A1 |
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48 Digital Source and A5 Digital Filter boards) from one of the 4 |
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49 possible trigger sources: external, channel 1, channel 2 and the |
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50 calibration. |
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51 |
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52 .. image:: {filename}images/hp3562a/trigger_level.png |
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53 |
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54 The trigger clock circuit produces the 20.48MHz clock using a |
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55 VCXO. From this signal are derived the 10.24MHz clock used by many |
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56 boards (A1, A4, A5, A6, A30, A32 and A34) and the 256kHz clock signal |
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57 used as internal sample signal. |
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58 |
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59 When an external clock is provided, a PLL is used to lock this |
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60 20.48MHz. The external signal can be 1, 2, 5 or the standard 10MHz. |
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61 |
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62 .. image:: {filename}images/hp3562a/trigger_clock.png |
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63 |
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64 .. image:: {filename}images/hp3562a/a31_trigger.jpg |
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65 |
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66 |
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67 Input ADC |
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68 --------- |
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69 |
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70 .. image:: {filename}images/hp3562a/hp3562a_a32_block_diagram.png |
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71 |
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72 |
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73 The ADC board converts analog data from the input board into 13-bits |
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74 serial data words. The Analog to Digital convertion is done in 2 |
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75 passes by a 8-bits ADC. At each digitilization step, the signal value |
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76 is frozen by a Track and Hold circuit. This frozen value is digitized |
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77 (with a 8-bit resolution), then the digitized value is substracted |
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78 from the input (hold) signal and the result is multiplied then |
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79 digitized a second time to produce the remaining 5-bits of resolution. |
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80 |
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81 .. image:: {filename}images/hp3562a/a32_input_adc.jpg |
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82 .. image:: {filename}images/hp3562a/a32_input_adc_bb.jpg |
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83 |
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84 |
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85 Input |
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86 ----- |
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87 |
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88 .. image:: {filename}images/hp3562a/hp3562a_a33_block_diagram.png |
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89 |
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90 The input assembly implements the voltage ranges and conditions the |
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91 input signal. It mostly consist in a pair switch attenuators (the |
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92 input is balanced), followed by a pair of amplifier/signal |
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93 conditionners. The balanced signal is then fed into a differential |
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94 amplifier followed by a amplifier and an attenuator. |
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95 |
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96 .. image:: {filename}images/hp3562a/a33_input.jpg |
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97 |
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98 |
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99 Next |
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100 ==== |
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101 |
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102 In the `next part <{filename}hp3562a_4.rst>`_, we will describe the |
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103 HP 1345A Digital Display used in the instrument. |