comparison: content/hp3562a_3.rst
content/hp3562a_3.rst
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| 7 :Tags: HP3562A, repair, test equipment, DSA | 7 :Tags: HP3562A, repair, test equipment, DSA |
| 8 :series: HP 3562A | 8 :series: HP 3562A |
| 9 :series_index: 3 | 9 :series_index: 3 |
| 10 | 10 |
| 11 This is the part 3 of the series about my | 11 This is the part 3 of the series about my |
| 12 `HP 3562A Digital Signal Analyzer <{filename}hp3562a.rst>`_, | 12 `HP 3562A Digital Signal Analyzer <{static}hp3562a.rst>`_, |
| 13 quickly describing the Analog Section of the instrument. | 13 quickly describing the Analog Section of the instrument. |
| 14 | 14 |
| 15 | 15 |
| 16 Analog Section | 16 Analog Section |
| 17 ============== | 17 ============== |
| 24 - A33, A35: Input | 24 - A33, A35: Input |
| 25 | 25 |
| 26 Analog Source | 26 Analog Source |
| 27 ------------- | 27 ------------- |
| 28 | 28 |
| 29 .. image:: {filename}images/hp3562a/hp3562a_a30_block_diagram.png | 29 .. image:: {static}images/hp3562a/hp3562a_a30_block_diagram.png |
| 30 | 30 |
| 31 This board is mainly a DAC converting signal signal from the Digital | 31 This board is mainly a DAC converting signal signal from the Digital |
| 32 Source board (for sin waves). It also generates Pseudo Random Noise | 32 Source board (for sin waves). It also generates Pseudo Random Noise |
| 33 and square waves (used for input calibration). | 33 and square waves (used for input calibration). |
| 34 | 34 |
| 35 The analog signal produced by the DAC is filtered by a 100kHz low pass | 35 The analog signal produced by the DAC is filtered by a 100kHz low pass |
| 36 filter, then pass throught a step attenuator (5mV per step). The way | 36 filter, then pass throught a step attenuator (5mV per step). The way |
| 37 this is implemented is quite interesting: the analog signal from the | 37 this is implemented is quite interesting: the analog signal from the |
| 38 main DAC is used a reference voltage for a multiplying DAC. | 38 main DAC is used a reference voltage for a multiplying DAC. |
| 39 | 39 |
| 40 .. image:: {filename}images/hp3562a/a30_analog_source.jpg | 40 .. image:: {static}images/hp3562a/a30_analog_source.jpg |
| 41 | 41 |
| 42 .. image:: {filename}images/hp3562a/a30_analog_source_dac.jpg | 42 .. image:: {static}images/hp3562a/a30_analog_source_dac.jpg |
| 43 | 43 |
| 44 Trigger | 44 Trigger |
| 45 ------- | 45 ------- |
| 46 | 46 |
| 47 A first section of this board produces the trigger signal (for A1 | 47 A first section of this board produces the trigger signal (for A1 |
| 48 Digital Source and A5 Digital Filter boards) from one of the 4 | 48 Digital Source and A5 Digital Filter boards) from one of the 4 |
| 49 possible trigger sources: external, channel 1, channel 2 and the | 49 possible trigger sources: external, channel 1, channel 2 and the |
| 50 calibration. | 50 calibration. |
| 51 | 51 |
| 52 .. image:: {filename}images/hp3562a/trigger_level.png | 52 .. image:: {static}images/hp3562a/trigger_level.png |
| 53 | 53 |
| 54 The trigger clock circuit produces the 20.48MHz clock using a | 54 The trigger clock circuit produces the 20.48MHz clock using a |
| 55 VCXO. From this signal are derived the 10.24MHz clock used by many | 55 VCXO. From this signal are derived the 10.24MHz clock used by many |
| 56 boards (A1, A4, A5, A6, A30, A32 and A34) and the 256kHz clock signal | 56 boards (A1, A4, A5, A6, A30, A32 and A34) and the 256kHz clock signal |
| 57 used as internal sample signal. | 57 used as internal sample signal. |
| 58 | 58 |
| 59 When an external clock is provided, a PLL is used to lock this | 59 When an external clock is provided, a PLL is used to lock this |
| 60 20.48MHz. The external signal can be 1, 2, 5 or the standard 10MHz. | 60 20.48MHz. The external signal can be 1, 2, 5 or the standard 10MHz. |
| 61 | 61 |
| 62 .. image:: {filename}images/hp3562a/trigger_clock.png | 62 .. image:: {static}images/hp3562a/trigger_clock.png |
| 63 | 63 |
| 64 .. image:: {filename}images/hp3562a/a31_trigger.jpg | 64 .. image:: {static}images/hp3562a/a31_trigger.jpg |
| 65 | 65 |
| 66 | 66 |
| 67 Input ADC | 67 Input ADC |
| 68 --------- | 68 --------- |
| 69 | 69 |
| 70 .. image:: {filename}images/hp3562a/hp3562a_a32_block_diagram.png | 70 .. image:: {static}images/hp3562a/hp3562a_a32_block_diagram.png |
| 71 | 71 |
| 72 | 72 |
| 73 The ADC board converts analog data from the input board into 13-bits | 73 The ADC board converts analog data from the input board into 13-bits |
| 74 serial data words. The Analog to Digital convertion is done in 2 | 74 serial data words. The Analog to Digital convertion is done in 2 |
| 75 passes by a 8-bits ADC. At each digitilization step, the signal value | 75 passes by a 8-bits ADC. At each digitilization step, the signal value |
| 76 is frozen by a Track and Hold circuit. This frozen value is digitized | 76 is frozen by a Track and Hold circuit. This frozen value is digitized |
| 77 (with a 8-bit resolution), then the digitized value is substracted | 77 (with a 8-bit resolution), then the digitized value is substracted |
| 78 from the input (hold) signal and the result is multiplied then | 78 from the input (hold) signal and the result is multiplied then |
| 79 digitized a second time to produce the remaining 5-bits of resolution. | 79 digitized a second time to produce the remaining 5-bits of resolution. |
| 80 | 80 |
| 81 .. image:: {filename}images/hp3562a/a32_input_adc.jpg | 81 .. image:: {static}images/hp3562a/a32_input_adc.jpg |
| 82 .. image:: {filename}images/hp3562a/a32_input_adc_bb.jpg | 82 .. image:: {static}images/hp3562a/a32_input_adc_bb.jpg |
| 83 | 83 |
| 84 | 84 |
| 85 Input | 85 Input |
| 86 ----- | 86 ----- |
| 87 | 87 |
| 88 .. image:: {filename}images/hp3562a/hp3562a_a33_block_diagram.png | 88 .. image:: {static}images/hp3562a/hp3562a_a33_block_diagram.png |
| 89 | 89 |
| 90 The input assembly implements the voltage ranges and conditions the | 90 The input assembly implements the voltage ranges and conditions the |
| 91 input signal. It mostly consist in a pair switch attenuators (the | 91 input signal. It mostly consist in a pair switch attenuators (the |
| 92 input is balanced), followed by a pair of amplifier/signal | 92 input is balanced), followed by a pair of amplifier/signal |
| 93 conditionners. The balanced signal is then fed into a differential | 93 conditionners. The balanced signal is then fed into a differential |
| 94 amplifier followed by a amplifier and an attenuator. | 94 amplifier followed by a amplifier and an attenuator. |
| 95 | 95 |
| 96 .. image:: {filename}images/hp3562a/a33_input.jpg | 96 .. image:: {static}images/hp3562a/a33_input.jpg |
| 97 | 97 |
| 98 | 98 |
| 99 Next | 99 Next |
| 100 ==== | 100 ==== |
| 101 | 101 |
| 102 In the `next part <{filename}hp3562a_4.rst>`_, we will describe the | 102 In the `next part <{static}hp3562a_4.rst>`_, we will describe the |
| 103 HP 1345A Digital Display used in the instrument. | 103 HP 1345A Digital Display used in the instrument. |
