content/hp8662a_3.rst

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24 procedure to follow in on the Service Sheet H. The general block diagram of 24 procedure to follow in on the Service Sheet H. The general block diagram of
25 this section is as follow: 25 this section is as follow:
26 26
27 .. image:: {static}/images/hp8662a/LF_block_diagram.png 27 .. image:: {static}/images/hp8662a/LF_block_diagram.png
28 :class: image-process-large-photo 28 :class: image-process-large-photo
29 :alt: LF block diagram
29 30
30 This Low Frequency Section consists in no less than 4 phase locked loops in 31 This Low Frequency Section consists in no less than 4 phase locked loops in
31 order to achieve adjustable frequency synthesis with the expected stability and 32 order to achieve adjustable frequency synthesis with the expected stability and
32 resolution. 33 resolution.
33 34
55 56
56 Here is a more detailed vue of the block diagram of the low frequency section: 57 Here is a more detailed vue of the block diagram of the low frequency section:
57 58
58 .. image:: {static}/images/hp8662a/sheet_H.png 59 .. image:: {static}/images/hp8662a/sheet_H.png
59 :class: image-process-large-photo 60 :class: image-process-large-photo
61 :alt: LF detailed block diagram
60 62
61 63
62 Fixing the Error 04 64 Fixing the Error 04
63 =================== 65 ===================
64 66
132 134
133 For example, at 100.3MHz, we have a decent signal: 135 For example, at 100.3MHz, we have a decent signal:
134 136
135 .. image:: {static}/images/hp8662a/working_not_quite_3.jpg 137 .. image:: {static}/images/hp8662a/working_not_quite_3.jpg
136 :class: image-process-large-photo 138 :class: image-process-large-photo
139 :alt: generate a 100.3MHz signal
137 140
138 .. image:: {static}/images/hp8662a/working_not_quite_3_sa.jpg 141 .. image:: {static}/images/hp8662a/working_not_quite_3_sa.jpg
139 :class: image-process-large-photo 142 :class: image-process-large-photo
143 :alt: 100.3MHz signal - spectrum
140 144
141 but at 101.0Mhz, it begins to looks pretty messy: 145 but at 101.0Mhz, it begins to looks pretty messy:
142 146
143 .. image:: {static}/images/hp8662a/working_not_quite_2.jpg 147 .. image:: {static}/images/hp8662a/working_not_quite_2.jpg
144 :class: image-process-large-photo 148 :class: image-process-large-photo
149 :alt: generate a 101.0MHz signal
145 150
146 .. image:: {static}/images/hp8662a/working_not_quite_2_sa.jpg 151 .. image:: {static}/images/hp8662a/working_not_quite_2_sa.jpg
147 :class: image-process-large-photo 152 :class: image-process-large-photo
153 :alt: 101.0MHz signal - noisy spectrum
148 154
149 and 101.9Mhz shows "nice" side bands: 155 and 101.9Mhz shows "nice" side bands:
150 156
151 .. image:: {static}/images/hp8662a/working_not_quite.jpg 157 .. image:: {static}/images/hp8662a/working_not_quite.jpg
152 :class: image-process-large-photo 158 :class: image-process-large-photo
159 :alt: generate a 101.9MHz signal
153 160
154 .. image:: {static}/images/hp8662a/working_not_quite_sa.jpg 161 .. image:: {static}/images/hp8662a/working_not_quite_sa.jpg
155 :class: image-process-large-photo 162 :class: image-process-large-photo
163 :alt: 101.9MHz signal - with spurious side bands
156 164
157 The problem seems quite clear: some PLL cannot lock at specific frequencies, 165 The problem seems quite clear: some PLL cannot lock at specific frequencies,
158 but the strange thing is that this unlock PLL does not produces an error. 166 but the strange thing is that this unlock PLL does not produces an error.
159 167
160 So I tried to figure out which boad assembly could be the culprit. With no 168 So I tried to figure out which boad assembly could be the culprit. With no
178 186
179 For example, a 101MHz signal which was very unstable before now looks like: 187 For example, a 101MHz signal which was very unstable before now looks like:
180 188
181 .. image:: {static}/images/hp8662a/working_101.jpg 189 .. image:: {static}/images/hp8662a/working_101.jpg
182 :class: image-process-large-photo 190 :class: image-process-large-photo
191 :alt: 101.0MHz signal - better spectrum

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