diff -r aba381b2bac9 -r 42a19a0d1c99 content/hp8662a_3.rst
--- a/content/hp8662a_3.rst	Thu Nov 05 22:15:16 2020 +0100
+++ b/content/hp8662a_3.rst	Thu Nov 05 23:28:39 2020 +0100
@@ -26,6 +26,7 @@
 
 .. image:: {static}/images/hp8662a/LF_block_diagram.png
    :class: image-process-large-photo
+   :alt: LF block diagram
 
 This Low Frequency Section consists in no less than 4 phase locked loops in
 order to achieve adjustable frequency synthesis with the expected stability and
@@ -57,6 +58,7 @@
 
 .. image:: {static}/images/hp8662a/sheet_H.png
    :class: image-process-large-photo
+   :alt: LF detailed block diagram
 
 
 Fixing the Error 04
@@ -134,25 +136,31 @@
 
 .. image:: {static}/images/hp8662a/working_not_quite_3.jpg
    :class: image-process-large-photo
+   :alt: generate a 100.3MHz signal
 
 .. image:: {static}/images/hp8662a/working_not_quite_3_sa.jpg
    :class: image-process-large-photo
+   :alt: 100.3MHz signal - spectrum
 
 but at 101.0Mhz, it begins to looks pretty messy:
 
 .. image:: {static}/images/hp8662a/working_not_quite_2.jpg
    :class: image-process-large-photo
+   :alt: generate a 101.0MHz signal
 
 .. image:: {static}/images/hp8662a/working_not_quite_2_sa.jpg
    :class: image-process-large-photo
+   :alt: 101.0MHz signal - noisy spectrum
 
 and 101.9Mhz shows "nice" side bands:
 
 .. image:: {static}/images/hp8662a/working_not_quite.jpg
    :class: image-process-large-photo
+   :alt: generate a 101.9MHz signal
 
 .. image:: {static}/images/hp8662a/working_not_quite_sa.jpg
    :class: image-process-large-photo
+   :alt: 101.9MHz signal - with spurious side bands
 
 The problem seems quite clear: some PLL cannot lock at specific frequencies,
 but the strange thing is that this unlock PLL does not produces an error.
@@ -180,3 +188,4 @@
 
 .. image:: {static}/images/hp8662a/working_101.jpg
    :class: image-process-large-photo
+   :alt: 101.0MHz signal - better spectrum