content/hp8662a_3.rst

Wed, 13 Mar 2024 11:03:13 +0100

author
David Douard <david.douard@sdf3.org>
date
Wed, 13 Mar 2024 11:03:13 +0100
changeset 152
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parent 129
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permissions
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Update URLs for pcb & firmware to sourcehut

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1 ===============================================
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2 HP8662A Synthetized Signal Generator - Part 3
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3 ===============================================
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4
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5 :Author: David Douard
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6 :Category: Electronics
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7 :Tags: HP8662A, repair, test equipment, HP, Generator, RF
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8 :series: HP 8662A
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9 :series_index: 3
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12 This is the part 3 on my series about my HP 8662A Signal Generator, and is
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13 about the third main problems I found with this unit, as evocated in `part
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14 2 <{filename}/hp8662a_2.rst>`_: Error 04 is lit and there are some very
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15 unpleasant spectrums at some frequencies.
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16
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17
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18 Low Fequency Section
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19 ====================
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20
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21 If the generator is now able to produce a signal (the AM and FM modulations
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22 also work), it also gives an Error 04, which is described in the Service Manual
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23 as "Sum Loop Unlocked (Low Frequency Section)", and the troubleshooting
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24 procedure to follow in on the Service Sheet H. The general block diagram of
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25 this section is as follow:
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26
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27 .. image:: {static}/images/hp8662a/LF_block_diagram.png
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28 :class: image-process-large-photo
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29 :alt: LF block diagram
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30
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31 This Low Frequency Section consists in no less than 4 phase locked loops in
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32 order to achieve adjustable frequency synthesis with the expected stability and
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33 resolution.
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34
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35 In fact, when in the main band of the generator, ie. when neither the output
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36 frequency doubler nor the down converter are in the signal path (that is, when
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37 the frequency range is between 120MHz and 640MHz). The frequency display
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38 consists in 11 digits, named DF0 to DF10, which are segmented to control
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39 several sets of PLLs:
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40
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41 ========= =====================================================================
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42 :DF0-DF2: are the fractional part of the fractional N-Loop (.1Hz, 1Hz and
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43 10Hz digits),
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44 --------- ---------------------------------------------------------------------
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45 :DF3-DF5: are the integer part of the fractional N-loop (100Hz, 1kHz and
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46 10kHz resolutions)
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47 --------- ---------------------------------------------------------------------
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48 :DF6-DF7: are used to set the pretune VCO value for the sum loop VCO (A3A7),
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49 the FM sum loop VCO (A3A8) as well as the N-Loop VCO (A3A4). These
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50 are the 0.1MHz and 1MHz resolution digits.
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51 --------- ---------------------------------------------------------------------
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52 :DF8-DF9: these control the high frequency section (DF10 can only be 0 or 1,
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53 in which case the frequency doubler is used).
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54 ========= =====================================================================
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55
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56
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57 Here is a more detailed vue of the block diagram of the low frequency section:
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58
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59 .. image:: {static}/images/hp8662a/sheet_H.png
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60 :class: image-process-large-photo
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61 :alt: LF detailed block diagram
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63
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64 Fixing the Error 04
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65 ===================
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66
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67 The service manual describes the Error 04 as related to the Sum Loop, and the
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68 first troubleshooting step is to adjust the LF Sum Loop VCO on A3A7.
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69
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70 To do this, one must open the loop of the PLL to be able to adjust the
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71 frequency-to-voltage curve of the VCO.
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72
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73 It took me a while to really understand the service manual on this point, as it explains:
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74
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75 Remove the two jumpers on the A3A7 VCO Assembly a n d plug the board back
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76 into its socket.
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77
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78 The problem is that there are no jumpers on that board... In fact, these
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79 jumpers exists, but are just soldered wires, and not, as one would expect,
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80 jumpers that can be easily unplugged.
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81
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82 Once I finally understood this, I've been able to perform this adjustment. This
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83 consists in tweaking two potentiometers to tune both ends of this
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84 frequency/voltage curve.
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85
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86 The ideal curve is (all frequencies are in MHz):
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87
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88 ===== =========== ========= =========
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89 Freq N-Loop VCO Sum L VCO FM SL VCO
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90 +/- 3MHz +/- 3MHz +/- .3MHz
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91 ===== =========== ========= =========
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92 320.0 122 120 10.0
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93 320.1 123 121 10.1
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94 320.2 124 122 10.2
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95 320.4 126 124 10.4
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96 320.8 130 128 10.8
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97 321.0 132 130 11
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98 322.0 142 140 12
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99 324.0 162 160 14
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100 328.0 202 200 18
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101 329.9 221 219 19.9
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102 ===== =========== ========= =========
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103
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104 As you can see, ideal curves are pretty linear.
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105
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106 At first, I could not find a correct set of tunings: when I was setting the two
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107 ends of the curve to their ideal values (120MHz and 219MHz), the values for
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108 324MHz and 328MHz did not match the +/- 3MHz criterion.
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109
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110 Here is the curve after I adjusted both ends to be as close as possible as
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111 their ideal values (the error is inversed to make the plot easier to read; most
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112 of the time, I am below the expected value):
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113
115
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114 .. plotly:: {static}/json/hp8662a_vco_sl.json
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115 :width: 800
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116 :height: 600
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117
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118 As you can see, the +/- 3MHz band is not achieved for most part of the curve.
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119 And it looks pretty bad since the max error is above 6MHz. However, I
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120 compensated this by overshooting these two points as much as possible in order
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121 to try to keep the whole curve within this +/- 3MHz band.
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122
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123 Unfortunately I haven't taken numerical values after this tuning, since this
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124 was enough to clear the Error 04.
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125
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126
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127 Other unstable PLLs
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128 ===================
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129
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130 After this adjustement, the generator seems to works fine: it does produces a
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131 nice output signal (well, I though) and gives no more error. But eventually,
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132 playing with the sweep controls, I found some pretty nasty behaviors at some
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133 ferquencies.
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134
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135 For example, at 100.3MHz, we have a decent signal:
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136
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137 .. image:: {static}/images/hp8662a/working_not_quite_3.jpg
101
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138 :class: image-process-large-photo
129
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139 :alt: generate a 100.3MHz signal
101
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140
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141 .. image:: {static}/images/hp8662a/working_not_quite_3_sa.jpg
101
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142 :class: image-process-large-photo
129
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143 :alt: 100.3MHz signal - spectrum
101
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144
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145 but at 101.0Mhz, it begins to looks pretty messy:
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146
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147 .. image:: {static}/images/hp8662a/working_not_quite_2.jpg
101
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148 :class: image-process-large-photo
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149 :alt: generate a 101.0MHz signal
101
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150
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151 .. image:: {static}/images/hp8662a/working_not_quite_2_sa.jpg
101
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152 :class: image-process-large-photo
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153 :alt: 101.0MHz signal - noisy spectrum
101
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154
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155 and 101.9Mhz shows "nice" side bands:
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156
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157 .. image:: {static}/images/hp8662a/working_not_quite.jpg
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158 :class: image-process-large-photo
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159 :alt: generate a 101.9MHz signal
101
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160
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161 .. image:: {static}/images/hp8662a/working_not_quite_sa.jpg
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162 :class: image-process-large-photo
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163 :alt: 101.9MHz signal - with spurious side bands
101
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164
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165 The problem seems quite clear: some PLL cannot lock at specific frequencies,
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166 but the strange thing is that this unlock PLL does not produces an error.
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167
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168 So I tried to figure out which boad assembly could be the culprit. With no
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169 error however, I had to troubleshoot without a procedure.
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170
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171 The funny thing was there was not clear 'pattern' of which frequencies produces
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172 the erratic behavior and which worked fine.
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173
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174 The problematic ranges were clearly cyclic upon the frequency range, but the
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175 limits were not very stable.
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176
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177 I spent a fait amount of time reading the service manual and reading the
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178 schematics to try to understand which board could be the culprit, and measuring
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179 value at any testpoint possible...
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180
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181 At the end, as I did not make any progress, I decided to try to make all the
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182 "post-reapir" adjustments related to the Low Frequency section.
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183
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184 And when I finally tuned the FM Sum Loop VCO, for the procedure is very similar
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185 to the Sum Loop VCO one, the problem disappeared.
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186
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187 For example, a 101MHz signal which was very unstable before now looks like:
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188
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189 .. image:: {static}/images/hp8662a/working_101.jpg
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190 :class: image-process-large-photo
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191 :alt: 101.0MHz signal - better spectrum

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