content/hp3562a_3.rst

Thu, 10 Nov 2022 19:15:24 +0100

author
David Douard <david.douard@sdf3.org>
date
Thu, 10 Nov 2022 19:15:24 +0100
changeset 146
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permissions
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Better fix for matomo integration

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1 ==========================================
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2 HP3562A Dynamic Signal Analyzer - Part 3
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3 ==========================================
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4
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5 :Author: David Douard
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6 :Category: Electronics
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7 :Tags: HP3562A, repair, test equipment, DSA
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8 :series: HP 3562A
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9 :series_index: 3
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10
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11 This is the part 3 of the series about my
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12 `HP 3562A Digital Signal Analyzer <{filename}/hp3562a.rst>`_,
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13 quickly describing the Analog Section of the instrument.
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14
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15
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16 Analog Section
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17 ==============
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18
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19 The analog section consist in 6 boards:
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20
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21 - A30: Analog Source
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22 - A31: Trigger
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23 - A32, A34: Input ADCs
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24 - A33, A35: Input
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25
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26 Analog Source
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27 -------------
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28
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29 .. image:: {static}/images/hp3562a/hp3562a_a30_block_diagram.png
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30 :alt: A30 - analog source block diagram
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31
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32 This board is mainly a DAC converting signal signal from the Digital
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33 Source board (for sin waves). It also generates Pseudo Random Noise
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34 and square waves (used for input calibration).
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35
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36 The analog signal produced by the DAC is filtered by a 100kHz low pass
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37 filter, then pass throught a step attenuator (5mV per step). The way
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38 this is implemented is quite interesting: the analog signal from the
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39 main DAC is used a reference voltage for a multiplying DAC.
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40
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41 .. image:: {static}/images/hp3562a/a30_analog_source.jpg
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42 :alt: A30 - PCB
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43
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44 .. image:: {static}/images/hp3562a/a30_analog_source_dac.jpg
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45 :alt: A30 - PCB (details)
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46
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47 Trigger
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48 -------
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49
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50 A first section of this board produces the trigger signal (for A1
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51 Digital Source and A5 Digital Filter boards) from one of the 4
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52 possible trigger sources: external, channel 1, channel 2 and the
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53 calibration.
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54
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55 .. image:: {static}/images/hp3562a/trigger_level.png
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56 :alt: A31 - Trigger circuit block diagram
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57
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58 The trigger clock circuit produces the 20.48MHz clock using a
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59 VCXO. From this signal are derived the 10.24MHz clock used by many
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60 boards (A1, A4, A5, A6, A30, A32 and A34) and the 256kHz clock signal
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61 used as internal sample signal.
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62
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63 When an external clock is provided, a PLL is used to lock this
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64 20.48MHz. The external signal can be 1, 2, 5 or the standard 10MHz.
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66 .. image:: {static}/images/hp3562a/trigger_clock.png
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67 :alt: A31 - Trigger circuit block diagram (ext ref)
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69 .. image:: {static}/images/hp3562a/a31_trigger.jpg
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70 :alt: A31 - Trigger PCB
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73 Input ADC
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74 ---------
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75
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77 :alt: A32 - ADC block diagram
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79 The ADC board converts analog data from the input board into 13-bits
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80 serial data words. The Analog to Digital convertion is done in 2
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81 passes by a 8-bits ADC. At each digitilization step, the signal value
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82 is frozen by a Track and Hold circuit. This frozen value is digitized
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83 (with a 8-bit resolution), then the digitized value is substracted
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84 from the input (hold) signal and the result is multiplied then
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85 digitized a second time to produce the remaining 5-bits of resolution.
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88 :alt: A32 - PCB
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91 :alt: A32 - PCB (details)
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94 Input
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95 -----
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97 .. image:: {static}/images/hp3562a/hp3562a_a33_block_diagram.png
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98 :alt: A33 - Input block diagram
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100 The input assembly implements the voltage ranges and conditions the
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101 input signal. It mostly consist in a pair switch attenuators (the
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102 input is balanced), followed by a pair of amplifier/signal
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103 conditionners. The balanced signal is then fed into a differential
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104 amplifier followed by a amplifier and an attenuator.
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105
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107 :alt: A33 - PCB
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109 Next
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110 ====
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111
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112 In the `next part <{filename}/hp3562a_4.rst>`_, we will describe the
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113 HP 1345A Digital Display used in the instrument.

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