--- a/content/hp3562a_3.rst Thu Nov 05 22:14:33 2020 +0100
+++ b/content/hp3562a_3.rst Thu Nov 05 22:15:16 2020 +0100
@@ -9,7 +9,7 @@
:series_index: 3
This is the part 3 of the series about my
-`HP 3562A Digital Signal Analyzer <{static}hp3562a.rst>`_,
+`HP 3562A Digital Signal Analyzer <{filename}/hp3562a.rst>`_,
quickly describing the Analog Section of the instrument.
@@ -26,7 +26,7 @@
Analog Source
-------------
-.. image:: {static}images/hp3562a/hp3562a_a30_block_diagram.png
+.. image:: {static}/images/hp3562a/hp3562a_a30_block_diagram.png
This board is mainly a DAC converting signal signal from the Digital
Source board (for sin waves). It also generates Pseudo Random Noise
@@ -37,9 +37,9 @@
this is implemented is quite interesting: the analog signal from the
main DAC is used a reference voltage for a multiplying DAC.
-.. image:: {static}images/hp3562a/a30_analog_source.jpg
+.. image:: {static}/images/hp3562a/a30_analog_source.jpg
-.. image:: {static}images/hp3562a/a30_analog_source_dac.jpg
+.. image:: {static}/images/hp3562a/a30_analog_source_dac.jpg
Trigger
-------
@@ -49,7 +49,7 @@
possible trigger sources: external, channel 1, channel 2 and the
calibration.
-.. image:: {static}images/hp3562a/trigger_level.png
+.. image:: {static}/images/hp3562a/trigger_level.png
The trigger clock circuit produces the 20.48MHz clock using a
VCXO. From this signal are derived the 10.24MHz clock used by many
@@ -59,15 +59,15 @@
When an external clock is provided, a PLL is used to lock this
20.48MHz. The external signal can be 1, 2, 5 or the standard 10MHz.
-.. image:: {static}images/hp3562a/trigger_clock.png
+.. image:: {static}/images/hp3562a/trigger_clock.png
-.. image:: {static}images/hp3562a/a31_trigger.jpg
+.. image:: {static}/images/hp3562a/a31_trigger.jpg
Input ADC
---------
-.. image:: {static}images/hp3562a/hp3562a_a32_block_diagram.png
+.. image:: {static}/images/hp3562a/hp3562a_a32_block_diagram.png
The ADC board converts analog data from the input board into 13-bits
@@ -78,14 +78,14 @@
from the input (hold) signal and the result is multiplied then
digitized a second time to produce the remaining 5-bits of resolution.
-.. image:: {static}images/hp3562a/a32_input_adc.jpg
-.. image:: {static}images/hp3562a/a32_input_adc_bb.jpg
+.. image:: {static}/images/hp3562a/a32_input_adc.jpg
+.. image:: {static}/images/hp3562a/a32_input_adc_bb.jpg
Input
-----
-.. image:: {static}images/hp3562a/hp3562a_a33_block_diagram.png
+.. image:: {static}/images/hp3562a/hp3562a_a33_block_diagram.png
The input assembly implements the voltage ranges and conditions the
input signal. It mostly consist in a pair switch attenuators (the
@@ -93,11 +93,11 @@
conditionners. The balanced signal is then fed into a differential
amplifier followed by a amplifier and an attenuator.
-.. image:: {static}images/hp3562a/a33_input.jpg
+.. image:: {static}/images/hp3562a/a33_input.jpg
Next
====
-In the `next part <{static}hp3562a_4.rst>`_, we will describe the
+In the `next part <{filename}/hp3562a_4.rst>`_, we will describe the
HP 1345A Digital Display used in the instrument.