# HG changeset patch
# User David Douard <david.douard@sdf3.org>
# Date 1604615319 -3600
# Node ID 42a19a0d1c991c590aaffe0dbdace5e0a22d66cd
# Parent  aba381b2bac98af4826fe31b89113e0e77275570
Add a few missing :alt: to images

far from being done everywhere however...

diff -r aba381b2bac9 -r 42a19a0d1c99 content/hp3562a_3.rst
--- a/content/hp3562a_3.rst	Thu Nov 05 22:15:16 2020 +0100
+++ b/content/hp3562a_3.rst	Thu Nov 05 23:28:39 2020 +0100
@@ -27,6 +27,7 @@
 -------------
 
 .. image:: {static}/images/hp3562a/hp3562a_a30_block_diagram.png
+   :alt: A30 - analog source block diagram
 
 This board is mainly a DAC converting signal signal from the Digital
 Source board (for sin waves). It also generates Pseudo Random Noise
@@ -38,8 +39,10 @@
 main DAC is used a reference voltage for a multiplying DAC.
 
 .. image:: {static}/images/hp3562a/a30_analog_source.jpg
+   :alt: A30 - PCB
 
 .. image:: {static}/images/hp3562a/a30_analog_source_dac.jpg
+   :alt: A30 - PCB (details)
 
 Trigger
 -------
@@ -50,6 +53,7 @@
 calibration.
 
 .. image:: {static}/images/hp3562a/trigger_level.png
+   :alt: A31 - Trigger circuit block diagram
 
 The trigger clock circuit produces the 20.48MHz clock using a
 VCXO. From this signal are derived the 10.24MHz clock used by many
@@ -60,15 +64,17 @@
 20.48MHz. The external signal can be 1, 2, 5 or the standard 10MHz.
 
 .. image:: {static}/images/hp3562a/trigger_clock.png
+   :alt: A31 - Trigger circuit block diagram (ext ref)
 
 .. image:: {static}/images/hp3562a/a31_trigger.jpg
+   :alt: A31 - Trigger PCB
 
 
 Input ADC
 ---------
 
 .. image:: {static}/images/hp3562a/hp3562a_a32_block_diagram.png
-
+   :alt: A32 - ADC block diagram
 
 The ADC board converts analog data from the input board into 13-bits
 serial data words. The Analog to Digital convertion is done in 2
@@ -79,13 +85,17 @@
 digitized a second time to produce the remaining 5-bits of resolution.
 
 .. image:: {static}/images/hp3562a/a32_input_adc.jpg
+   :alt: A32 - PCB
+
 .. image:: {static}/images/hp3562a/a32_input_adc_bb.jpg
+   :alt: A32 - PCB (details)
 
 
 Input
 -----
 
 .. image:: {static}/images/hp3562a/hp3562a_a33_block_diagram.png
+   :alt: A33 - Input block diagram
 
 The input assembly implements the voltage ranges and conditions the
 input signal. It mostly consist in a pair switch attenuators (the
@@ -94,7 +104,7 @@
 amplifier followed by a amplifier and an attenuator.
 
 .. image:: {static}/images/hp3562a/a33_input.jpg
-
+   :alt: A33 - PCB
 
 Next
 ====
diff -r aba381b2bac9 -r 42a19a0d1c99 content/hp8662a_3.rst
--- a/content/hp8662a_3.rst	Thu Nov 05 22:15:16 2020 +0100
+++ b/content/hp8662a_3.rst	Thu Nov 05 23:28:39 2020 +0100
@@ -26,6 +26,7 @@
 
 .. image:: {static}/images/hp8662a/LF_block_diagram.png
    :class: image-process-large-photo
+   :alt: LF block diagram
 
 This Low Frequency Section consists in no less than 4 phase locked loops in
 order to achieve adjustable frequency synthesis with the expected stability and
@@ -57,6 +58,7 @@
 
 .. image:: {static}/images/hp8662a/sheet_H.png
    :class: image-process-large-photo
+   :alt: LF detailed block diagram
 
 
 Fixing the Error 04
@@ -134,25 +136,31 @@
 
 .. image:: {static}/images/hp8662a/working_not_quite_3.jpg
    :class: image-process-large-photo
+   :alt: generate a 100.3MHz signal
 
 .. image:: {static}/images/hp8662a/working_not_quite_3_sa.jpg
    :class: image-process-large-photo
+   :alt: 100.3MHz signal - spectrum
 
 but at 101.0Mhz, it begins to looks pretty messy:
 
 .. image:: {static}/images/hp8662a/working_not_quite_2.jpg
    :class: image-process-large-photo
+   :alt: generate a 101.0MHz signal
 
 .. image:: {static}/images/hp8662a/working_not_quite_2_sa.jpg
    :class: image-process-large-photo
+   :alt: 101.0MHz signal - noisy spectrum
 
 and 101.9Mhz shows "nice" side bands:
 
 .. image:: {static}/images/hp8662a/working_not_quite.jpg
    :class: image-process-large-photo
+   :alt: generate a 101.9MHz signal
 
 .. image:: {static}/images/hp8662a/working_not_quite_sa.jpg
    :class: image-process-large-photo
+   :alt: 101.9MHz signal - with spurious side bands
 
 The problem seems quite clear: some PLL cannot lock at specific frequencies,
 but the strange thing is that this unlock PLL does not produces an error.
@@ -180,3 +188,4 @@
 
 .. image:: {static}/images/hp8662a/working_101.jpg
    :class: image-process-large-photo
+   :alt: 101.0MHz signal - better spectrum