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| 1 ========================================== | |
| 2 HP3562A Dynamic Signal Analyzer - Part 2 | |
| 3 ========================================== | |
| 4 | |
| 5 :Author: David Douard | |
| 6 :Category: Electronics | |
| 7 :Tags: HP3562A, repair, test equipment, DSA | |
| 8 :series: HP 3562A | |
| 9 :series_index: 2 | |
| 10 | |
| 11 This is the part 2 of the series about my | |
| 12 `HP 3562A Digital Signal Analyzer <{filename}hp3562a.rst>`_, | |
| 13 quickly describing the Digital Section of the instrument. | |
| 14 | |
| 15 | |
| 16 Digital Section | |
| 17 =============== | |
| 18 | |
| 19 The unit is quite capable, since the main CPU is a 68000 (not exactly | |
| 20 of small CPU for the time). | |
| 21 | |
| 22 .. image:: {filename}images/hp3562a/cpu.jpg | |
| 23 | |
| 24 The 8 boards are: | |
| 25 | |
| 26 - A1: Digital source and front-end interface (rev B, ref: 03562-66501) | |
| 27 - A2: CPU & GPIB controller (rev D, ref: 03562-66502) | |
| 28 - A3: Memory (rev B, ref: 03562-66538) | |
| 29 - A4: Local oscillator (rev C, ref: 03562-66504) | |
| 30 - A5: Digital filter (rev B, ref: 03562-66505) | |
| 31 - A6: Digital filter controller (rev D, ref: 03562-66506) | |
| 32 - A7: Floating Point Processor (FPP) (rev B, ref: 03562-66507) | |
| 33 - A9: FFT (rev B, ref: 03562-66509) | |
| 34 | |
| 35 The service manual also describes an A8 board with additional RAM, but | |
| 36 my device does not have such a board. It looks to me that my version | |
| 37 of the DSA has both extra ROM and RAM on the A3 memory board. | |
| 38 | |
| 39 | |
| 40 Digital Source | |
| 41 -------------- | |
| 42 | |
| 43 .. Note:: The Service Manual available on the net lacks a few pages in | |
| 44 the Digital Source section, so I do not have details on the | |
| 45 Timing Control section. | |
| 46 | |
| 47 .. image:: {filename}images/hp3562a/hp3562a_a1_block_diagram.png | |
| 48 :alt: Block diagram of the A1 Digital Source Board | |
| 49 | |
| 50 This board is mainly responsible for generating the digital signals | |
| 51 that are used as input for the source DAC. It generates all sort of | |
| 52 noise figures, bursts, sweeps, and so on. | |
| 53 | |
| 54 .. image:: {filename}images/hp3562a/a1_digital_source.jpg | |
| 55 | |
| 56 The Timing Control section looks like: | |
| 57 | |
| 58 .. image:: {filename}images/hp3562a/hp3562a_a1_timing_control_circuit.png | |
| 59 :alt: A1 Timing Control block diagram | |
| 60 | |
| 61 The Phase Resolution is used in external and internal triggered | |
| 62 measurements, ensuring that the phase of a triggered measurement is | |
| 63 accurate. Since the trigger moment does not always occur on a sample | |
| 64 and hold edge, there is a time delay and phase error in the data. | |
| 65 This phase resolution circuit counts the time between the samples and | |
| 66 a trigger. | |
| 67 | |
| 68 .. image:: {filename}images/hp3562a/hp3562a_a1_phase_resolution_circuit.png | |
| 69 :alt: A1 Phase Resolution block diagram | |
| 70 | |
| 71 The Burst Control circuit controls the burst length and generates the | |
| 72 pulse signal to the Local Oscillator (A4). It provides the gating | |
| 73 signal that gates the analog source on and off during the burst and | |
| 74 chirp modes. | |
| 75 | |
| 76 .. image:: {filename}images/hp3562a/hp3562a_a1_burst_control_circuit.png | |
| 77 :alt: A1 Burst Control block diagram | |
| 78 | |
| 79 | |
| 80 Other parts of this board are the LO Input Receiver that synchronizes | |
| 81 the local oscillator input data to the sample rate, the Multiplier | |
| 82 that multiply the LO data by the noise and send it to the analog | |
| 83 source, and the Noise Generator that produces binary random sequences | |
| 84 that is used for band-limited random noise and burst noise signals. | |
| 85 | |
| 86 | |
| 87 CPU | |
| 88 --- | |
| 89 | |
| 90 The processing unit is a MC68000. It aims at telling each assembly | |
| 91 which process to execute and monitor the overall functionning and data | |
| 92 processing of the instrument. | |
| 93 | |
| 94 .. image:: {filename}images/hp3562a/hp3562a_a2_block_diagram.png | |
| 95 | |
| 96 The main CPU board, with the beautiful MC68000P9 DIP64 package: | |
| 97 | |
| 98 .. image:: {filename}images/hp3562a/a2_cpu.jpg | |
| 99 | |
| 100 It comes with 2 populated M5M256BP static ram chips (32k x 8bits), for | |
| 101 the CPU, but seems to be capable of holding 4 more of them. The CPU | |
| 102 runs at 8MHz. | |
| 103 | |
| 104 There is also some ROM, the main "boot loader" program. Unfortunately, | |
| 105 neither of the ROM chips are mounted on sockets but are directly | |
| 106 soldered on the PCBs, so I did not took the risk of damaging one of | |
| 107 them by desoldering them for dumping their content. | |
| 108 | |
| 109 Most of the remaining of the circuit is to manage the global data bus, | |
| 110 the system bus, the IRQs and the GPIB bus. | |
| 111 | |
| 112 The blue connector is for the GPIB connector. | |
| 113 | |
| 114 | |
| 115 Memory | |
| 116 ------ | |
| 117 | |
| 118 .. image:: {filename}images/hp3562a/a38_memory.jpg | |
| 119 | |
| 120 This board is described as an "extension of the read only memory of | |
| 121 the system CPU board" and read/write memory used by most of the other | |
| 122 assemblies. | |
| 123 | |
| 124 .. image:: {filename}images/hp3562a/hp3562a_a38_memory_block_diagram.png | |
| 125 | |
| 126 The ROM section stores most programs for the HP 3562A except the | |
| 127 startup routines (which are on the ROM ships of the A2 CPU | |
| 128 bloard). | |
| 129 | |
| 130 The board allows flexibility in the number and type of ROM chipes | |
| 131 used. ROM density is selected by placement of jumpers. | |
| 132 | |
| 133 .. image:: {filename}images/hp3562a/hp3562a_a38_rom_block_diagram.png | |
| 134 | |
| 135 | |
| 136 The RAM section of the assembly consist of 4 32k by 8 bits static RAM | |
| 137 chips as well as the arbitrer section which controls access requests | |
| 138 to the global RAM from six devices (FFT, both Digital Filters, | |
| 139 Display, FPP and the system CPU). | |
| 140 | |
| 141 .. image:: {filename}images/hp3562a/hp3562a_a38_ram_block_diagram.png | |
| 142 | |
| 143 The Display Controller section also lies on this A38 board. | |
| 144 | |
| 145 .. Note:: On older versions of the instruments, this board was | |
| 146 splitted in 2 (A3 and A8) and used less dense chips (thus, much more | |
| 147 chips). | |
| 148 | |
| 149 | |
| 150 Local Oscillator | |
| 151 ---------------- | |
| 152 | |
| 153 The Local Oscillator produces digital sin and cosine signals | |
| 154 (synchronized with the sample rate). The sinusoidal signal is | |
| 155 generated from a table of values stored in the ROM. | |
| 156 | |
| 157 .. image:: {filename}images/hp3562a/hp3562a_a4_block_diagram.png | |
| 158 | |
| 159 .. image:: {filename}images/hp3562a/a4_loc.jpg | |
| 160 | |
| 161 | |
| 162 | |
| 163 Digital Filter and Digital Filter Controller | |
| 164 -------------------------------------------- | |
| 165 | |
| 166 The Digital Filter Assembly consists in both A5 and A6. It processes | |
| 167 two channels of serial data coming from the instrument front end (ADC) | |
| 168 ans stores the results in global RAM. Processing consists of | |
| 169 conversion from a serial format to a parallel format and, if required, | |
| 170 digital filtering or zoom (a combination of frequency shifting and | |
| 171 filtering). The processed data is transferred on the global data bus. | |
| 172 | |
| 173 .. figure:: {filename}images/hp3562a/a5_a6_block_diagram.png | |
| 174 :alt: Digital Filter Assembly block diagram | |
| 175 | |
| 176 Digital Filter Assembly block diagram. | |
| 177 | |
| 178 **Digital Filter:** Each digital filter consists of a control IC and 2 | |
| 179 filter ICs, one for the real data and one for the imaginary data. | |
| 180 | |
| 181 .. figure:: {filename}images/hp3562a/a6_zoom.png | |
| 182 :alt: Digital Filter for the zoom mode | |
| 183 | |
| 184 The Digital Filters are fed with a kind of LF I/Q demodulator, used | |
| 185 for zooming or actual digital filtering. | |
| 186 | |
| 187 | |
| 188 .. figure:: {filename}images/hp3562a/a5_filter.jpg | |
| 189 :alt: Picture of the A5 Digital Filter board | |
| 190 | |
| 191 Picture of the A5 Digital Filter board. | |
| 192 | |
| 193 .. figure:: {filename}images/hp3562a/hp3562a_a5_block_diagram.png | |
| 194 :alt: Digital Filter block diagram | |
| 195 | |
| 196 The A5 Digital Filter board block diagram. | |
| 197 | |
| 198 | |
| 199 **Clock Generator:** The clock generator creates two complementary clock | |
| 200 pulses from the 10.24MHz system clock. | |
| 201 | |
| 202 **Overload Detect:** The first 3 bits in the ADC serial data stream | |
| 203 contain overrange information that must be stripped off the serial | |
| 204 data. | |
| 205 | |
| 206 | |
| 207 .. figure:: {filename}images/hp3562a/a6_control.jpg | |
| 208 :alt: Picture of the A6 Digital Filter Control board | |
| 209 | |
| 210 Picture of the A6 Digital Filter Control board. | |
| 211 | |
| 212 .. figure:: {filename}images/hp3562a/a6_block_diagram.png | |
| 213 :alt: Digital Filter Controller block diagram | |
| 214 | |
| 215 The A6 Digital Filter Controller board block diagram. | |
| 216 | |
| 217 | |
| 218 FPP | |
| 219 --- | |
| 220 | |
| 221 The Floating Point Processor board is a fast arithmetic unit which | |
| 222 carries out real and complex arithmetic operations on blocks of data | |
| 223 stored in the global RAM. The processing ALUs are six AM2903 bit-slice | |
| 224 microprocessor ICs and one AM2910 microprogram | |
| 225 controller. Instructions are provided to the ALUs by an address | |
| 226 sequencer and seven microcode PROMs. | |
| 227 | |
| 228 .. figure:: {filename}images/hp3562a/hp3562a_a7_block_diagram.png | |
| 229 :alt: Floating Point Processor block diagram | |
| 230 :align: center | |
| 231 | |
| 232 Floating Point Processor block diagram. | |
| 233 | |
| 234 .. figure:: {filename}images/hp3562a/a7_fpp.jpg | |
| 235 :alt: Picture of the A7 FPP board | |
| 236 :align: center | |
| 237 | |
| 238 Picture of the A7 FPP board. | |
| 239 | |
| 240 This Floating Point Processor is capable of handling 16 bits integers, | |
| 241 32 bits and 64 bits floats. | |
| 242 | |
| 243 | |
| 244 FFT | |
| 245 --- | |
| 246 | |
| 247 .. image:: {filename}images/hp3562a/hp3562a_a9_block_diagram.png | |
| 248 | |
| 249 The FFT board performs windowing, FFT and Inverse FFT directly from | |
| 250 and to the RAM. | |
| 251 It's built around a TMS230 microprocessor runningat 5MHz | |
| 252 | |
| 253 .. image:: {filename}images/hp3562a/a9_fft.jpg | |
| 254 | |
| 255 | |
| 256 Keyboard | |
| 257 -------- | |
| 258 | |
| 259 .. image:: {filename}images/hp3562a/hp3562a_a15_block_diagram.png | |
| 260 | |
| 261 | |
| 262 Next | |
| 263 ==== | |
| 264 | |
| 265 In the `next part <{filename}hp3562a_3.rst>`_, we will describe the | |
| 266 Analog Section of the instrument. |
