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| 1 =============================================== | |
| 2 HP8662A Synthetized Signal Generator - Part 3 | |
| 3 =============================================== | |
| 4 | |
| 5 :Author: David Douard | |
| 6 :Category: Electronics | |
| 7 :Tags: HP8662A, repair, test equipment, HP, Generator, RF | |
| 8 :series: HP 8662A | |
| 9 :series_index: 3 | |
| 10 | |
| 11 | |
| 12 This is the part 3 on my series about my HP 8662A Signal Generator, and is | |
| 13 about the third main problems I found with this unit, as evocated in `part | |
| 14 2 <{filename}hp8662a_2.rst>`_: Error 04 is lit and there are some very | |
| 15 unpleasant spectrums at some frequencies. | |
| 16 | |
| 17 | |
| 18 Low Fequency Section | |
| 19 ==================== | |
| 20 | |
| 21 If the generator is now able to produce a signal (the AM and FM modulations | |
| 22 also work), it also gives an Error 04, which is described in the Service Manual | |
| 23 as "Sum Loop Unlocked (Low Frequency Section)", and the troubleshooting | |
| 24 procedure to follow in on the Service Sheet H. The general block diagram of | |
| 25 this section is as follow: | |
| 26 | |
| 27 .. image:: {filename}images/hp8662a/LF_block_diagram.png | |
| 28 :class: image-process-large-photo | |
| 29 | |
| 30 This Low Frequency Section consists in no less than 4 phase locked loops in | |
| 31 order to achieve adjustable frequency synthesis with the expected stability and | |
| 32 resolution. | |
| 33 | |
| 34 In fact, when in the main band of the generator, ie. when neither the output | |
| 35 frequency doubler nor the down converter are in the signal path (that is, when | |
| 36 the frequency range is between 120MHz and 640MHz). The frequency display | |
| 37 consists in 11 digits, named DF0 to DF10, which are segmented to control | |
| 38 several sets of PLLs: | |
| 39 | |
| 40 :DF0 - DF2: are the fractional part of the fractional N-Loop (.1Hz, 1Hz and | |
| 41 10Hz digits), | |
| 42 | |
| 43 :DF3 - DF5: are the integer part of the fractional N-loop (100Hz, 1kHz and | |
| 44 10kHz resolutions) | |
| 45 | |
| 46 :DF6 - DF7: are used to set the pretune VCO value for the sum loop VCO (A3A7), | |
| 47 the FM sum loop VCO (A3A8) as well as the N-Loop VCO (A3A4). These | |
| 48 are the 0.1MHz and 1MHz resolution digits. | |
| 49 | |
| 50 :DF8 - DF9: these control the high frequency section (DF10 can only be 0 or 1, | |
| 51 in which case the frequency doubler is used). | |
| 52 | |
| 53 | |
| 54 Here is a more detailed vue of the block diagram of the low frequency section: | |
| 55 | |
| 56 .. image:: {filename}images/hp8662a/sheet_H.png | |
| 57 :class: image-process-large-photo | |
| 58 | |
| 59 | |
| 60 Fixing the Error 04 | |
| 61 =================== | |
| 62 | |
| 63 The service manual describes the Error 04 as related to the Sum Loop, and the | |
| 64 first troubleshooting step is to adjust the LF Sum Loop VCO on A3A7. | |
| 65 | |
| 66 To do this, one must open the loop of the PLL to be able to adjust the | |
| 67 frequency-to-voltage curve of the VCO. | |
| 68 | |
| 69 It took me a while to really understand the service manual on this point, as it explains: | |
| 70 | |
| 71 Remove the two jumpers on the A3A7 VCO Assembly a n d plug the board back | |
| 72 into its socket. | |
| 73 | |
| 74 The problem is that there are no jumpers on that board... In fact, these | |
| 75 jumpers exists, but are just soldered wires, and not, as one would expect, | |
| 76 jumpers that can be easily unplugged. | |
| 77 | |
| 78 Once I finally understood this, I've been able to perform this adjustment. This | |
| 79 consists in tweaking two potentiometers to tune both ends of this | |
| 80 frequency/voltage curve. | |
| 81 | |
| 82 The ideal curve is (all frequencies are in MHz): | |
| 83 | |
| 84 ===== =========== ========= ========= | |
| 85 Freq N-Loop VCO Sum L VCO FM SL VCO | |
| 86 +/- 3MHz +/- 3MHz +/- .3MHz | |
| 87 ===== =========== ========= ========= | |
| 88 320.0 122 120 10.0 | |
| 89 320.1 123 121 10.1 | |
| 90 320.2 124 122 10.2 | |
| 91 320.4 126 124 10.4 | |
| 92 320.8 130 128 10.8 | |
| 93 321.0 132 130 11 | |
| 94 322.0 142 140 12 | |
| 95 324.0 162 160 14 | |
| 96 328.0 202 200 18 | |
| 97 329.9 221 219 19.9 | |
| 98 ===== =========== ========= ========= | |
| 99 | |
| 100 As you can see, ideal curves are pretty linear. | |
| 101 | |
| 102 At first, I could not find a correct set of tunings: when I was setting the two | |
| 103 ends of the curve to their ideal values (120MHz and 219MHz), the values for | |
| 104 324MHz and 328MHz did not match the +/- 3MHz criterion. | |
| 105 | |
| 106 Here is the curve after I adjusted both ends to be as close as possible as | |
| 107 their ideal values (the error is inversed to make the plot easier to read; most | |
| 108 of the time, I am below the expected value): | |
| 109 | |
| 110 .. plotly:: {filename}/json/hp8662a_vco_sl.json | |
| 111 :width: 800 | |
| 112 :height: 600 | |
| 113 | |
| 114 As you can see, the +/- 3MHz band is not achieved for most part of the curve. | |
| 115 And it looks pretty bad since the max error is above 6MHz. However, I | |
| 116 compensated this by overshooting these two points as much as possible in order | |
| 117 to try to keep the whole curve within this +/- 3MHz band. | |
| 118 | |
| 119 Unfortunately I haven't taken numerical values after this tuning, since this | |
| 120 was enough to clear the Error 04. | |
| 121 | |
| 122 | |
| 123 Other unstable PLLs | |
| 124 =================== | |
| 125 | |
| 126 After this adjustement, the generator seems to works fine: it does produces a | |
| 127 nice output signal (well, I though) and gives no more error. But eventually, | |
| 128 playing with the sweep controls, I found some pretty nasty behaviors at some | |
| 129 ferquencies. | |
| 130 | |
| 131 For example, at 100.3MHz, we have a decent signal: | |
| 132 | |
| 133 .. image:: {filename}/images/hp8662a/working_not_quite_3.jpg | |
| 134 :class: image-process-large-photo | |
| 135 | |
| 136 .. image:: {filename}/images/hp8662a/working_not_quite_3_sa.jpg | |
| 137 :class: image-process-large-photo | |
| 138 | |
| 139 but at 101.0Mhz, it begins to looks pretty messy: | |
| 140 | |
| 141 .. image:: {filename}/images/hp8662a/working_not_quite_2.jpg | |
| 142 :class: image-process-large-photo | |
| 143 | |
| 144 .. image:: {filename}/images/hp8662a/working_not_quite_2_sa.jpg | |
| 145 :class: image-process-large-photo | |
| 146 | |
| 147 and 101.9Mhz shows "nice" side bands: | |
| 148 | |
| 149 .. image:: {filename}/images/hp8662a/working_not_quite.jpg | |
| 150 :class: image-process-large-photo | |
| 151 | |
| 152 .. image:: {filename}/images/hp8662a/working_not_quite_sa.jpg | |
| 153 :class: image-process-large-photo | |
| 154 | |
| 155 The problem seems quite clear: some PLL cannot lock at specific frequencies, | |
| 156 but the strange thing is that this unlock PLL does not produces an error. | |
| 157 | |
| 158 So I tried to figure out which boad assembly could be the culprit. With no | |
| 159 error however, I had to troubleshoot without a procedure. | |
| 160 | |
| 161 The funny thing was there was not clear 'pattern' of which frequencies produces | |
| 162 the erratic behavior and which worked fine. | |
| 163 | |
| 164 The problematic ranges were clearly cyclic upon the frequency range, but the | |
| 165 limits were not very stable. | |
| 166 | |
| 167 I spent a fait amount of time reading the service manual and reading the | |
| 168 schematics to try to understand which board could be the culprit, and measuring | |
| 169 value at any testpoint possible... | |
| 170 | |
| 171 At the end, as I did not make any progress, I decided to try to make all the | |
| 172 "post-reapir" adjustments related to the Low Frequency section. | |
| 173 | |
| 174 And when I finally tuned the FM Sum Loop VCO, for the procedure is very similar | |
| 175 to the Sum Loop VCO one, the problem disappeared. | |
| 176 | |
| 177 For example, a 101MHz signal which was very unstable before now looks like: | |
| 178 | |
| 179 .. image:: {filename}/images/hp8662a/working_101.jpg | |
| 180 :class: image-process-large-photo |
