comparison: content/hp3562a_3.rst
content/hp3562a_3.rst
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| 25 | 25 |
| 26 Analog Source | 26 Analog Source |
| 27 ------------- | 27 ------------- |
| 28 | 28 |
| 29 .. image:: {static}/images/hp3562a/hp3562a_a30_block_diagram.png | 29 .. image:: {static}/images/hp3562a/hp3562a_a30_block_diagram.png |
| 30 :alt: A30 - analog source block diagram | |
| 30 | 31 |
| 31 This board is mainly a DAC converting signal signal from the Digital | 32 This board is mainly a DAC converting signal signal from the Digital |
| 32 Source board (for sin waves). It also generates Pseudo Random Noise | 33 Source board (for sin waves). It also generates Pseudo Random Noise |
| 33 and square waves (used for input calibration). | 34 and square waves (used for input calibration). |
| 34 | 35 |
| 36 filter, then pass throught a step attenuator (5mV per step). The way | 37 filter, then pass throught a step attenuator (5mV per step). The way |
| 37 this is implemented is quite interesting: the analog signal from the | 38 this is implemented is quite interesting: the analog signal from the |
| 38 main DAC is used a reference voltage for a multiplying DAC. | 39 main DAC is used a reference voltage for a multiplying DAC. |
| 39 | 40 |
| 40 .. image:: {static}/images/hp3562a/a30_analog_source.jpg | 41 .. image:: {static}/images/hp3562a/a30_analog_source.jpg |
| 42 :alt: A30 - PCB | |
| 41 | 43 |
| 42 .. image:: {static}/images/hp3562a/a30_analog_source_dac.jpg | 44 .. image:: {static}/images/hp3562a/a30_analog_source_dac.jpg |
| 45 :alt: A30 - PCB (details) | |
| 43 | 46 |
| 44 Trigger | 47 Trigger |
| 45 ------- | 48 ------- |
| 46 | 49 |
| 47 A first section of this board produces the trigger signal (for A1 | 50 A first section of this board produces the trigger signal (for A1 |
| 48 Digital Source and A5 Digital Filter boards) from one of the 4 | 51 Digital Source and A5 Digital Filter boards) from one of the 4 |
| 49 possible trigger sources: external, channel 1, channel 2 and the | 52 possible trigger sources: external, channel 1, channel 2 and the |
| 50 calibration. | 53 calibration. |
| 51 | 54 |
| 52 .. image:: {static}/images/hp3562a/trigger_level.png | 55 .. image:: {static}/images/hp3562a/trigger_level.png |
| 56 :alt: A31 - Trigger circuit block diagram | |
| 53 | 57 |
| 54 The trigger clock circuit produces the 20.48MHz clock using a | 58 The trigger clock circuit produces the 20.48MHz clock using a |
| 55 VCXO. From this signal are derived the 10.24MHz clock used by many | 59 VCXO. From this signal are derived the 10.24MHz clock used by many |
| 56 boards (A1, A4, A5, A6, A30, A32 and A34) and the 256kHz clock signal | 60 boards (A1, A4, A5, A6, A30, A32 and A34) and the 256kHz clock signal |
| 57 used as internal sample signal. | 61 used as internal sample signal. |
| 58 | 62 |
| 59 When an external clock is provided, a PLL is used to lock this | 63 When an external clock is provided, a PLL is used to lock this |
| 60 20.48MHz. The external signal can be 1, 2, 5 or the standard 10MHz. | 64 20.48MHz. The external signal can be 1, 2, 5 or the standard 10MHz. |
| 61 | 65 |
| 62 .. image:: {static}/images/hp3562a/trigger_clock.png | 66 .. image:: {static}/images/hp3562a/trigger_clock.png |
| 67 :alt: A31 - Trigger circuit block diagram (ext ref) | |
| 63 | 68 |
| 64 .. image:: {static}/images/hp3562a/a31_trigger.jpg | 69 .. image:: {static}/images/hp3562a/a31_trigger.jpg |
| 70 :alt: A31 - Trigger PCB | |
| 65 | 71 |
| 66 | 72 |
| 67 Input ADC | 73 Input ADC |
| 68 --------- | 74 --------- |
| 69 | 75 |
| 70 .. image:: {static}/images/hp3562a/hp3562a_a32_block_diagram.png | 76 .. image:: {static}/images/hp3562a/hp3562a_a32_block_diagram.png |
| 71 | 77 :alt: A32 - ADC block diagram |
| 72 | 78 |
| 73 The ADC board converts analog data from the input board into 13-bits | 79 The ADC board converts analog data from the input board into 13-bits |
| 74 serial data words. The Analog to Digital convertion is done in 2 | 80 serial data words. The Analog to Digital convertion is done in 2 |
| 75 passes by a 8-bits ADC. At each digitilization step, the signal value | 81 passes by a 8-bits ADC. At each digitilization step, the signal value |
| 76 is frozen by a Track and Hold circuit. This frozen value is digitized | 82 is frozen by a Track and Hold circuit. This frozen value is digitized |
| 77 (with a 8-bit resolution), then the digitized value is substracted | 83 (with a 8-bit resolution), then the digitized value is substracted |
| 78 from the input (hold) signal and the result is multiplied then | 84 from the input (hold) signal and the result is multiplied then |
| 79 digitized a second time to produce the remaining 5-bits of resolution. | 85 digitized a second time to produce the remaining 5-bits of resolution. |
| 80 | 86 |
| 81 .. image:: {static}/images/hp3562a/a32_input_adc.jpg | 87 .. image:: {static}/images/hp3562a/a32_input_adc.jpg |
| 88 :alt: A32 - PCB | |
| 89 | |
| 82 .. image:: {static}/images/hp3562a/a32_input_adc_bb.jpg | 90 .. image:: {static}/images/hp3562a/a32_input_adc_bb.jpg |
| 91 :alt: A32 - PCB (details) | |
| 83 | 92 |
| 84 | 93 |
| 85 Input | 94 Input |
| 86 ----- | 95 ----- |
| 87 | 96 |
| 88 .. image:: {static}/images/hp3562a/hp3562a_a33_block_diagram.png | 97 .. image:: {static}/images/hp3562a/hp3562a_a33_block_diagram.png |
| 98 :alt: A33 - Input block diagram | |
| 89 | 99 |
| 90 The input assembly implements the voltage ranges and conditions the | 100 The input assembly implements the voltage ranges and conditions the |
| 91 input signal. It mostly consist in a pair switch attenuators (the | 101 input signal. It mostly consist in a pair switch attenuators (the |
| 92 input is balanced), followed by a pair of amplifier/signal | 102 input is balanced), followed by a pair of amplifier/signal |
| 93 conditionners. The balanced signal is then fed into a differential | 103 conditionners. The balanced signal is then fed into a differential |
| 94 amplifier followed by a amplifier and an attenuator. | 104 amplifier followed by a amplifier and an attenuator. |
| 95 | 105 |
| 96 .. image:: {static}/images/hp3562a/a33_input.jpg | 106 .. image:: {static}/images/hp3562a/a33_input.jpg |
| 97 | 107 :alt: A33 - PCB |
| 98 | 108 |
| 99 Next | 109 Next |
| 100 ==== | 110 ==== |
| 101 | 111 |
| 102 In the `next part <{filename}/hp3562a_4.rst>`_, we will describe the | 112 In the `next part <{filename}/hp3562a_4.rst>`_, we will describe the |
