content/eip545b_4.rst

Thu, 10 Nov 2022 16:45:50 +0100

author
David Douard <david.douard@sdf3.org>
date
Thu, 10 Nov 2022 16:45:50 +0100
changeset 141
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parent 128
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permissions
-rw-r--r--

Fix a pelican warning on why.rst

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1 ========================================
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2 EIP 545B RF Frequency Counter - Part 4
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3 ========================================
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4
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5 :author: David Douard
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6 :Category: Electronics
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7 :Tags: test equipment, RF, EIP, 545, 545A, 545B, 575A, 578A, counter
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8 :series: EIP545B Frequency Counter
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9 :series_index: 4
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10
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11
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12 This part is about my attempt to modify the firmware to "fix" the problem of
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13 weird intial setup: a -160MHz offset and a resolution set to 5 digits.
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14
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15 In the `previous part <{filename}/eip545b_3.rst>`_, we figured some probable
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16 spots in the firware where these default setup configurations might be set.
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17
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18 EPROM checksums
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19 ===============
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20
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21 In order to be able to modify the content od the firmware without generating an
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22 error at startup, we must understand how checksum are computed.
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23
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24 The Service Manual for the 578B does not explain how it is computed. The one
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25 for the 545A gives a clue but is not valid for the 545B: in the Option 2 (power
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26 meter) calibration procedure, since the "power vs. power" and "power vs.
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27 frequency" calibration tables are stored in the EPROM, the checksum must be
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28 computed when a calibration is performed. For this unit, the value at address
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29 0x02F6 must be set so that the sum modulo 256 of all bytes of the EPROM is
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30 equal to 0xFF.
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31
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32 So the checksum is just a matter of sum modulo 256, but on the 545B, each EPROM
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33 chip has its content verified, as can be deduced by the fact there are 3 error
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34 codes (31, 32 and 33), one for each EPROM chip.
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35
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36 I found the part of the initialisation code that compute this checksum::
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37
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38 ; Test PROM bank i (i in 1,2,3);
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39 ; M000C: start address
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40 ; M000E: i
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41 6041 Z6041 CLRA ;4F
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42 6042 LDY #Z4000 ;10 8E 40 00
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43 6046 LDX Z000C ;9E 0C
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44 6048 Z6048 ADDA ,X+ ;AB 80
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45 604A LEAY -$01,Y ;31 3F
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46 604C BNE Z6048 ;26 FA
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47 604E STX >Z000C ;BF 00 0C
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48 6051 LDB >Z000E ;F6 00 0E
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49 6054 CMPB #$03 ;C1 03
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50 6056 BEQ Z605E ;27 06
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51 6058 DECB ;5A
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52 6059 LDX #MFFEA ;8E FF EA
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53 605C ADDA B,X ;AB 85
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54 605E Z605E COMA ;43
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55 605F RTS ;39
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56
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57
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58 This chunck of code is called with the start address in 0x000C (set to 0x4000
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59 on normal initial execution), and EPROM 'bank' in byte 0x000E (can be 1, 2 or
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60 3). Once again, during normal init execution, this function is called with the
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61 value 1 in this memory cell.
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62
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63 So when i = 1 or 2, the sum if computed (in register A), and the result is
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64 compared to the value stored at 0xFFEA (first EPROM) and 0xFFEB (second EPROM).
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65
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66 For the third one (in which those checksum values are), no comparison is made,
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67 the sum is expected to be 0xFF, which can be achieved by modifying the value of
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68 byte 0xFFEC.
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71 Frequency Offset
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72 ================
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73
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74 As explained before, the frequency offset initial value seems to be set in the
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75 chunck of code around 0x6118-0x6125::
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76
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77 6118 LDX #M0276 ;8E 02 76
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78 611B LDA #$01 ;86 01
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79 611D STA ,X ;A7 84
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80 611F STA $02,X ;A7 02
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81 6121 LDA #$60 ;86 60
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82 6123 STA $03,X ;A7 03
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83
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84 So the easiest way to remove this is to replace this code by NOPs. I've tried
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85 this, computed the checksums and burnt a pair of EPROMs (only bank 1 and 3 are
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86 modified).
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87
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88 And it worked! Mostly. The offset set to 0 as expected, but the "Offset"
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89 indicator remains on. I can live with that, but I'll try to figure out how to
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90 fix this also, if possible.
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91
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92
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93 Digits Resolution
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94 =================
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95
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96 The chuck of initialisation code related to this setup is::
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97
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98 6125 LDX #M005D ;8E 00 5D
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99 6128 LDA #$0D ;86 0D
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100 612A STA $01,X ;A7 01
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101 612C LDA #$05 ;86 05
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102 612E STA >M0045 ;B7 00 45
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103
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104
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105 At least the last 3 lines are directly related to this resolutin setup. So I've
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106 tried to replace these few opcodes with NOPs.
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107
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108 And the result is a partial success: all the digits are displayed when I power
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109 the device on, but the frequency counter still computes only 5 digits, the
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110 other ones stay zero. The gating is not modified. Not very useful as is...
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111 More digging required!

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