content/hp8662a_3.rst

Tue, 28 Aug 2018 15:12:24 +0200

author
David Douard <david.douard@logilab.fr>
date
Tue, 28 Aug 2018 15:12:24 +0200
changeset 109
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parent 101
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child 115
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[prologix] minor improvments

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1 ===============================================
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2 HP8662A Synthetized Signal Generator - Part 3
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3 ===============================================
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4
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5 :Author: David Douard
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6 :Category: Electronics
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7 :Tags: HP8662A, repair, test equipment, HP, Generator, RF
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8 :series: HP 8662A
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9 :series_index: 3
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10
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11
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12 This is the part 3 on my series about my HP 8662A Signal Generator, and is
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13 about the third main problems I found with this unit, as evocated in `part
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14 2 <{filename}hp8662a_2.rst>`_: Error 04 is lit and there are some very
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15 unpleasant spectrums at some frequencies.
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16
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17
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18 Low Fequency Section
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19 ====================
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20
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21 If the generator is now able to produce a signal (the AM and FM modulations
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22 also work), it also gives an Error 04, which is described in the Service Manual
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23 as "Sum Loop Unlocked (Low Frequency Section)", and the troubleshooting
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24 procedure to follow in on the Service Sheet H. The general block diagram of
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25 this section is as follow:
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26
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27 .. image:: {filename}images/hp8662a/LF_block_diagram.png
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28 :class: image-process-large-photo
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29
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30 This Low Frequency Section consists in no less than 4 phase locked loops in
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31 order to achieve adjustable frequency synthesis with the expected stability and
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32 resolution.
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33
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34 In fact, when in the main band of the generator, ie. when neither the output
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35 frequency doubler nor the down converter are in the signal path (that is, when
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36 the frequency range is between 120MHz and 640MHz). The frequency display
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37 consists in 11 digits, named DF0 to DF10, which are segmented to control
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38 several sets of PLLs:
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39
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40 :DF0 - DF2: are the fractional part of the fractional N-Loop (.1Hz, 1Hz and
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41 10Hz digits),
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42
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43 :DF3 - DF5: are the integer part of the fractional N-loop (100Hz, 1kHz and
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44 10kHz resolutions)
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45
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46 :DF6 - DF7: are used to set the pretune VCO value for the sum loop VCO (A3A7),
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47 the FM sum loop VCO (A3A8) as well as the N-Loop VCO (A3A4). These
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48 are the 0.1MHz and 1MHz resolution digits.
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49
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50 :DF8 - DF9: these control the high frequency section (DF10 can only be 0 or 1,
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51 in which case the frequency doubler is used).
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52
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53
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54 Here is a more detailed vue of the block diagram of the low frequency section:
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55
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56 .. image:: {filename}images/hp8662a/sheet_H.png
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57 :class: image-process-large-photo
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58
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59
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60 Fixing the Error 04
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61 ===================
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62
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63 The service manual describes the Error 04 as related to the Sum Loop, and the
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64 first troubleshooting step is to adjust the LF Sum Loop VCO on A3A7.
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65
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66 To do this, one must open the loop of the PLL to be able to adjust the
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67 frequency-to-voltage curve of the VCO.
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68
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69 It took me a while to really understand the service manual on this point, as it explains:
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70
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71 Remove the two jumpers on the A3A7 VCO Assembly a n d plug the board back
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72 into its socket.
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73
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74 The problem is that there are no jumpers on that board... In fact, these
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75 jumpers exists, but are just soldered wires, and not, as one would expect,
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76 jumpers that can be easily unplugged.
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77
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78 Once I finally understood this, I've been able to perform this adjustment. This
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79 consists in tweaking two potentiometers to tune both ends of this
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80 frequency/voltage curve.
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81
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82 The ideal curve is (all frequencies are in MHz):
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83
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84 ===== =========== ========= =========
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85 Freq N-Loop VCO Sum L VCO FM SL VCO
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86 +/- 3MHz +/- 3MHz +/- .3MHz
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87 ===== =========== ========= =========
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88 320.0 122 120 10.0
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89 320.1 123 121 10.1
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90 320.2 124 122 10.2
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91 320.4 126 124 10.4
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92 320.8 130 128 10.8
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93 321.0 132 130 11
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94 322.0 142 140 12
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95 324.0 162 160 14
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96 328.0 202 200 18
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97 329.9 221 219 19.9
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98 ===== =========== ========= =========
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99
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100 As you can see, ideal curves are pretty linear.
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101
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102 At first, I could not find a correct set of tunings: when I was setting the two
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103 ends of the curve to their ideal values (120MHz and 219MHz), the values for
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104 324MHz and 328MHz did not match the +/- 3MHz criterion.
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105
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106 Here is the curve after I adjusted both ends to be as close as possible as
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107 their ideal values (the error is inversed to make the plot easier to read; most
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108 of the time, I am below the expected value):
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109
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110 .. plotly:: {filename}/json/hp8662a_vco_sl.json
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111 :width: 800
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112 :height: 600
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113
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114 As you can see, the +/- 3MHz band is not achieved for most part of the curve.
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115 And it looks pretty bad since the max error is above 6MHz. However, I
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116 compensated this by overshooting these two points as much as possible in order
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117 to try to keep the whole curve within this +/- 3MHz band.
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118
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119 Unfortunately I haven't taken numerical values after this tuning, since this
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120 was enough to clear the Error 04.
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121
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122
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123 Other unstable PLLs
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124 ===================
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125
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126 After this adjustement, the generator seems to works fine: it does produces a
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127 nice output signal (well, I though) and gives no more error. But eventually,
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128 playing with the sweep controls, I found some pretty nasty behaviors at some
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129 ferquencies.
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130
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131 For example, at 100.3MHz, we have a decent signal:
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132
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133 .. image:: {filename}/images/hp8662a/working_not_quite_3.jpg
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134 :class: image-process-large-photo
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135
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136 .. image:: {filename}/images/hp8662a/working_not_quite_3_sa.jpg
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137 :class: image-process-large-photo
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138
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139 but at 101.0Mhz, it begins to looks pretty messy:
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140
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141 .. image:: {filename}/images/hp8662a/working_not_quite_2.jpg
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142 :class: image-process-large-photo
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143
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144 .. image:: {filename}/images/hp8662a/working_not_quite_2_sa.jpg
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145 :class: image-process-large-photo
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146
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147 and 101.9Mhz shows "nice" side bands:
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148
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149 .. image:: {filename}/images/hp8662a/working_not_quite.jpg
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150 :class: image-process-large-photo
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151
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152 .. image:: {filename}/images/hp8662a/working_not_quite_sa.jpg
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153 :class: image-process-large-photo
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154
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155 The problem seems quite clear: some PLL cannot lock at specific frequencies,
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156 but the strange thing is that this unlock PLL does not produces an error.
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157
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158 So I tried to figure out which boad assembly could be the culprit. With no
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159 error however, I had to troubleshoot without a procedure.
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160
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161 The funny thing was there was not clear 'pattern' of which frequencies produces
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162 the erratic behavior and which worked fine.
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163
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164 The problematic ranges were clearly cyclic upon the frequency range, but the
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165 limits were not very stable.
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166
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167 I spent a fait amount of time reading the service manual and reading the
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168 schematics to try to understand which board could be the culprit, and measuring
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169 value at any testpoint possible...
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170
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171 At the end, as I did not make any progress, I decided to try to make all the
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172 "post-reapir" adjustments related to the Low Frequency section.
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173
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174 And when I finally tuned the FM Sum Loop VCO, for the procedure is very similar
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175 to the Sum Loop VCO one, the problem disappeared.
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176
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177 For example, a 101MHz signal which was very unstable before now looks like:
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178
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179 .. image:: {filename}/images/hp8662a/working_101.jpg
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180 :class: image-process-large-photo

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