Mercurial > hp34970-pcb / file comparison
comparison: hp34970.pro
hp34970.pro
- changeset 0
- a70499980c1d
- child 1
- ac54b4966d64
equal
deleted
inserted
replaced
| -1:000000000000 | 0:a70499980c1d |
|---|---|
| 1 update=sam. 19 sept. 2020 18:13:47 CEST | |
| 2 version=1 | |
| 3 last_client=kicad | |
| 4 [general] | |
| 5 version=1 | |
| 6 RootSch= | |
| 7 BoardNm= | |
| 8 [cvpcb] | |
| 9 version=1 | |
| 10 NetIExt=net | |
| 11 [eeschema] | |
| 12 version=1 | |
| 13 LibDir= | |
| 14 [eeschema/libraries] | |
| 15 [pcbnew] | |
| 16 version=1 | |
| 17 PageLayoutDescrFile= | |
| 18 LastNetListRead= | |
| 19 CopperLayerCount=2 | |
| 20 BoardThickness=1.6002 | |
| 21 AllowMicroVias=0 | |
| 22 AllowBlindVias=0 | |
| 23 RequireCourtyardDefinitions=1 | |
| 24 ProhibitOverlappingCourtyards=1 | |
| 25 MinTrackWidth=0.127 | |
| 26 MinViaDiameter=0.6 | |
| 27 MinViaDrill=0.3 | |
| 28 MinMicroViaDiameter=0.2 | |
| 29 MinMicroViaDrill=0.09999999999999999 | |
| 30 MinHoleToHole=0.4 | |
| 31 TrackWidth1=0.127 | |
| 32 TrackWidth2=0.15 | |
| 33 TrackWidth3=0.2 | |
| 34 TrackWidth4=0.4 | |
| 35 TrackWidth5=0.6 | |
| 36 ViaDiameter1=0.6 | |
| 37 ViaDrill1=0.3 | |
| 38 ViaDiameter2=0.6 | |
| 39 ViaDrill2=0.3 | |
| 40 ViaDiameter3=0.9 | |
| 41 ViaDrill3=0.4 | |
| 42 dPairWidth1=0.1524 | |
| 43 dPairGap1=0.254 | |
| 44 dPairViaGap1=0.25 | |
| 45 SilkLineWidth=0.1524 | |
| 46 SilkTextSizeV=0.8128 | |
| 47 SilkTextSizeH=0.8128 | |
| 48 SilkTextSizeThickness=0.1524 | |
| 49 SilkTextItalic=0 | |
| 50 SilkTextUpright=1 | |
| 51 CopperLineWidth=0.254 | |
| 52 CopperTextSizeV=1.524 | |
| 53 CopperTextSizeH=1.524 | |
| 54 CopperTextThickness=0.3048 | |
| 55 CopperTextItalic=0 | |
| 56 CopperTextUpright=1 | |
| 57 EdgeCutLineWidth=0.03809999999999999 | |
| 58 CourtyardLineWidth=0.05 | |
| 59 OthersLineWidth=0.1524 | |
| 60 OthersTextSizeV=1.016 | |
| 61 OthersTextSizeH=1.016 | |
| 62 OthersTextSizeThickness=0.1524 | |
| 63 OthersTextItalic=0 | |
| 64 OthersTextUpright=1 | |
| 65 SolderMaskClearance=0 | |
| 66 SolderMaskMinWidth=0.12 | |
| 67 SolderPasteClearance=0 | |
| 68 SolderPasteRatio=-0 | |
| 69 [pcbnew/Layer.F.Cu] | |
| 70 Name=Front | |
| 71 Type=0 | |
| 72 Enabled=1 | |
| 73 [pcbnew/Layer.In1.Cu] | |
| 74 Name=In1.Cu | |
| 75 Type=0 | |
| 76 Enabled=0 | |
| 77 [pcbnew/Layer.In2.Cu] | |
| 78 Name=In2.Cu | |
| 79 Type=0 | |
| 80 Enabled=0 | |
| 81 [pcbnew/Layer.In3.Cu] | |
| 82 Name=In3.Cu | |
| 83 Type=0 | |
| 84 Enabled=0 | |
| 85 [pcbnew/Layer.In4.Cu] | |
| 86 Name=In4.Cu | |
| 87 Type=0 | |
| 88 Enabled=0 | |
| 89 [pcbnew/Layer.In5.Cu] | |
| 90 Name=In5.Cu | |
| 91 Type=0 | |
| 92 Enabled=0 | |
| 93 [pcbnew/Layer.In6.Cu] | |
| 94 Name=In6.Cu | |
| 95 Type=0 | |
| 96 Enabled=0 | |
| 97 [pcbnew/Layer.In7.Cu] | |
| 98 Name=In7.Cu | |
| 99 Type=0 | |
| 100 Enabled=0 | |
| 101 [pcbnew/Layer.In8.Cu] | |
| 102 Name=In8.Cu | |
| 103 Type=0 | |
| 104 Enabled=0 | |
| 105 [pcbnew/Layer.In9.Cu] | |
| 106 Name=In9.Cu | |
| 107 Type=0 | |
| 108 Enabled=0 | |
| 109 [pcbnew/Layer.In10.Cu] | |
| 110 Name=In10.Cu | |
| 111 Type=0 | |
| 112 Enabled=0 | |
| 113 [pcbnew/Layer.In11.Cu] | |
| 114 Name=In11.Cu | |
| 115 Type=0 | |
| 116 Enabled=0 | |
| 117 [pcbnew/Layer.In12.Cu] | |
| 118 Name=In12.Cu | |
| 119 Type=0 | |
| 120 Enabled=0 | |
| 121 [pcbnew/Layer.In13.Cu] | |
| 122 Name=In13.Cu | |
| 123 Type=0 | |
| 124 Enabled=0 | |
| 125 [pcbnew/Layer.In14.Cu] | |
| 126 Name=In14.Cu | |
| 127 Type=0 | |
| 128 Enabled=0 | |
| 129 [pcbnew/Layer.In15.Cu] | |
| 130 Name=In15.Cu | |
| 131 Type=0 | |
| 132 Enabled=0 | |
| 133 [pcbnew/Layer.In16.Cu] | |
| 134 Name=In16.Cu | |
| 135 Type=0 | |
| 136 Enabled=0 | |
| 137 [pcbnew/Layer.In17.Cu] | |
| 138 Name=In17.Cu | |
| 139 Type=0 | |
| 140 Enabled=0 | |
| 141 [pcbnew/Layer.In18.Cu] | |
| 142 Name=In18.Cu | |
| 143 Type=0 | |
| 144 Enabled=0 | |
| 145 [pcbnew/Layer.In19.Cu] | |
| 146 Name=In19.Cu | |
| 147 Type=0 | |
| 148 Enabled=0 | |
| 149 [pcbnew/Layer.In20.Cu] | |
| 150 Name=In20.Cu | |
| 151 Type=0 | |
| 152 Enabled=0 | |
| 153 [pcbnew/Layer.In21.Cu] | |
| 154 Name=In21.Cu | |
| 155 Type=0 | |
| 156 Enabled=0 | |
| 157 [pcbnew/Layer.In22.Cu] | |
| 158 Name=In22.Cu | |
| 159 Type=0 | |
| 160 Enabled=0 | |
| 161 [pcbnew/Layer.In23.Cu] | |
| 162 Name=In23.Cu | |
| 163 Type=0 | |
| 164 Enabled=0 | |
| 165 [pcbnew/Layer.In24.Cu] | |
| 166 Name=In24.Cu | |
| 167 Type=0 | |
| 168 Enabled=0 | |
| 169 [pcbnew/Layer.In25.Cu] | |
| 170 Name=In25.Cu | |
| 171 Type=0 | |
| 172 Enabled=0 | |
| 173 [pcbnew/Layer.In26.Cu] | |
| 174 Name=In26.Cu | |
| 175 Type=0 | |
| 176 Enabled=0 | |
| 177 [pcbnew/Layer.In27.Cu] | |
| 178 Name=In27.Cu | |
| 179 Type=0 | |
| 180 Enabled=0 | |
| 181 [pcbnew/Layer.In28.Cu] | |
| 182 Name=In28.Cu | |
| 183 Type=0 | |
| 184 Enabled=0 | |
| 185 [pcbnew/Layer.In29.Cu] | |
| 186 Name=In29.Cu | |
| 187 Type=0 | |
| 188 Enabled=0 | |
| 189 [pcbnew/Layer.In30.Cu] | |
| 190 Name=In30.Cu | |
| 191 Type=0 | |
| 192 Enabled=0 | |
| 193 [pcbnew/Layer.B.Cu] | |
| 194 Name=Back | |
| 195 Type=0 | |
| 196 Enabled=1 | |
| 197 [pcbnew/Layer.B.Adhes] | |
| 198 Enabled=0 | |
| 199 [pcbnew/Layer.F.Adhes] | |
| 200 Enabled=0 | |
| 201 [pcbnew/Layer.B.Paste] | |
| 202 Enabled=1 | |
| 203 [pcbnew/Layer.F.Paste] | |
| 204 Enabled=1 | |
| 205 [pcbnew/Layer.B.SilkS] | |
| 206 Enabled=1 | |
| 207 [pcbnew/Layer.F.SilkS] | |
| 208 Enabled=1 | |
| 209 [pcbnew/Layer.B.Mask] | |
| 210 Enabled=1 | |
| 211 [pcbnew/Layer.F.Mask] | |
| 212 Enabled=1 | |
| 213 [pcbnew/Layer.Dwgs.User] | |
| 214 Enabled=1 | |
| 215 [pcbnew/Layer.Cmts.User] | |
| 216 Enabled=0 | |
| 217 [pcbnew/Layer.Eco1.User] | |
| 218 Enabled=0 | |
| 219 [pcbnew/Layer.Eco2.User] | |
| 220 Enabled=0 | |
| 221 [pcbnew/Layer.Edge.Cuts] | |
| 222 Enabled=1 | |
| 223 [pcbnew/Layer.Margin] | |
| 224 Enabled=1 | |
| 225 [pcbnew/Layer.B.CrtYd] | |
| 226 Enabled=1 | |
| 227 [pcbnew/Layer.F.CrtYd] | |
| 228 Enabled=1 | |
| 229 [pcbnew/Layer.B.Fab] | |
| 230 Enabled=0 | |
| 231 [pcbnew/Layer.F.Fab] | |
| 232 Enabled=1 | |
| 233 [pcbnew/Layer.Rescue] | |
| 234 Enabled=0 | |
| 235 [pcbnew/Netclasses] | |
| 236 [pcbnew/Netclasses/Default] | |
| 237 Name=Default | |
| 238 Clearance=0.127 | |
| 239 TrackWidth=0.127 | |
| 240 ViaDiameter=0.6 | |
| 241 ViaDrill=0.3 | |
| 242 uViaDiameter=0.6858 | |
| 243 uViaDrill=0.3302 | |
| 244 dPairWidth=0.1524 | |
| 245 dPairGap=0.254 | |
| 246 dPairViaGap=0.25 | |
| 247 [schematic_editor] | |
| 248 version=1 | |
| 249 PageLayoutDescrFile= | |
| 250 PlotDirectoryName= | |
| 251 SubpartIdSeparator=0 | |
| 252 SubpartFirstId=65 | |
| 253 NetFmtName=Pcbnew | |
| 254 SpiceAjustPassiveValues=0 | |
| 255 LabSize=50 | |
| 256 ERC_TestSimilarLabels=1 |
