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comparison: src/TARGET_STM32F303xE/device/stm32f303xe.h

src/TARGET_STM32F303xE/device/stm32f303xe.h

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1 /**
2 ******************************************************************************
3 * @file stm32f303xe.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32F303xE Devices Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral’s registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
16 *
17 * Redistribution and use in source and binary forms, with or without modification,
18 * are permitted provided that the following conditions are met:
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials provided with the distribution.
24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 ******************************************************************************
40 */
41
42 /** @addtogroup CMSIS_Device
43 * @{
44 */
45
46 /** @addtogroup stm32f303xe
47 * @{
48 */
49
50 #ifndef __STM32F303xE_H
51 #define __STM32F303xE_H
52
53 #ifdef __cplusplus
54 extern "C" {
55 #endif /* __cplusplus */
56
57 /** @addtogroup Configuration_section_for_CMSIS
58 * @{
59 */
60
61 /**
62 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
63 */
64 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
65 #define __MPU_PRESENT 1U /*!< STM32F303xE devices provide an MPU */
66 #define __NVIC_PRIO_BITS 4U /*!< STM32F303xE devices use 4 Bits for the Priority Levels */
67 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
68 #ifndef __FPU_PRESENT
69 #define __FPU_PRESENT 1U /*!< STM32F303xE devices provide an FPU */
70 #endif
71 /**
72 * @}
73 */
74
75 /** @addtogroup Peripheral_interrupt_number_definition
76 * @{
77 */
78
79 /**
80 * @brief STM32F303xE devices Interrupt Number Definition, according to the selected device
81 * in @ref Library_configuration_section
82 */
83 typedef enum
84 {
85 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
86 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
87 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
88 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
89 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
90 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
91 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
92 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
93 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
94 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
95 /****** STM32 specific Interrupt Numbers **********************************************************************/
96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
97 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
98 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
99 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
100 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
101 RCC_IRQn = 5, /*!< RCC global Interrupt */
102 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
103 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
104 EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
105 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
106 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
107 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
108 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
109 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
110 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
111 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
112 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
113 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
114 ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
115 USB_HP_CAN_TX_IRQn = 19, /*!< USB Device High Priority or CAN TX Interrupts */
116 USB_LP_CAN_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN RX0 Interrupts */
117 CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
118 CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
119 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
120 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
121 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
122 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
123 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
124 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
125 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
126 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
127 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
128 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
129 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
130 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
131 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
132 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
133 USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
134 USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
135 USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
136 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
137 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
138 USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
139 TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
140 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
141 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
142 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
143 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
144 FMC_IRQn = 48, /*!< FMC global Interrupt */
145 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
146 UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
147 UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
148 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
149 TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
150 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
151 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
152 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
153 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
154 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
155 ADC4_IRQn = 61, /*!< ADC4 global Interrupt */
156 COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/
157 COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/
158 COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */
159 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
160 I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */
161 USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */
162 USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */
163 USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
164 TIM20_BRK_IRQn = 77, /*!< TIM20 Break Interrupt */
165 TIM20_UP_IRQn = 78, /*!< TIM20 Update Interrupt */
166 TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger and Commutation Interrupt */
167 TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare Interrupt */
168 FPU_IRQn = 81, /*!< Floating point Interrupt */
169 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
170 } IRQn_Type;
171
172 /**
173 * @}
174 */
175
176 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
177 #include "system_stm32f3xx.h" /* STM32F3xx System Header */
178 #include <stdint.h>
179
180 /** @addtogroup Peripheral_registers_structures
181 * @{
182 */
183
184 /**
185 * @brief Analog to Digital Converter
186 */
187
188 typedef struct
189 {
190 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
191 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
192 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
193 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
194 uint32_t RESERVED0; /*!< Reserved, 0x010 */
195 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
196 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
197 uint32_t RESERVED1; /*!< Reserved, 0x01C */
198 __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
199 __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
200 __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
201 uint32_t RESERVED2; /*!< Reserved, 0x02C */
202 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
203 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
204 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
205 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
206 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
207 uint32_t RESERVED3; /*!< Reserved, 0x044 */
208 uint32_t RESERVED4; /*!< Reserved, 0x048 */
209 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
210 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
211 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
212 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
213 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
214 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
215 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
216 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
217 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
218 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
219 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
220 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
221 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
222 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
223 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
224 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
225 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
226 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
227
228 } ADC_TypeDef;
229
230 typedef struct
231 {
232 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
233 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
234 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
235 __IO uint32_t CDR; /*!< ADC common regular data register for dual
236 AND triple modes, Address offset: ADC1/3 base address + 0x30C */
237 } ADC_Common_TypeDef;
238
239 /**
240 * @brief Controller Area Network TxMailBox
241 */
242 typedef struct
243 {
244 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
245 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
246 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
247 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
248 } CAN_TxMailBox_TypeDef;
249
250 /**
251 * @brief Controller Area Network FIFOMailBox
252 */
253 typedef struct
254 {
255 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
256 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
257 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
258 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
259 } CAN_FIFOMailBox_TypeDef;
260
261 /**
262 * @brief Controller Area Network FilterRegister
263 */
264 typedef struct
265 {
266 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
267 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
268 } CAN_FilterRegister_TypeDef;
269
270 /**
271 * @brief Controller Area Network
272 */
273 typedef struct
274 {
275 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
276 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
277 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
278 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
279 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
280 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
281 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
282 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
283 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
284 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
285 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
286 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
287 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
288 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
289 uint32_t RESERVED2; /*!< Reserved, 0x208 */
290 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
291 uint32_t RESERVED3; /*!< Reserved, 0x210 */
292 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
293 uint32_t RESERVED4; /*!< Reserved, 0x218 */
294 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
295 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
296 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
297 } CAN_TypeDef;
298
299 /**
300 * @brief Analog Comparators
301 */
302 typedef struct
303 {
304 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
305 } COMP_TypeDef;
306
307 typedef struct
308 {
309 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
310 } COMP_Common_TypeDef;
311
312 /**
313 * @brief CRC calculation unit
314 */
315
316 typedef struct
317 {
318 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
319 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
320 uint8_t RESERVED0; /*!< Reserved, 0x05 */
321 uint16_t RESERVED1; /*!< Reserved, 0x06 */
322 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
323 uint32_t RESERVED2; /*!< Reserved, 0x0C */
324 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
325 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
326 } CRC_TypeDef;
327
328 /**
329 * @brief Digital to Analog Converter
330 */
331
332 typedef struct
333 {
334 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
335 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
336 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
337 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
338 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
339 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
340 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
341 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
342 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
343 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
344 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
345 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
346 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
347 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
348 } DAC_TypeDef;
349
350 /**
351 * @brief Debug MCU
352 */
353
354 typedef struct
355 {
356 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
357 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
358 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
359 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
360 }DBGMCU_TypeDef;
361
362 /**
363 * @brief DMA Controller
364 */
365
366 typedef struct
367 {
368 __IO uint32_t CCR; /*!< DMA channel x configuration register */
369 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
370 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
371 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
372 } DMA_Channel_TypeDef;
373
374 typedef struct
375 {
376 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
377 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
378 } DMA_TypeDef;
379
380 /**
381 * @brief External Interrupt/Event Controller
382 */
383
384 typedef struct
385 {
386 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
387 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
388 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
389 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
390 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
391 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
392 uint32_t RESERVED1; /*!< Reserved, 0x18 */
393 uint32_t RESERVED2; /*!< Reserved, 0x1C */
394 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
395 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
396 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
397 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
398 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
399 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
400 }EXTI_TypeDef;
401
402 /**
403 * @brief FLASH Registers
404 */
405
406 typedef struct
407 {
408 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
409 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
410 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
411 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
412 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
413 __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */
414 uint32_t RESERVED; /*!< Reserved, 0x18 */
415 __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */
416 __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */
417
418 } FLASH_TypeDef;
419
420 /**
421 * @brief Flexible Memory Controller
422 */
423
424 typedef struct
425 {
426 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
427 } FMC_Bank1_TypeDef;
428
429 /**
430 * @brief Flexible Memory Controller Bank1E
431 */
432
433 typedef struct
434 {
435 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
436 } FMC_Bank1E_TypeDef;
437
438 /**
439 * @brief Flexible Memory Controller Bank2
440 */
441
442 typedef struct
443 {
444 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
445 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
446 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
447 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
448 uint32_t RESERVED0; /*!< Reserved, 0x70 */
449 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
450 uint32_t RESERVED1; /*!< Reserved, 0x78 */
451 uint32_t RESERVED2; /*!< Reserved, 0x7C */
452 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
453 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
454 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
455 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
456 uint32_t RESERVED3; /*!< Reserved, 0x90 */
457 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
458 } FMC_Bank2_3_TypeDef;
459
460 /**
461 * @brief Flexible Memory Controller Bank4
462 */
463
464 typedef struct
465 {
466 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
467 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
468 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
469 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
470 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
471 } FMC_Bank4_TypeDef;
472
473 /**
474 * @brief Option Bytes Registers
475 */
476 typedef struct
477 {
478 __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */
479 __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */
480 uint16_t RESERVED0; /*!< Reserved, 0x04 */
481 uint16_t RESERVED1; /*!< Reserved, 0x06 */
482 __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */
483 __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */
484 __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */
485 __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */
486 } OB_TypeDef;
487
488 /**
489 * @brief General Purpose I/O
490 */
491
492 typedef struct
493 {
494 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
495 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
496 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
497 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
498 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
499 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
500 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
501 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
502 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
503 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
504 }GPIO_TypeDef;
505
506 /**
507 * @brief Operational Amplifier (OPAMP)
508 */
509
510 typedef struct
511 {
512 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
513 } OPAMP_TypeDef;
514
515 /**
516 * @brief System configuration controller
517 */
518
519 typedef struct
520 {
521 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
522 __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
523 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
524 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
525 __IO uint32_t RESERVED0; /*!< Reserved, 0x1C */
526 __IO uint32_t RESERVED1; /*!< Reserved, 0x20 */
527 __IO uint32_t RESERVED2; /*!< Reserved, 0x24 */
528 __IO uint32_t RESERVED4; /*!< Reserved, 0x28 */
529 __IO uint32_t RESERVED5; /*!< Reserved, 0x2C */
530 __IO uint32_t RESERVED6; /*!< Reserved, 0x30 */
531 __IO uint32_t RESERVED7; /*!< Reserved, 0x34 */
532 __IO uint32_t RESERVED8; /*!< Reserved, 0x38 */
533 __IO uint32_t RESERVED9; /*!< Reserved, 0x3C */
534 __IO uint32_t RESERVED10; /*!< Reserved, 0x40 */
535 __IO uint32_t RESERVED11; /*!< Reserved, 0x44 */
536 __IO uint32_t CFGR4; /*!< SYSCFG configuration register 4, Address offset: 0x48 */
537 __IO uint32_t RESERVED12; /*!< Reserved, 0x4C */
538 __IO uint32_t RESERVED13; /*!< Reserved, 0x50 */
539 } SYSCFG_TypeDef;
540
541 /**
542 * @brief Inter-integrated Circuit Interface
543 */
544
545 typedef struct
546 {
547 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
548 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
549 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
550 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
551 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
552 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
553 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
554 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
555 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
556 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
557 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
558 }I2C_TypeDef;
559
560 /**
561 * @brief Independent WATCHDOG
562 */
563
564 typedef struct
565 {
566 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
567 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
568 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
569 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
570 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
571 } IWDG_TypeDef;
572
573 /**
574 * @brief Power Control
575 */
576
577 typedef struct
578 {
579 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
580 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
581 } PWR_TypeDef;
582
583 /**
584 * @brief Reset and Clock Control
585 */
586 typedef struct
587 {
588 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
589 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
590 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
591 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
592 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
593 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
594 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
595 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
596 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
597 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
598 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
599 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
600 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
601 } RCC_TypeDef;
602
603 /**
604 * @brief Real-Time Clock
605 */
606
607 typedef struct
608 {
609 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
610 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
611 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
612 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
613 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
614 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
615 uint32_t RESERVED0; /*!< Reserved, 0x18 */
616 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
617 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
618 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
619 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
620 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
621 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
622 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
623 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
624 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
625 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
626 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
627 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
628 uint32_t RESERVED7; /*!< Reserved, 0x4C */
629 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
630 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
631 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
632 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
633 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
634 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
635 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
636 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
637 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
638 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
639 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
640 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
641 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
642 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
643 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
644 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
645 } RTC_TypeDef;
646
647
648 /**
649 * @brief Serial Peripheral Interface
650 */
651
652 typedef struct
653 {
654 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
655 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
656 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
657 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
658 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
659 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
660 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
661 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
662 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
663 } SPI_TypeDef;
664
665 /**
666 * @brief TIM
667 */
668 typedef struct
669 {
670 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
671 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
672 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
673 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
674 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
675 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
676 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
677 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
678 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
679 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
680 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
681 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
682 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
683 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
684 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
685 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
686 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
687 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
688 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
689 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
690 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
691 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
692 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
693 __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
694 } TIM_TypeDef;
695
696 /**
697 * @brief Touch Sensing Controller (TSC)
698 */
699 typedef struct
700 {
701 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
702 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
703 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
704 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
705 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
706 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
707 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
708 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
709 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
710 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
711 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
712 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
713 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
714 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
715 } TSC_TypeDef;
716
717 /**
718 * @brief Universal Synchronous Asynchronous Receiver Transmitter
719 */
720
721 typedef struct
722 {
723 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
724 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
725 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
726 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
727 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
728 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
729 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
730 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
731 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
732 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
733 uint16_t RESERVED1; /*!< Reserved, 0x26 */
734 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
735 uint16_t RESERVED2; /*!< Reserved, 0x2A */
736 } USART_TypeDef;
737
738 /**
739 * @brief Universal Serial Bus Full Speed Device
740 */
741
742 typedef struct
743 {
744 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
745 __IO uint16_t RESERVED0; /*!< Reserved */
746 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
747 __IO uint16_t RESERVED1; /*!< Reserved */
748 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
749 __IO uint16_t RESERVED2; /*!< Reserved */
750 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
751 __IO uint16_t RESERVED3; /*!< Reserved */
752 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
753 __IO uint16_t RESERVED4; /*!< Reserved */
754 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
755 __IO uint16_t RESERVED5; /*!< Reserved */
756 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
757 __IO uint16_t RESERVED6; /*!< Reserved */
758 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
759 __IO uint16_t RESERVED7[17]; /*!< Reserved */
760 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
761 __IO uint16_t RESERVED8; /*!< Reserved */
762 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
763 __IO uint16_t RESERVED9; /*!< Reserved */
764 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
765 __IO uint16_t RESERVEDA; /*!< Reserved */
766 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
767 __IO uint16_t RESERVEDB; /*!< Reserved */
768 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
769 __IO uint16_t RESERVEDC; /*!< Reserved */
770 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
771 __IO uint16_t RESERVEDD; /*!< Reserved */
772 } USB_TypeDef;
773
774 /**
775 * @brief Window WATCHDOG
776 */
777 typedef struct
778 {
779 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
780 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
781 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
782 } WWDG_TypeDef;
783
784 /** @addtogroup Peripheral_memory_map
785 * @{
786 */
787
788 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
789 #define CCMDATARAM_BASE ((uint32_t)0x10000000U) /*!< CCM(core coupled memory) data RAM base address in the alias region */
790 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
791 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
792 #define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */
793 #define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC registers base address */
794
795 #define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM base address in the bit-band region */
796 #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
797
798
799 /*!< Peripheral memory map */
800 #define APB1PERIPH_BASE PERIPH_BASE
801 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
802 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
803 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U)
804 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000U)
805
806 /*!< APB1 peripherals */
807 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
808 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
809 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
810 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U)
811 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)
812 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
813 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
814 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
815 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400U)
816 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
817 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U)
818 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000U)
819 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
820 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
821 #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U)
822 #define UART5_BASE (APB1PERIPH_BASE + 0x00005000U)
823 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
824 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U)
825 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
826 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */
827 #define CAN_BASE (APB1PERIPH_BASE + 0x00006400U)
828 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
829 #define DAC1_BASE (APB1PERIPH_BASE + 0x00007400U)
830 #define DAC_BASE DAC1_BASE
831 #define I2C3_BASE (APB1PERIPH_BASE + 0x00007800U)
832
833 /*!< APB2 peripherals */
834 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000U)
835 #define COMP1_BASE (APB2PERIPH_BASE + 0x0000001CU)
836 #define COMP2_BASE (APB2PERIPH_BASE + 0x00000020U)
837 #define COMP3_BASE (APB2PERIPH_BASE + 0x00000024U)
838 #define COMP4_BASE (APB2PERIPH_BASE + 0x00000028U)
839 #define COMP5_BASE (APB2PERIPH_BASE + 0x0000002CU)
840 #define COMP6_BASE (APB2PERIPH_BASE + 0x00000030U)
841 #define COMP7_BASE (APB2PERIPH_BASE + 0x00000034U)
842 #define COMP_BASE COMP1_BASE
843 #define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038U)
844 #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003CU)
845 #define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040U)
846 #define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044U)
847 #define OPAMP_BASE OPAMP1_BASE
848 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
849 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U)
850 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
851 #define TIM8_BASE (APB2PERIPH_BASE + 0x00003400U)
852 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
853 #define SPI4_BASE (APB2PERIPH_BASE + 0x00003C00U)
854 #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000U)
855 #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400U)
856 #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800U)
857 #define TIM20_BASE (APB2PERIPH_BASE + 0x00005000U)
858
859 /*!< AHB1 peripherals */
860 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000U)
861 #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008U)
862 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001CU)
863 #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030U)
864 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044U)
865 #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058U)
866 #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006CU)
867 #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080U)
868 #define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400U)
869 #define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408U)
870 #define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041CU)
871 #define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430U)
872 #define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444U)
873 #define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458U)
874 #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000U)
875 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
876 #define OB_BASE ((uint32_t)0x1FFFF800U) /*!< Flash Option Bytes base address */
877 #define FLASHSIZE_BASE ((uint32_t)0x1FFFF7CCU) /*!< FLASH Size register base address */
878 #define UID_BASE ((uint32_t)0x1FFFF7ACU) /*!< Unique device ID register base address */
879 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000U)
880 #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000U)
881
882 /*!< AHB2 peripherals */
883 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000U)
884 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400U)
885 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800U)
886 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00U)
887 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000U)
888 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400U)
889 #define GPIOG_BASE (AHB2PERIPH_BASE + 0x00001800U)
890 #define GPIOH_BASE (AHB2PERIPH_BASE + 0x00001C00U)
891
892 /*!< AHB3 peripherals */
893 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000U)
894 #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100U)
895 #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300U)
896 #define ADC3_BASE (AHB3PERIPH_BASE + 0x00000400U)
897 #define ADC4_BASE (AHB3PERIPH_BASE + 0x00000500U)
898 #define ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700U)
899
900 /*!< FMC Bankx base address */
901 #define FMC_BANK1 (FMC_BASE) /*!< FMC Bank1 base address */
902 #define FMC_BANK1_1 (FMC_BANK1) /*!< FMC Bank1_1 base address */
903 #define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U) /*!< FMC Bank1_2 base address */
904 #define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U) /*!< FMC Bank1_3 base address */
905 #define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U) /*!< FMC Bank1_4 base address */
906
907 #define FMC_BANK2 (FMC_BASE + 0x10000000U) /*!< FMC Bank2 base address */
908 #define FMC_BANK3 (FMC_BASE + 0x20000000U) /*!< FMC Bank3 base address */
909 #define FMC_BANK4 (FMC_BASE + 0x30000000U) /*!< FMC Bank4 base address */
910
911 /*!< FMC Bankx registers base address */
912 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
913 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
914 #define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060U)
915 #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0U)
916
917 #define DBGMCU_BASE ((uint32_t)0xE0042000U) /*!< Debug MCU registers base address */
918 /**
919 * @}
920 */
921
922 /** @addtogroup Peripheral_declaration
923 * @{
924 */
925 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
926 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
927 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
928 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
929 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
930 #define RTC ((RTC_TypeDef *) RTC_BASE)
931 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
932 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
933 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
934 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
935 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
936 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
937 #define USART2 ((USART_TypeDef *) USART2_BASE)
938 #define USART3 ((USART_TypeDef *) USART3_BASE)
939 #define UART4 ((USART_TypeDef *) UART4_BASE)
940 #define UART5 ((USART_TypeDef *) UART5_BASE)
941 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
942 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
943 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
944 #define CAN1 ((CAN_TypeDef *) CAN_BASE)
945 #define PWR ((PWR_TypeDef *) PWR_BASE)
946 #define DAC ((DAC_TypeDef *) DAC_BASE)
947 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
948 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
949 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
950 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
951 #define COMP3 ((COMP_TypeDef *) COMP3_BASE)
952 #define COMP4 ((COMP_TypeDef *) COMP4_BASE)
953 #define COMP34_COMMON ((COMP_Common_TypeDef *) COMP4_BASE)
954 #define COMP5 ((COMP_TypeDef *) COMP5_BASE)
955 #define COMP6 ((COMP_TypeDef *) COMP6_BASE)
956 #define COMP56_COMMON ((COMP_Common_TypeDef *) COMP6_BASE)
957 #define COMP7 ((COMP_TypeDef *) COMP7_BASE)
958 /* Legacy define */
959 #define COMP ((COMP_TypeDef *) COMP_BASE)
960 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
961 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
962 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
963 #define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
964 #define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
965 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
966 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
967 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
968 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
969 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
970 #define USART1 ((USART_TypeDef *) USART1_BASE)
971 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
972 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
973 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
974 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
975 #define TIM20 ((TIM_TypeDef *) TIM20_BASE)
976 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
977 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
978 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
979 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
980 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
981 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
982 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
983 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
984 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
985 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
986 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
987 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
988 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
989 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
990 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
991 #define RCC ((RCC_TypeDef *) RCC_BASE)
992 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
993 #define OB ((OB_TypeDef *) OB_BASE)
994 #define CRC ((CRC_TypeDef *) CRC_BASE)
995 #define TSC ((TSC_TypeDef *) TSC_BASE)
996 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
997 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
998 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
999 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1000 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1001 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1002 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1003 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1004 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1005 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1006 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1007 #define ADC4 ((ADC_TypeDef *) ADC4_BASE)
1008 #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
1009 #define ADC34_COMMON ((ADC_Common_TypeDef *) ADC3_4_COMMON_BASE)
1010 /* Legacy defines */
1011 #define ADC1_2_COMMON ADC12_COMMON
1012 #define ADC3_4_COMMON ADC34_COMMON
1013 #define USB ((USB_TypeDef *) USB_BASE)
1014 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1015 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1016 #define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
1017 #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
1018
1019 /**
1020 * @}
1021 */
1022
1023 /** @addtogroup Exported_constants
1024 * @{
1025 */
1026
1027 /** @addtogroup Peripheral_Registers_Bits_Definition
1028 * @{
1029 */
1030
1031 /******************************************************************************/
1032 /* Peripheral Registers_Bits_Definition */
1033 /******************************************************************************/
1034
1035 /******************************************************************************/
1036 /* */
1037 /* Analog to Digital Converter SAR (ADC) */
1038 /* */
1039 /******************************************************************************/
1040
1041 #define ADC5_V1_1 /*!< ADC IP version */
1042
1043 /*
1044 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
1045 */
1046 #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
1047
1048 /******************** Bit definition for ADC_ISR register ********************/
1049 #define ADC_ISR_ADRDY_Pos (0U)
1050 #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
1051 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
1052 #define ADC_ISR_EOSMP_Pos (1U)
1053 #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
1054 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
1055 #define ADC_ISR_EOC_Pos (2U)
1056 #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
1057 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
1058 #define ADC_ISR_EOS_Pos (3U)
1059 #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
1060 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
1061 #define ADC_ISR_OVR_Pos (4U)
1062 #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
1063 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
1064 #define ADC_ISR_JEOC_Pos (5U)
1065 #define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
1066 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
1067 #define ADC_ISR_JEOS_Pos (6U)
1068 #define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
1069 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
1070 #define ADC_ISR_AWD1_Pos (7U)
1071 #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
1072 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
1073 #define ADC_ISR_AWD2_Pos (8U)
1074 #define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
1075 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
1076 #define ADC_ISR_AWD3_Pos (9U)
1077 #define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
1078 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
1079 #define ADC_ISR_JQOVF_Pos (10U)
1080 #define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
1081 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
1082
1083 /* Legacy defines */
1084 #define ADC_ISR_ADRD (ADC_ISR_ADRDY)
1085
1086 /******************** Bit definition for ADC_IER register ********************/
1087 #define ADC_IER_ADRDYIE_Pos (0U)
1088 #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
1089 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
1090 #define ADC_IER_EOSMPIE_Pos (1U)
1091 #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
1092 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
1093 #define ADC_IER_EOCIE_Pos (2U)
1094 #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
1095 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
1096 #define ADC_IER_EOSIE_Pos (3U)
1097 #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
1098 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
1099 #define ADC_IER_OVRIE_Pos (4U)
1100 #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
1101 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
1102 #define ADC_IER_JEOCIE_Pos (5U)
1103 #define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
1104 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
1105 #define ADC_IER_JEOSIE_Pos (6U)
1106 #define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
1107 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
1108 #define ADC_IER_AWD1IE_Pos (7U)
1109 #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
1110 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
1111 #define ADC_IER_AWD2IE_Pos (8U)
1112 #define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
1113 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
1114 #define ADC_IER_AWD3IE_Pos (9U)
1115 #define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
1116 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
1117 #define ADC_IER_JQOVFIE_Pos (10U)
1118 #define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
1119 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
1120
1121 /* Legacy defines */
1122 #define ADC_IER_RDY (ADC_IER_ADRDYIE)
1123 #define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
1124 #define ADC_IER_EOC (ADC_IER_EOCIE)
1125 #define ADC_IER_EOS (ADC_IER_EOSIE)
1126 #define ADC_IER_OVR (ADC_IER_OVRIE)
1127 #define ADC_IER_JEOC (ADC_IER_JEOCIE)
1128 #define ADC_IER_JEOS (ADC_IER_JEOSIE)
1129 #define ADC_IER_AWD1 (ADC_IER_AWD1IE)
1130 #define ADC_IER_AWD2 (ADC_IER_AWD2IE)
1131 #define ADC_IER_AWD3 (ADC_IER_AWD3IE)
1132 #define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
1133
1134 /******************** Bit definition for ADC_CR register ********************/
1135 #define ADC_CR_ADEN_Pos (0U)
1136 #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
1137 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
1138 #define ADC_CR_ADDIS_Pos (1U)
1139 #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
1140 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
1141 #define ADC_CR_ADSTART_Pos (2U)
1142 #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
1143 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
1144 #define ADC_CR_JADSTART_Pos (3U)
1145 #define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
1146 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
1147 #define ADC_CR_ADSTP_Pos (4U)
1148 #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
1149 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
1150 #define ADC_CR_JADSTP_Pos (5U)
1151 #define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
1152 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
1153 #define ADC_CR_ADVREGEN_Pos (28U)
1154 #define ADC_CR_ADVREGEN_Msk (0x3U << ADC_CR_ADVREGEN_Pos) /*!< 0x30000000 */
1155 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
1156 #define ADC_CR_ADVREGEN_0 (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
1157 #define ADC_CR_ADVREGEN_1 (0x2U << ADC_CR_ADVREGEN_Pos) /*!< 0x20000000 */
1158 #define ADC_CR_ADCALDIF_Pos (30U)
1159 #define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
1160 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
1161 #define ADC_CR_ADCAL_Pos (31U)
1162 #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
1163 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
1164
1165 /******************** Bit definition for ADC_CFGR register ******************/
1166 #define ADC_CFGR_DMAEN_Pos (0U)
1167 #define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
1168 #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA enable */
1169 #define ADC_CFGR_DMACFG_Pos (1U)
1170 #define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
1171 #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA configuration */
1172
1173 #define ADC_CFGR_RES_Pos (3U)
1174 #define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
1175 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
1176 #define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
1177 #define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
1178
1179 #define ADC_CFGR_ALIGN_Pos (5U)
1180 #define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
1181 #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
1182
1183 #define ADC_CFGR_EXTSEL_Pos (6U)
1184 #define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
1185 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
1186 #define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
1187 #define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
1188 #define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
1189 #define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
1190
1191 #define ADC_CFGR_EXTEN_Pos (10U)
1192 #define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
1193 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
1194 #define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
1195 #define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
1196
1197 #define ADC_CFGR_OVRMOD_Pos (12U)
1198 #define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
1199 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
1200 #define ADC_CFGR_CONT_Pos (13U)
1201 #define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
1202 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
1203 #define ADC_CFGR_AUTDLY_Pos (14U)
1204 #define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
1205 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
1206
1207 #define ADC_CFGR_DISCEN_Pos (16U)
1208 #define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
1209 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
1210
1211 #define ADC_CFGR_DISCNUM_Pos (17U)
1212 #define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
1213 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
1214 #define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
1215 #define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
1216 #define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
1217
1218 #define ADC_CFGR_JDISCEN_Pos (20U)
1219 #define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
1220 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
1221 #define ADC_CFGR_JQM_Pos (21U)
1222 #define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
1223 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
1224 #define ADC_CFGR_AWD1SGL_Pos (22U)
1225 #define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
1226 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1227 #define ADC_CFGR_AWD1EN_Pos (23U)
1228 #define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
1229 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1230 #define ADC_CFGR_JAWD1EN_Pos (24U)
1231 #define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
1232 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1233 #define ADC_CFGR_JAUTO_Pos (25U)
1234 #define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
1235 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
1236
1237 #define ADC_CFGR_AWD1CH_Pos (26U)
1238 #define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
1239 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
1240 #define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
1241 #define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
1242 #define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
1243 #define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
1244 #define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
1245
1246 /* Legacy defines */
1247 #define ADC_CFGR_AUTOFF_Pos (15U)
1248 #define ADC_CFGR_AUTOFF_Msk (0x1U << ADC_CFGR_AUTOFF_Pos) /*!< 0x00008000 */
1249 #define ADC_CFGR_AUTOFF ADC_CFGR_AUTOFF_Msk /*!< ADC low power auto power off */
1250
1251 /******************** Bit definition for ADC_SMPR1 register *****************/
1252 #define ADC_SMPR1_SMP0_Pos (0U)
1253 #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
1254 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
1255 #define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
1256 #define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
1257 #define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
1258
1259 #define ADC_SMPR1_SMP1_Pos (3U)
1260 #define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
1261 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
1262 #define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
1263 #define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
1264 #define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
1265
1266 #define ADC_SMPR1_SMP2_Pos (6U)
1267 #define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
1268 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
1269 #define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
1270 #define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
1271 #define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
1272
1273 #define ADC_SMPR1_SMP3_Pos (9U)
1274 #define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
1275 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
1276 #define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
1277 #define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
1278 #define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
1279
1280 #define ADC_SMPR1_SMP4_Pos (12U)
1281 #define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
1282 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
1283 #define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
1284 #define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
1285 #define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
1286
1287 #define ADC_SMPR1_SMP5_Pos (15U)
1288 #define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
1289 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
1290 #define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
1291 #define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
1292 #define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
1293
1294 #define ADC_SMPR1_SMP6_Pos (18U)
1295 #define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
1296 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
1297 #define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
1298 #define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
1299 #define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
1300
1301 #define ADC_SMPR1_SMP7_Pos (21U)
1302 #define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
1303 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
1304 #define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
1305 #define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
1306 #define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
1307
1308 #define ADC_SMPR1_SMP8_Pos (24U)
1309 #define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
1310 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
1311 #define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
1312 #define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
1313 #define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
1314
1315 #define ADC_SMPR1_SMP9_Pos (27U)
1316 #define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
1317 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
1318 #define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
1319 #define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
1320 #define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
1321
1322 /******************** Bit definition for ADC_SMPR2 register *****************/
1323 #define ADC_SMPR2_SMP10_Pos (0U)
1324 #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
1325 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
1326 #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
1327 #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
1328 #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
1329
1330 #define ADC_SMPR2_SMP11_Pos (3U)
1331 #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
1332 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
1333 #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
1334 #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
1335 #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
1336
1337 #define ADC_SMPR2_SMP12_Pos (6U)
1338 #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
1339 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
1340 #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
1341 #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
1342 #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
1343
1344 #define ADC_SMPR2_SMP13_Pos (9U)
1345 #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
1346 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
1347 #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
1348 #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
1349 #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
1350
1351 #define ADC_SMPR2_SMP14_Pos (12U)
1352 #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
1353 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
1354 #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
1355 #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
1356 #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
1357
1358 #define ADC_SMPR2_SMP15_Pos (15U)
1359 #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
1360 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
1361 #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
1362 #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
1363 #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
1364
1365 #define ADC_SMPR2_SMP16_Pos (18U)
1366 #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
1367 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
1368 #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
1369 #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
1370 #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
1371
1372 #define ADC_SMPR2_SMP17_Pos (21U)
1373 #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
1374 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
1375 #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
1376 #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
1377 #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
1378
1379 #define ADC_SMPR2_SMP18_Pos (24U)
1380 #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
1381 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
1382 #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
1383 #define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
1384 #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
1385
1386 /******************** Bit definition for ADC_TR1 register *******************/
1387 #define ADC_TR1_LT1_Pos (0U)
1388 #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
1389 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
1390 #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
1391 #define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
1392 #define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
1393 #define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
1394 #define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
1395 #define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
1396 #define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
1397 #define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
1398 #define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
1399 #define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
1400 #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
1401 #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
1402
1403 #define ADC_TR1_HT1_Pos (16U)
1404 #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
1405 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
1406 #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
1407 #define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
1408 #define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
1409 #define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
1410 #define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
1411 #define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
1412 #define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
1413 #define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
1414 #define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
1415 #define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
1416 #define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
1417 #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
1418
1419 /******************** Bit definition for ADC_TR2 register *******************/
1420 #define ADC_TR2_LT2_Pos (0U)
1421 #define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
1422 #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
1423 #define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
1424 #define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
1425 #define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
1426 #define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
1427 #define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
1428 #define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
1429 #define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
1430 #define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
1431
1432 #define ADC_TR2_HT2_Pos (16U)
1433 #define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
1434 #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
1435 #define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
1436 #define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
1437 #define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
1438 #define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
1439 #define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
1440 #define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
1441 #define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
1442 #define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
1443
1444 /******************** Bit definition for ADC_TR3 register *******************/
1445 #define ADC_TR3_LT3_Pos (0U)
1446 #define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
1447 #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
1448 #define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
1449 #define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
1450 #define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
1451 #define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
1452 #define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
1453 #define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
1454 #define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
1455 #define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
1456
1457 #define ADC_TR3_HT3_Pos (16U)
1458 #define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
1459 #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
1460 #define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
1461 #define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
1462 #define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
1463 #define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
1464 #define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
1465 #define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
1466 #define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
1467 #define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
1468
1469 /******************** Bit definition for ADC_SQR1 register ******************/
1470 #define ADC_SQR1_L_Pos (0U)
1471 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
1472 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
1473 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
1474 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
1475 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
1476 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
1477
1478 #define ADC_SQR1_SQ1_Pos (6U)
1479 #define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
1480 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
1481 #define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
1482 #define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
1483 #define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
1484 #define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
1485 #define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
1486
1487 #define ADC_SQR1_SQ2_Pos (12U)
1488 #define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
1489 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
1490 #define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
1491 #define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
1492 #define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
1493 #define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
1494 #define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
1495
1496 #define ADC_SQR1_SQ3_Pos (18U)
1497 #define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
1498 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
1499 #define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
1500 #define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
1501 #define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
1502 #define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
1503 #define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
1504
1505 #define ADC_SQR1_SQ4_Pos (24U)
1506 #define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
1507 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
1508 #define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
1509 #define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
1510 #define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
1511 #define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
1512 #define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
1513
1514 /******************** Bit definition for ADC_SQR2 register ******************/
1515 #define ADC_SQR2_SQ5_Pos (0U)
1516 #define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
1517 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
1518 #define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
1519 #define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
1520 #define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
1521 #define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
1522 #define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
1523
1524 #define ADC_SQR2_SQ6_Pos (6U)
1525 #define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
1526 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
1527 #define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
1528 #define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
1529 #define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
1530 #define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
1531 #define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
1532
1533 #define ADC_SQR2_SQ7_Pos (12U)
1534 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
1535 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
1536 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
1537 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
1538 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
1539 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
1540 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
1541
1542 #define ADC_SQR2_SQ8_Pos (18U)
1543 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
1544 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
1545 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
1546 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
1547 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
1548 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
1549 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
1550
1551 #define ADC_SQR2_SQ9_Pos (24U)
1552 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
1553 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
1554 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
1555 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
1556 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
1557 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
1558 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
1559
1560 /******************** Bit definition for ADC_SQR3 register ******************/
1561 #define ADC_SQR3_SQ10_Pos (0U)
1562 #define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
1563 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
1564 #define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
1565 #define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
1566 #define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
1567 #define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
1568 #define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
1569
1570 #define ADC_SQR3_SQ11_Pos (6U)
1571 #define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
1572 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
1573 #define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
1574 #define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
1575 #define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
1576 #define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
1577 #define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
1578
1579 #define ADC_SQR3_SQ12_Pos (12U)
1580 #define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
1581 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
1582 #define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
1583 #define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
1584 #define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
1585 #define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
1586 #define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
1587
1588 #define ADC_SQR3_SQ13_Pos (18U)
1589 #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
1590 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
1591 #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
1592 #define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
1593 #define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
1594 #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
1595 #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
1596
1597 #define ADC_SQR3_SQ14_Pos (24U)
1598 #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
1599 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
1600 #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
1601 #define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
1602 #define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
1603 #define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
1604 #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
1605
1606 /******************** Bit definition for ADC_SQR4 register ******************/
1607 #define ADC_SQR4_SQ15_Pos (0U)
1608 #define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
1609 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
1610 #define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
1611 #define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
1612 #define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
1613 #define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
1614 #define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
1615
1616 #define ADC_SQR4_SQ16_Pos (6U)
1617 #define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
1618 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
1619 #define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
1620 #define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
1621 #define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
1622 #define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
1623 #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
1624
1625 /******************** Bit definition for ADC_DR register ********************/
1626 #define ADC_DR_RDATA_Pos (0U)
1627 #define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
1628 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
1629 #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
1630 #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
1631 #define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
1632 #define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
1633 #define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
1634 #define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
1635 #define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
1636 #define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
1637 #define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
1638 #define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
1639 #define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
1640 #define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
1641 #define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
1642 #define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
1643 #define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
1644 #define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
1645
1646 /******************** Bit definition for ADC_JSQR register ******************/
1647 #define ADC_JSQR_JL_Pos (0U)
1648 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
1649 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
1650 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
1651 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
1652
1653 #define ADC_JSQR_JEXTSEL_Pos (2U)
1654 #define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */
1655 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
1656 #define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
1657 #define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
1658 #define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
1659 #define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
1660
1661 #define ADC_JSQR_JEXTEN_Pos (6U)
1662 #define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */
1663 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
1664 #define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */
1665 #define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
1666
1667 #define ADC_JSQR_JSQ1_Pos (8U)
1668 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */
1669 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
1670 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */
1671 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
1672 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
1673 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
1674 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
1675
1676 #define ADC_JSQR_JSQ2_Pos (14U)
1677 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
1678 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
1679 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
1680 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
1681 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
1682 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
1683 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
1684
1685 #define ADC_JSQR_JSQ3_Pos (20U)
1686 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */
1687 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
1688 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */
1689 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
1690 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
1691 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
1692 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
1693
1694 #define ADC_JSQR_JSQ4_Pos (26U)
1695 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */
1696 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
1697 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */
1698 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
1699 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
1700 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
1701 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
1702
1703
1704 /******************** Bit definition for ADC_OFR1 register ******************/
1705 #define ADC_OFR1_OFFSET1_Pos (0U)
1706 #define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
1707 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
1708 #define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
1709 #define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
1710 #define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
1711 #define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
1712 #define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
1713 #define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
1714 #define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
1715 #define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
1716 #define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
1717 #define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
1718 #define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
1719 #define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
1720
1721 #define ADC_OFR1_OFFSET1_CH_Pos (26U)
1722 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
1723 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
1724 #define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
1725 #define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
1726 #define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
1727 #define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
1728 #define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
1729
1730 #define ADC_OFR1_OFFSET1_EN_Pos (31U)
1731 #define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
1732 #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
1733
1734 /******************** Bit definition for ADC_OFR2 register ******************/
1735 #define ADC_OFR2_OFFSET2_Pos (0U)
1736 #define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
1737 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
1738 #define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
1739 #define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
1740 #define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
1741 #define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
1742 #define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
1743 #define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
1744 #define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
1745 #define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
1746 #define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
1747 #define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
1748 #define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
1749 #define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
1750
1751 #define ADC_OFR2_OFFSET2_CH_Pos (26U)
1752 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
1753 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
1754 #define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
1755 #define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
1756 #define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
1757 #define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
1758 #define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
1759
1760 #define ADC_OFR2_OFFSET2_EN_Pos (31U)
1761 #define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
1762 #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
1763
1764 /******************** Bit definition for ADC_OFR3 register ******************/
1765 #define ADC_OFR3_OFFSET3_Pos (0U)
1766 #define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
1767 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
1768 #define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
1769 #define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
1770 #define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
1771 #define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
1772 #define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
1773 #define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
1774 #define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
1775 #define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
1776 #define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
1777 #define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
1778 #define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
1779 #define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
1780
1781 #define ADC_OFR3_OFFSET3_CH_Pos (26U)
1782 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
1783 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
1784 #define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
1785 #define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
1786 #define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
1787 #define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
1788 #define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
1789
1790 #define ADC_OFR3_OFFSET3_EN_Pos (31U)
1791 #define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
1792 #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
1793
1794 /******************** Bit definition for ADC_OFR4 register ******************/
1795 #define ADC_OFR4_OFFSET4_Pos (0U)
1796 #define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
1797 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
1798 #define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
1799 #define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
1800 #define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
1801 #define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
1802 #define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
1803 #define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
1804 #define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
1805 #define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
1806 #define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
1807 #define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
1808 #define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
1809 #define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
1810
1811 #define ADC_OFR4_OFFSET4_CH_Pos (26U)
1812 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
1813 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
1814 #define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
1815 #define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
1816 #define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
1817 #define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
1818 #define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
1819
1820 #define ADC_OFR4_OFFSET4_EN_Pos (31U)
1821 #define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
1822 #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
1823
1824 /******************** Bit definition for ADC_JDR1 register ******************/
1825 #define ADC_JDR1_JDATA_Pos (0U)
1826 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
1827 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
1828 #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
1829 #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
1830 #define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
1831 #define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
1832 #define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
1833 #define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
1834 #define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
1835 #define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
1836 #define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
1837 #define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
1838 #define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
1839 #define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
1840 #define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
1841 #define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
1842 #define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
1843 #define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
1844
1845 /******************** Bit definition for ADC_JDR2 register ******************/
1846 #define ADC_JDR2_JDATA_Pos (0U)
1847 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
1848 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
1849 #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
1850 #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
1851 #define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
1852 #define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
1853 #define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
1854 #define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
1855 #define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
1856 #define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
1857 #define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
1858 #define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
1859 #define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
1860 #define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
1861 #define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
1862 #define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
1863 #define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
1864 #define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
1865
1866 /******************** Bit definition for ADC_JDR3 register ******************/
1867 #define ADC_JDR3_JDATA_Pos (0U)
1868 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
1869 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
1870 #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
1871 #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
1872 #define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
1873 #define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
1874 #define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
1875 #define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
1876 #define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
1877 #define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
1878 #define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
1879 #define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
1880 #define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
1881 #define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
1882 #define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
1883 #define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
1884 #define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
1885 #define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
1886
1887 /******************** Bit definition for ADC_JDR4 register ******************/
1888 #define ADC_JDR4_JDATA_Pos (0U)
1889 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
1890 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
1891 #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
1892 #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
1893 #define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
1894 #define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
1895 #define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
1896 #define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
1897 #define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
1898 #define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
1899 #define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
1900 #define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
1901 #define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
1902 #define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
1903 #define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
1904 #define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
1905 #define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
1906 #define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
1907
1908 /******************** Bit definition for ADC_AWD2CR register ****************/
1909 #define ADC_AWD2CR_AWD2CH_Pos (0U)
1910 #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
1911 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
1912 #define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
1913 #define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
1914 #define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
1915 #define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
1916 #define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
1917 #define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
1918 #define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
1919 #define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
1920 #define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
1921 #define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
1922 #define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
1923 #define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
1924 #define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
1925 #define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
1926 #define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
1927 #define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
1928 #define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
1929 #define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
1930 #define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
1931
1932 /******************** Bit definition for ADC_AWD3CR register ****************/
1933 #define ADC_AWD3CR_AWD3CH_Pos (0U)
1934 #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
1935 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
1936 #define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
1937 #define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
1938 #define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
1939 #define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
1940 #define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
1941 #define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
1942 #define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
1943 #define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
1944 #define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
1945 #define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
1946 #define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
1947 #define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
1948 #define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
1949 #define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
1950 #define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
1951 #define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
1952 #define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
1953 #define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
1954 #define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
1955
1956 /******************** Bit definition for ADC_DIFSEL register ****************/
1957 #define ADC_DIFSEL_DIFSEL_Pos (0U)
1958 #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
1959 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
1960 #define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
1961 #define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
1962 #define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
1963 #define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
1964 #define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
1965 #define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
1966 #define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
1967 #define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
1968 #define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
1969 #define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
1970 #define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
1971 #define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
1972 #define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
1973 #define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
1974 #define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
1975 #define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
1976 #define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
1977 #define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
1978 #define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
1979
1980 /******************** Bit definition for ADC_CALFACT register ***************/
1981 #define ADC_CALFACT_CALFACT_S_Pos (0U)
1982 #define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
1983 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
1984 #define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
1985 #define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
1986 #define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
1987 #define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
1988 #define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
1989 #define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
1990 #define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
1991
1992 #define ADC_CALFACT_CALFACT_D_Pos (16U)
1993 #define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
1994 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
1995 #define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
1996 #define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
1997 #define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
1998 #define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
1999 #define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
2000 #define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
2001 #define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
2002
2003 /************************* ADC Common registers *****************************/
2004 /*************** Bit definition for ADC12_COMMON_CSR register ***************/
2005 #define ADC12_CSR_ADRDY_MST_Pos (0U)
2006 #define ADC12_CSR_ADRDY_MST_Msk (0x1U << ADC12_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
2007 #define ADC12_CSR_ADRDY_MST ADC12_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
2008 #define ADC12_CSR_ADRDY_EOSMP_MST_Pos (1U)
2009 #define ADC12_CSR_ADRDY_EOSMP_MST_Msk (0x1U << ADC12_CSR_ADRDY_EOSMP_MST_Pos) /*!< 0x00000002 */
2010 #define ADC12_CSR_ADRDY_EOSMP_MST ADC12_CSR_ADRDY_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
2011 #define ADC12_CSR_ADRDY_EOC_MST_Pos (2U)
2012 #define ADC12_CSR_ADRDY_EOC_MST_Msk (0x1U << ADC12_CSR_ADRDY_EOC_MST_Pos) /*!< 0x00000004 */
2013 #define ADC12_CSR_ADRDY_EOC_MST ADC12_CSR_ADRDY_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
2014 #define ADC12_CSR_ADRDY_EOS_MST_Pos (3U)
2015 #define ADC12_CSR_ADRDY_EOS_MST_Msk (0x1U << ADC12_CSR_ADRDY_EOS_MST_Pos) /*!< 0x00000008 */
2016 #define ADC12_CSR_ADRDY_EOS_MST ADC12_CSR_ADRDY_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
2017 #define ADC12_CSR_ADRDY_OVR_MST_Pos (4U)
2018 #define ADC12_CSR_ADRDY_OVR_MST_Msk (0x1U << ADC12_CSR_ADRDY_OVR_MST_Pos) /*!< 0x00000010 */
2019 #define ADC12_CSR_ADRDY_OVR_MST ADC12_CSR_ADRDY_OVR_MST_Msk /*!< Overrun flag of the master ADC */
2020 #define ADC12_CSR_ADRDY_JEOC_MST_Pos (5U)
2021 #define ADC12_CSR_ADRDY_JEOC_MST_Msk (0x1U << ADC12_CSR_ADRDY_JEOC_MST_Pos) /*!< 0x00000020 */
2022 #define ADC12_CSR_ADRDY_JEOC_MST ADC12_CSR_ADRDY_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
2023 #define ADC12_CSR_ADRDY_JEOS_MST_Pos (6U)
2024 #define ADC12_CSR_ADRDY_JEOS_MST_Msk (0x1U << ADC12_CSR_ADRDY_JEOS_MST_Pos) /*!< 0x00000040 */
2025 #define ADC12_CSR_ADRDY_JEOS_MST ADC12_CSR_ADRDY_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
2026 #define ADC12_CSR_AWD1_MST_Pos (7U)
2027 #define ADC12_CSR_AWD1_MST_Msk (0x1U << ADC12_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
2028 #define ADC12_CSR_AWD1_MST ADC12_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
2029 #define ADC12_CSR_AWD2_MST_Pos (8U)
2030 #define ADC12_CSR_AWD2_MST_Msk (0x1U << ADC12_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
2031 #define ADC12_CSR_AWD2_MST ADC12_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
2032 #define ADC12_CSR_AWD3_MST_Pos (9U)
2033 #define ADC12_CSR_AWD3_MST_Msk (0x1U << ADC12_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
2034 #define ADC12_CSR_AWD3_MST ADC12_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
2035 #define ADC12_CSR_JQOVF_MST_Pos (10U)
2036 #define ADC12_CSR_JQOVF_MST_Msk (0x1U << ADC12_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
2037 #define ADC12_CSR_JQOVF_MST ADC12_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
2038 #define ADC12_CSR_ADRDY_SLV_Pos (16U)
2039 #define ADC12_CSR_ADRDY_SLV_Msk (0x1U << ADC12_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
2040 #define ADC12_CSR_ADRDY_SLV ADC12_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
2041 #define ADC12_CSR_ADRDY_EOSMP_SLV_Pos (17U)
2042 #define ADC12_CSR_ADRDY_EOSMP_SLV_Msk (0x1U << ADC12_CSR_ADRDY_EOSMP_SLV_Pos) /*!< 0x00020000 */
2043 #define ADC12_CSR_ADRDY_EOSMP_SLV ADC12_CSR_ADRDY_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
2044 #define ADC12_CSR_ADRDY_EOC_SLV_Pos (18U)
2045 #define ADC12_CSR_ADRDY_EOC_SLV_Msk (0x1U << ADC12_CSR_ADRDY_EOC_SLV_Pos) /*!< 0x00040000 */
2046 #define ADC12_CSR_ADRDY_EOC_SLV ADC12_CSR_ADRDY_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
2047 #define ADC12_CSR_ADRDY_EOS_SLV_Pos (19U)
2048 #define ADC12_CSR_ADRDY_EOS_SLV_Msk (0x1U << ADC12_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */
2049 #define ADC12_CSR_ADRDY_EOS_SLV ADC12_CSR_ADRDY_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
2050 #define ADC12_CSR_ADRDY_OVR_SLV_Pos (20U)
2051 #define ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1U << ADC12_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
2052 #define ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
2053 #define ADC12_CSR_ADRDY_JEOC_SLV_Pos (21U)
2054 #define ADC12_CSR_ADRDY_JEOC_SLV_Msk (0x1U << ADC12_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */
2055 #define ADC12_CSR_ADRDY_JEOC_SLV ADC12_CSR_ADRDY_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
2056 #define ADC12_CSR_ADRDY_JEOS_SLV_Pos (22U)
2057 #define ADC12_CSR_ADRDY_JEOS_SLV_Msk (0x1U << ADC12_CSR_ADRDY_JEOS_SLV_Pos) /*!< 0x00400000 */
2058 #define ADC12_CSR_ADRDY_JEOS_SLV ADC12_CSR_ADRDY_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
2059 #define ADC12_CSR_AWD1_SLV_Pos (23U)
2060 #define ADC12_CSR_AWD1_SLV_Msk (0x1U << ADC12_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
2061 #define ADC12_CSR_AWD1_SLV ADC12_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
2062 #define ADC12_CSR_AWD2_SLV_Pos (24U)
2063 #define ADC12_CSR_AWD2_SLV_Msk (0x1U << ADC12_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
2064 #define ADC12_CSR_AWD2_SLV ADC12_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
2065 #define ADC12_CSR_AWD3_SLV_Pos (25U)
2066 #define ADC12_CSR_AWD3_SLV_Msk (0x1U << ADC12_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
2067 #define ADC12_CSR_AWD3_SLV ADC12_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
2068 #define ADC12_CSR_JQOVF_SLV_Pos (26U)
2069 #define ADC12_CSR_JQOVF_SLV_Msk (0x1U << ADC12_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
2070 #define ADC12_CSR_JQOVF_SLV ADC12_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
2071
2072 /*************** Bit definition for ADC34_COMMON_CSR register ***************/
2073 #define ADC34_CSR_ADRDY_MST_Pos (0U)
2074 #define ADC34_CSR_ADRDY_MST_Msk (0x1U << ADC34_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
2075 #define ADC34_CSR_ADRDY_MST ADC34_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
2076 #define ADC34_CSR_ADRDY_EOSMP_MST_Pos (1U)
2077 #define ADC34_CSR_ADRDY_EOSMP_MST_Msk (0x1U << ADC34_CSR_ADRDY_EOSMP_MST_Pos) /*!< 0x00000002 */
2078 #define ADC34_CSR_ADRDY_EOSMP_MST ADC34_CSR_ADRDY_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
2079 #define ADC34_CSR_ADRDY_EOC_MST_Pos (2U)
2080 #define ADC34_CSR_ADRDY_EOC_MST_Msk (0x1U << ADC34_CSR_ADRDY_EOC_MST_Pos) /*!< 0x00000004 */
2081 #define ADC34_CSR_ADRDY_EOC_MST ADC34_CSR_ADRDY_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
2082 #define ADC34_CSR_ADRDY_EOS_MST_Pos (3U)
2083 #define ADC34_CSR_ADRDY_EOS_MST_Msk (0x1U << ADC34_CSR_ADRDY_EOS_MST_Pos) /*!< 0x00000008 */
2084 #define ADC34_CSR_ADRDY_EOS_MST ADC34_CSR_ADRDY_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
2085 #define ADC34_CSR_ADRDY_OVR_MST_Pos (4U)
2086 #define ADC34_CSR_ADRDY_OVR_MST_Msk (0x1U << ADC34_CSR_ADRDY_OVR_MST_Pos) /*!< 0x00000010 */
2087 #define ADC34_CSR_ADRDY_OVR_MST ADC34_CSR_ADRDY_OVR_MST_Msk /*!< Overrun flag of the master ADC */
2088 #define ADC34_CSR_ADRDY_JEOC_MST_Pos (5U)
2089 #define ADC34_CSR_ADRDY_JEOC_MST_Msk (0x1U << ADC34_CSR_ADRDY_JEOC_MST_Pos) /*!< 0x00000020 */
2090 #define ADC34_CSR_ADRDY_JEOC_MST ADC34_CSR_ADRDY_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
2091 #define ADC34_CSR_ADRDY_JEOS_MST_Pos (6U)
2092 #define ADC34_CSR_ADRDY_JEOS_MST_Msk (0x1U << ADC34_CSR_ADRDY_JEOS_MST_Pos) /*!< 0x00000040 */
2093 #define ADC34_CSR_ADRDY_JEOS_MST ADC34_CSR_ADRDY_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
2094 #define ADC34_CSR_AWD1_MST_Pos (7U)
2095 #define ADC34_CSR_AWD1_MST_Msk (0x1U << ADC34_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
2096 #define ADC34_CSR_AWD1_MST ADC34_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
2097 #define ADC34_CSR_AWD2_MST_Pos (8U)
2098 #define ADC34_CSR_AWD2_MST_Msk (0x1U << ADC34_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
2099 #define ADC34_CSR_AWD2_MST ADC34_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
2100 #define ADC34_CSR_AWD3_MST_Pos (9U)
2101 #define ADC34_CSR_AWD3_MST_Msk (0x1U << ADC34_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
2102 #define ADC34_CSR_AWD3_MST ADC34_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
2103 #define ADC34_CSR_JQOVF_MST_Pos (10U)
2104 #define ADC34_CSR_JQOVF_MST_Msk (0x1U << ADC34_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
2105 #define ADC34_CSR_JQOVF_MST ADC34_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
2106 #define ADC34_CSR_ADRDY_SLV_Pos (16U)
2107 #define ADC34_CSR_ADRDY_SLV_Msk (0x1U << ADC34_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
2108 #define ADC34_CSR_ADRDY_SLV ADC34_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
2109 #define ADC34_CSR_ADRDY_EOSMP_SLV_Pos (17U)
2110 #define ADC34_CSR_ADRDY_EOSMP_SLV_Msk (0x1U << ADC34_CSR_ADRDY_EOSMP_SLV_Pos) /*!< 0x00020000 */
2111 #define ADC34_CSR_ADRDY_EOSMP_SLV ADC34_CSR_ADRDY_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
2112 #define ADC34_CSR_ADRDY_EOC_SLV_Pos (18U)
2113 #define ADC34_CSR_ADRDY_EOC_SLV_Msk (0x1U << ADC34_CSR_ADRDY_EOC_SLV_Pos) /*!< 0x00040000 */
2114 #define ADC34_CSR_ADRDY_EOC_SLV ADC34_CSR_ADRDY_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
2115 #define ADC34_CSR_ADRDY_EOS_SLV_Pos (19U)
2116 #define ADC34_CSR_ADRDY_EOS_SLV_Msk (0x1U << ADC34_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */
2117 #define ADC34_CSR_ADRDY_EOS_SLV ADC34_CSR_ADRDY_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
2118 #define ADC12_CSR_ADRDY_OVR_SLV_Pos (20U)
2119 #define ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1U << ADC12_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
2120 #define ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
2121 #define ADC34_CSR_ADRDY_JEOC_SLV_Pos (21U)
2122 #define ADC34_CSR_ADRDY_JEOC_SLV_Msk (0x1U << ADC34_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */
2123 #define ADC34_CSR_ADRDY_JEOC_SLV ADC34_CSR_ADRDY_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
2124 #define ADC34_CSR_ADRDY_JEOS_SLV_Pos (22U)
2125 #define ADC34_CSR_ADRDY_JEOS_SLV_Msk (0x1U << ADC34_CSR_ADRDY_JEOS_SLV_Pos) /*!< 0x00400000 */
2126 #define ADC34_CSR_ADRDY_JEOS_SLV ADC34_CSR_ADRDY_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
2127 #define ADC34_CSR_AWD1_SLV_Pos (23U)
2128 #define ADC34_CSR_AWD1_SLV_Msk (0x1U << ADC34_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
2129 #define ADC34_CSR_AWD1_SLV ADC34_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
2130 #define ADC34_CSR_AWD2_SLV_Pos (24U)
2131 #define ADC34_CSR_AWD2_SLV_Msk (0x1U << ADC34_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
2132 #define ADC34_CSR_AWD2_SLV ADC34_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
2133 #define ADC34_CSR_AWD3_SLV_Pos (25U)
2134 #define ADC34_CSR_AWD3_SLV_Msk (0x1U << ADC34_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
2135 #define ADC34_CSR_AWD3_SLV ADC34_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
2136 #define ADC34_CSR_JQOVF_SLV_Pos (26U)
2137 #define ADC34_CSR_JQOVF_SLV_Msk (0x1U << ADC34_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
2138 #define ADC34_CSR_JQOVF_SLV ADC34_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
2139
2140 /*************** Bit definition for ADC12_COMMON_CCR register ***************/
2141 #define ADC12_CCR_MULTI_Pos (0U)
2142 #define ADC12_CCR_MULTI_Msk (0x1FU << ADC12_CCR_MULTI_Pos) /*!< 0x0000001F */
2143 #define ADC12_CCR_MULTI ADC12_CCR_MULTI_Msk /*!< Multi ADC mode selection */
2144 #define ADC12_CCR_MULTI_0 (0x01U << ADC12_CCR_MULTI_Pos) /*!< 0x00000001 */
2145 #define ADC12_CCR_MULTI_1 (0x02U << ADC12_CCR_MULTI_Pos) /*!< 0x00000002 */
2146 #define ADC12_CCR_MULTI_2 (0x04U << ADC12_CCR_MULTI_Pos) /*!< 0x00000004 */
2147 #define ADC12_CCR_MULTI_3 (0x08U << ADC12_CCR_MULTI_Pos) /*!< 0x00000008 */
2148 #define ADC12_CCR_MULTI_4 (0x10U << ADC12_CCR_MULTI_Pos) /*!< 0x00000010 */
2149 #define ADC12_CCR_DELAY_Pos (8U)
2150 #define ADC12_CCR_DELAY_Msk (0xFU << ADC12_CCR_DELAY_Pos) /*!< 0x00000F00 */
2151 #define ADC12_CCR_DELAY ADC12_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
2152 #define ADC12_CCR_DELAY_0 (0x1U << ADC12_CCR_DELAY_Pos) /*!< 0x00000100 */
2153 #define ADC12_CCR_DELAY_1 (0x2U << ADC12_CCR_DELAY_Pos) /*!< 0x00000200 */
2154 #define ADC12_CCR_DELAY_2 (0x4U << ADC12_CCR_DELAY_Pos) /*!< 0x00000400 */
2155 #define ADC12_CCR_DELAY_3 (0x8U << ADC12_CCR_DELAY_Pos) /*!< 0x00000800 */
2156 #define ADC12_CCR_DMACFG_Pos (13U)
2157 #define ADC12_CCR_DMACFG_Msk (0x1U << ADC12_CCR_DMACFG_Pos) /*!< 0x00002000 */
2158 #define ADC12_CCR_DMACFG ADC12_CCR_DMACFG_Msk /*!< DMA configuration for multi-ADC mode */
2159 #define ADC12_CCR_MDMA_Pos (14U)
2160 #define ADC12_CCR_MDMA_Msk (0x3U << ADC12_CCR_MDMA_Pos) /*!< 0x0000C000 */
2161 #define ADC12_CCR_MDMA ADC12_CCR_MDMA_Msk /*!< DMA mode for multi-ADC mode */
2162 #define ADC12_CCR_MDMA_0 (0x1U << ADC12_CCR_MDMA_Pos) /*!< 0x00004000 */
2163 #define ADC12_CCR_MDMA_1 (0x2U << ADC12_CCR_MDMA_Pos) /*!< 0x00008000 */
2164 #define ADC12_CCR_CKMODE_Pos (16U)
2165 #define ADC12_CCR_CKMODE_Msk (0x3U << ADC12_CCR_CKMODE_Pos) /*!< 0x00030000 */
2166 #define ADC12_CCR_CKMODE ADC12_CCR_CKMODE_Msk /*!< ADC clock mode */
2167 #define ADC12_CCR_CKMODE_0 (0x1U << ADC12_CCR_CKMODE_Pos) /*!< 0x00010000 */
2168 #define ADC12_CCR_CKMODE_1 (0x2U << ADC12_CCR_CKMODE_Pos) /*!< 0x00020000 */
2169 #define ADC12_CCR_VREFEN_Pos (22U)
2170 #define ADC12_CCR_VREFEN_Msk (0x1U << ADC12_CCR_VREFEN_Pos) /*!< 0x00400000 */
2171 #define ADC12_CCR_VREFEN ADC12_CCR_VREFEN_Msk /*!< VREFINT enable */
2172 #define ADC12_CCR_TSEN_Pos (23U)
2173 #define ADC12_CCR_TSEN_Msk (0x1U << ADC12_CCR_TSEN_Pos) /*!< 0x00800000 */
2174 #define ADC12_CCR_TSEN ADC12_CCR_TSEN_Msk /*!< Temperature sensor enable */
2175 #define ADC12_CCR_VBATEN_Pos (24U)
2176 #define ADC12_CCR_VBATEN_Msk (0x1U << ADC12_CCR_VBATEN_Pos) /*!< 0x01000000 */
2177 #define ADC12_CCR_VBATEN ADC12_CCR_VBATEN_Msk /*!< VBAT enable */
2178
2179 /*************** Bit definition for ADC34_COMMON_CCR register ***************/
2180 #define ADC34_CCR_MULTI_Pos (0U)
2181 #define ADC34_CCR_MULTI_Msk (0x1FU << ADC34_CCR_MULTI_Pos) /*!< 0x0000001F */
2182 #define ADC34_CCR_MULTI ADC34_CCR_MULTI_Msk /*!< Multi ADC mode selection */
2183 #define ADC34_CCR_MULTI_0 (0x01U << ADC34_CCR_MULTI_Pos) /*!< 0x00000001 */
2184 #define ADC34_CCR_MULTI_1 (0x02U << ADC34_CCR_MULTI_Pos) /*!< 0x00000002 */
2185 #define ADC34_CCR_MULTI_2 (0x04U << ADC34_CCR_MULTI_Pos) /*!< 0x00000004 */
2186 #define ADC34_CCR_MULTI_3 (0x08U << ADC34_CCR_MULTI_Pos) /*!< 0x00000008 */
2187 #define ADC34_CCR_MULTI_4 (0x10U << ADC34_CCR_MULTI_Pos) /*!< 0x00000010 */
2188
2189 #define ADC34_CCR_DELAY_Pos (8U)
2190 #define ADC34_CCR_DELAY_Msk (0xFU << ADC34_CCR_DELAY_Pos) /*!< 0x00000F00 */
2191 #define ADC34_CCR_DELAY ADC34_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
2192 #define ADC34_CCR_DELAY_0 (0x1U << ADC34_CCR_DELAY_Pos) /*!< 0x00000100 */
2193 #define ADC34_CCR_DELAY_1 (0x2U << ADC34_CCR_DELAY_Pos) /*!< 0x00000200 */
2194 #define ADC34_CCR_DELAY_2 (0x4U << ADC34_CCR_DELAY_Pos) /*!< 0x00000400 */
2195 #define ADC34_CCR_DELAY_3 (0x8U << ADC34_CCR_DELAY_Pos) /*!< 0x00000800 */
2196
2197 #define ADC34_CCR_DMACFG_Pos (13U)
2198 #define ADC34_CCR_DMACFG_Msk (0x1U << ADC34_CCR_DMACFG_Pos) /*!< 0x00002000 */
2199 #define ADC34_CCR_DMACFG ADC34_CCR_DMACFG_Msk /*!< DMA configuration for multi-ADC mode */
2200 #define ADC34_CCR_MDMA_Pos (14U)
2201 #define ADC34_CCR_MDMA_Msk (0x3U << ADC34_CCR_MDMA_Pos) /*!< 0x0000C000 */
2202 #define ADC34_CCR_MDMA ADC34_CCR_MDMA_Msk /*!< DMA mode for multi-ADC mode */
2203 #define ADC34_CCR_MDMA_0 (0x1U << ADC34_CCR_MDMA_Pos) /*!< 0x00004000 */
2204 #define ADC34_CCR_MDMA_1 (0x2U << ADC34_CCR_MDMA_Pos) /*!< 0x00008000 */
2205
2206 #define ADC34_CCR_CKMODE_Pos (16U)
2207 #define ADC34_CCR_CKMODE_Msk (0x3U << ADC34_CCR_CKMODE_Pos) /*!< 0x00030000 */
2208 #define ADC34_CCR_CKMODE ADC34_CCR_CKMODE_Msk /*!< ADC clock mode */
2209 #define ADC34_CCR_CKMODE_0 (0x1U << ADC34_CCR_CKMODE_Pos) /*!< 0x00010000 */
2210 #define ADC34_CCR_CKMODE_1 (0x2U << ADC34_CCR_CKMODE_Pos) /*!< 0x00020000 */
2211
2212 #define ADC34_CCR_VREFEN_Pos (22U)
2213 #define ADC34_CCR_VREFEN_Msk (0x1U << ADC34_CCR_VREFEN_Pos) /*!< 0x00400000 */
2214 #define ADC34_CCR_VREFEN ADC34_CCR_VREFEN_Msk /*!< VREFINT enable */
2215 #define ADC34_CCR_TSEN_Pos (23U)
2216 #define ADC34_CCR_TSEN_Msk (0x1U << ADC34_CCR_TSEN_Pos) /*!< 0x00800000 */
2217 #define ADC34_CCR_TSEN ADC34_CCR_TSEN_Msk /*!< Temperature sensor enable */
2218 #define ADC34_CCR_VBATEN_Pos (24U)
2219 #define ADC34_CCR_VBATEN_Msk (0x1U << ADC34_CCR_VBATEN_Pos) /*!< 0x01000000 */
2220 #define ADC34_CCR_VBATEN ADC34_CCR_VBATEN_Msk /*!< VBAT enable */
2221
2222 /*************** Bit definition for ADC12_COMMON_CDR register ***************/
2223 #define ADC12_CDR_RDATA_MST_Pos (0U)
2224 #define ADC12_CDR_RDATA_MST_Msk (0xFFFFU << ADC12_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
2225 #define ADC12_CDR_RDATA_MST ADC12_CDR_RDATA_MST_Msk /*!< Regular Data of the master ADC */
2226 #define ADC12_CDR_RDATA_MST_0 (0x0001U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
2227 #define ADC12_CDR_RDATA_MST_1 (0x0002U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
2228 #define ADC12_CDR_RDATA_MST_2 (0x0004U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
2229 #define ADC12_CDR_RDATA_MST_3 (0x0008U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
2230 #define ADC12_CDR_RDATA_MST_4 (0x0010U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
2231 #define ADC12_CDR_RDATA_MST_5 (0x0020U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
2232 #define ADC12_CDR_RDATA_MST_6 (0x0040U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
2233 #define ADC12_CDR_RDATA_MST_7 (0x0080U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
2234 #define ADC12_CDR_RDATA_MST_8 (0x0100U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
2235 #define ADC12_CDR_RDATA_MST_9 (0x0200U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
2236 #define ADC12_CDR_RDATA_MST_10 (0x0400U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
2237 #define ADC12_CDR_RDATA_MST_11 (0x0800U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
2238 #define ADC12_CDR_RDATA_MST_12 (0x1000U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
2239 #define ADC12_CDR_RDATA_MST_13 (0x2000U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
2240 #define ADC12_CDR_RDATA_MST_14 (0x4000U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
2241 #define ADC12_CDR_RDATA_MST_15 (0x8000U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
2242
2243 #define ADC12_CDR_RDATA_SLV_Pos (16U)
2244 #define ADC12_CDR_RDATA_SLV_Msk (0xFFFFU << ADC12_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
2245 #define ADC12_CDR_RDATA_SLV ADC12_CDR_RDATA_SLV_Msk /*!< Regular Data of the master ADC */
2246 #define ADC12_CDR_RDATA_SLV_0 (0x0001U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
2247 #define ADC12_CDR_RDATA_SLV_1 (0x0002U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
2248 #define ADC12_CDR_RDATA_SLV_2 (0x0004U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
2249 #define ADC12_CDR_RDATA_SLV_3 (0x0008U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
2250 #define ADC12_CDR_RDATA_SLV_4 (0x0010U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
2251 #define ADC12_CDR_RDATA_SLV_5 (0x0020U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
2252 #define ADC12_CDR_RDATA_SLV_6 (0x0040U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
2253 #define ADC12_CDR_RDATA_SLV_7 (0x0080U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
2254 #define ADC12_CDR_RDATA_SLV_8 (0x0100U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
2255 #define ADC12_CDR_RDATA_SLV_9 (0x0200U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
2256 #define ADC12_CDR_RDATA_SLV_10 (0x0400U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
2257 #define ADC12_CDR_RDATA_SLV_11 (0x0800U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
2258 #define ADC12_CDR_RDATA_SLV_12 (0x1000U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
2259 #define ADC12_CDR_RDATA_SLV_13 (0x2000U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
2260 #define ADC12_CDR_RDATA_SLV_14 (0x4000U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
2261 #define ADC12_CDR_RDATA_SLV_15 (0x8000U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
2262
2263 /*************** Bit definition for ADC34_COMMON_CDR register ***************/
2264 #define ADC34_CDR_RDATA_MST_Pos (0U)
2265 #define ADC34_CDR_RDATA_MST_Msk (0xFFFFU << ADC34_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
2266 #define ADC34_CDR_RDATA_MST ADC34_CDR_RDATA_MST_Msk /*!< Regular Data of the master ADC */
2267 #define ADC34_CDR_RDATA_MST_0 (0x0001U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
2268 #define ADC34_CDR_RDATA_MST_1 (0x0002U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
2269 #define ADC34_CDR_RDATA_MST_2 (0x0004U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
2270 #define ADC34_CDR_RDATA_MST_3 (0x0008U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
2271 #define ADC34_CDR_RDATA_MST_4 (0x0010U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
2272 #define ADC34_CDR_RDATA_MST_5 (0x0020U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
2273 #define ADC34_CDR_RDATA_MST_6 (0x0040U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
2274 #define ADC34_CDR_RDATA_MST_7 (0x0080U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
2275 #define ADC34_CDR_RDATA_MST_8 (0x0100U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
2276 #define ADC34_CDR_RDATA_MST_9 (0x0200U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
2277 #define ADC34_CDR_RDATA_MST_10 (0x0400U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
2278 #define ADC34_CDR_RDATA_MST_11 (0x0800U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
2279 #define ADC34_CDR_RDATA_MST_12 (0x1000U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
2280 #define ADC34_CDR_RDATA_MST_13 (0x2000U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
2281 #define ADC34_CDR_RDATA_MST_14 (0x4000U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
2282 #define ADC34_CDR_RDATA_MST_15 (0x8000U << ADC34_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
2283
2284 #define ADC34_CDR_RDATA_SLV_Pos (16U)
2285 #define ADC34_CDR_RDATA_SLV_Msk (0xFFFFU << ADC34_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
2286 #define ADC34_CDR_RDATA_SLV ADC34_CDR_RDATA_SLV_Msk /*!< Regular Data of the master ADC */
2287 #define ADC34_CDR_RDATA_SLV_0 (0x0001U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
2288 #define ADC34_CDR_RDATA_SLV_1 (0x0002U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
2289 #define ADC34_CDR_RDATA_SLV_2 (0x0004U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
2290 #define ADC34_CDR_RDATA_SLV_3 (0x0008U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
2291 #define ADC34_CDR_RDATA_SLV_4 (0x0010U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
2292 #define ADC34_CDR_RDATA_SLV_5 (0x0020U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
2293 #define ADC34_CDR_RDATA_SLV_6 (0x0040U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
2294 #define ADC34_CDR_RDATA_SLV_7 (0x0080U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
2295 #define ADC34_CDR_RDATA_SLV_8 (0x0100U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
2296 #define ADC34_CDR_RDATA_SLV_9 (0x0200U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
2297 #define ADC34_CDR_RDATA_SLV_10 (0x0400U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
2298 #define ADC34_CDR_RDATA_SLV_11 (0x0800U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
2299 #define ADC34_CDR_RDATA_SLV_12 (0x1000U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
2300 #define ADC34_CDR_RDATA_SLV_13 (0x2000U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
2301 #define ADC34_CDR_RDATA_SLV_14 (0x4000U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
2302 #define ADC34_CDR_RDATA_SLV_15 (0x8000U << ADC34_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
2303
2304 /******************** Bit definition for ADC_CSR register *******************/
2305 #define ADC_CSR_ADRDY_MST_Pos (0U)
2306 #define ADC_CSR_ADRDY_MST_Msk (0x1U << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
2307 #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */
2308 #define ADC_CSR_EOSMP_MST_Pos (1U)
2309 #define ADC_CSR_EOSMP_MST_Msk (0x1U << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
2310 #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */
2311 #define ADC_CSR_EOC_MST_Pos (2U)
2312 #define ADC_CSR_EOC_MST_Msk (0x1U << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
2313 #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */
2314 #define ADC_CSR_EOS_MST_Pos (3U)
2315 #define ADC_CSR_EOS_MST_Msk (0x1U << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
2316 #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */
2317 #define ADC_CSR_OVR_MST_Pos (4U)
2318 #define ADC_CSR_OVR_MST_Msk (0x1U << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
2319 #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */
2320 #define ADC_CSR_JEOC_MST_Pos (5U)
2321 #define ADC_CSR_JEOC_MST_Msk (0x1U << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
2322 #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */
2323 #define ADC_CSR_JEOS_MST_Pos (6U)
2324 #define ADC_CSR_JEOS_MST_Msk (0x1U << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
2325 #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
2326 #define ADC_CSR_AWD1_MST_Pos (7U)
2327 #define ADC_CSR_AWD1_MST_Msk (0x1U << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
2328 #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */
2329 #define ADC_CSR_AWD2_MST_Pos (8U)
2330 #define ADC_CSR_AWD2_MST_Msk (0x1U << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
2331 #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */
2332 #define ADC_CSR_AWD3_MST_Pos (9U)
2333 #define ADC_CSR_AWD3_MST_Msk (0x1U << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
2334 #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */
2335 #define ADC_CSR_JQOVF_MST_Pos (10U)
2336 #define ADC_CSR_JQOVF_MST_Msk (0x1U << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
2337 #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */
2338
2339 #define ADC_CSR_ADRDY_SLV_Pos (16U)
2340 #define ADC_CSR_ADRDY_SLV_Msk (0x1U << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
2341 #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */
2342 #define ADC_CSR_EOSMP_SLV_Pos (17U)
2343 #define ADC_CSR_EOSMP_SLV_Msk (0x1U << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
2344 #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */
2345 #define ADC_CSR_EOC_SLV_Pos (18U)
2346 #define ADC_CSR_EOC_SLV_Msk (0x1U << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
2347 #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */
2348 #define ADC_CSR_EOS_SLV_Pos (19U)
2349 #define ADC_CSR_EOS_SLV_Msk (0x1U << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
2350 #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */
2351 #define ADC_CSR_OVR_SLV_Pos (20U)
2352 #define ADC_CSR_OVR_SLV_Msk (0x1U << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
2353 #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */
2354 #define ADC_CSR_JEOC_SLV_Pos (21U)
2355 #define ADC_CSR_JEOC_SLV_Msk (0x1U << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
2356 #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */
2357 #define ADC_CSR_JEOS_SLV_Pos (22U)
2358 #define ADC_CSR_JEOS_SLV_Msk (0x1U << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
2359 #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */
2360 #define ADC_CSR_AWD1_SLV_Pos (23U)
2361 #define ADC_CSR_AWD1_SLV_Msk (0x1U << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
2362 #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */
2363 #define ADC_CSR_AWD2_SLV_Pos (24U)
2364 #define ADC_CSR_AWD2_SLV_Msk (0x1U << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
2365 #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */
2366 #define ADC_CSR_AWD3_SLV_Pos (25U)
2367 #define ADC_CSR_AWD3_SLV_Msk (0x1U << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
2368 #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */
2369 #define ADC_CSR_JQOVF_SLV_Pos (26U)
2370 #define ADC_CSR_JQOVF_SLV_Msk (0x1U << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
2371 #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */
2372
2373 /* Legacy defines */
2374 #define ADC_CSR_ADRDY_EOSMP_MST ADC_CSR_EOSMP_MST
2375 #define ADC_CSR_ADRDY_EOC_MST ADC_CSR_EOC_MST
2376 #define ADC_CSR_ADRDY_EOS_MST ADC_CSR_EOS_MST
2377 #define ADC_CSR_ADRDY_OVR_MST ADC_CSR_OVR_MST
2378 #define ADC_CSR_ADRDY_JEOC_MST ADC_CSR_JEOC_MST
2379 #define ADC_CSR_ADRDY_JEOS_MST ADC_CSR_JEOS_MST
2380
2381 #define ADC_CSR_ADRDY_EOSMP_SLV ADC_CSR_EOSMP_SLV
2382 #define ADC_CSR_ADRDY_EOC_SLV ADC_CSR_EOC_SLV
2383 #define ADC_CSR_ADRDY_EOS_SLV ADC_CSR_EOS_SLV
2384 #define ADC_CSR_ADRDY_OVR_SLV ADC_CSR_OVR_SLV
2385 #define ADC_CSR_ADRDY_JEOC_SLV ADC_CSR_JEOC_SLV
2386 #define ADC_CSR_ADRDY_JEOS_SLV ADC_CSR_JEOS_SLV
2387
2388 /******************** Bit definition for ADC_CCR register *******************/
2389 #define ADC_CCR_DUAL_Pos (0U)
2390 #define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
2391 #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
2392 #define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
2393 #define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
2394 #define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
2395 #define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
2396 #define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
2397
2398 #define ADC_CCR_DELAY_Pos (8U)
2399 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
2400 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
2401 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
2402 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
2403 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
2404 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
2405
2406 #define ADC_CCR_DMACFG_Pos (13U)
2407 #define ADC_CCR_DMACFG_Msk (0x1U << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */
2408 #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */
2409
2410 #define ADC_CCR_MDMA_Pos (14U)
2411 #define ADC_CCR_MDMA_Msk (0x3U << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */
2412 #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */
2413 #define ADC_CCR_MDMA_0 (0x1U << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */
2414 #define ADC_CCR_MDMA_1 (0x2U << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */
2415
2416 #define ADC_CCR_CKMODE_Pos (16U)
2417 #define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
2418 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2419 #define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
2420 #define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
2421
2422 #define ADC_CCR_VREFEN_Pos (22U)
2423 #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
2424 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
2425 #define ADC_CCR_TSEN_Pos (23U)
2426 #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
2427 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
2428 #define ADC_CCR_VBATEN_Pos (24U)
2429 #define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
2430 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
2431
2432 /* Legacy defines */
2433 #define ADC_CCR_MULTI (ADC_CCR_DUAL)
2434 #define ADC_CCR_MULTI_0 (ADC_CCR_DUAL_0)
2435 #define ADC_CCR_MULTI_1 (ADC_CCR_DUAL_1)
2436 #define ADC_CCR_MULTI_2 (ADC_CCR_DUAL_2)
2437 #define ADC_CCR_MULTI_3 (ADC_CCR_DUAL_3)
2438 #define ADC_CCR_MULTI_4 (ADC_CCR_DUAL_4)
2439
2440 /******************** Bit definition for ADC_CDR register *******************/
2441 #define ADC_CDR_RDATA_MST_Pos (0U)
2442 #define ADC_CDR_RDATA_MST_Msk (0xFFFFU << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
2443 #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
2444 #define ADC_CDR_RDATA_MST_0 (0x0001U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
2445 #define ADC_CDR_RDATA_MST_1 (0x0002U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
2446 #define ADC_CDR_RDATA_MST_2 (0x0004U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
2447 #define ADC_CDR_RDATA_MST_3 (0x0008U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
2448 #define ADC_CDR_RDATA_MST_4 (0x0010U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
2449 #define ADC_CDR_RDATA_MST_5 (0x0020U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
2450 #define ADC_CDR_RDATA_MST_6 (0x0040U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
2451 #define ADC_CDR_RDATA_MST_7 (0x0080U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
2452 #define ADC_CDR_RDATA_MST_8 (0x0100U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
2453 #define ADC_CDR_RDATA_MST_9 (0x0200U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
2454 #define ADC_CDR_RDATA_MST_10 (0x0400U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
2455 #define ADC_CDR_RDATA_MST_11 (0x0800U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
2456 #define ADC_CDR_RDATA_MST_12 (0x1000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
2457 #define ADC_CDR_RDATA_MST_13 (0x2000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
2458 #define ADC_CDR_RDATA_MST_14 (0x4000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
2459 #define ADC_CDR_RDATA_MST_15 (0x8000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
2460
2461 #define ADC_CDR_RDATA_SLV_Pos (16U)
2462 #define ADC_CDR_RDATA_SLV_Msk (0xFFFFU << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
2463 #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
2464 #define ADC_CDR_RDATA_SLV_0 (0x0001U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
2465 #define ADC_CDR_RDATA_SLV_1 (0x0002U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
2466 #define ADC_CDR_RDATA_SLV_2 (0x0004U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
2467 #define ADC_CDR_RDATA_SLV_3 (0x0008U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
2468 #define ADC_CDR_RDATA_SLV_4 (0x0010U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
2469 #define ADC_CDR_RDATA_SLV_5 (0x0020U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
2470 #define ADC_CDR_RDATA_SLV_6 (0x0040U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
2471 #define ADC_CDR_RDATA_SLV_7 (0x0080U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
2472 #define ADC_CDR_RDATA_SLV_8 (0x0100U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
2473 #define ADC_CDR_RDATA_SLV_9 (0x0200U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
2474 #define ADC_CDR_RDATA_SLV_10 (0x0400U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
2475 #define ADC_CDR_RDATA_SLV_11 (0x0800U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
2476 #define ADC_CDR_RDATA_SLV_12 (0x1000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
2477 #define ADC_CDR_RDATA_SLV_13 (0x2000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
2478 #define ADC_CDR_RDATA_SLV_14 (0x4000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
2479 #define ADC_CDR_RDATA_SLV_15 (0x8000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
2480
2481 /******************************************************************************/
2482 /* */
2483 /* Analog Comparators (COMP) */
2484 /* */
2485 /******************************************************************************/
2486
2487 #define COMP_V1_3_0_0 /*!< Comparator IP version */
2488
2489 /********************** Bit definition for COMP1_CSR register ***************/
2490 #define COMP1_CSR_COMP1EN_Pos (0U)
2491 #define COMP1_CSR_COMP1EN_Msk (0x1U << COMP1_CSR_COMP1EN_Pos) /*!< 0x00000001 */
2492 #define COMP1_CSR_COMP1EN COMP1_CSR_COMP1EN_Msk /*!< COMP1 enable */
2493 #define COMP1_CSR_COMP1SW1_Pos (1U)
2494 #define COMP1_CSR_COMP1SW1_Msk (0x1U << COMP1_CSR_COMP1SW1_Pos) /*!< 0x00000002 */
2495 #define COMP1_CSR_COMP1SW1 COMP1_CSR_COMP1SW1_Msk /*!< COMP1 SW1 switch control */
2496 /* Legacy defines */
2497 #define COMP_CSR_COMP1SW1 COMP1_CSR_COMP1SW1
2498 #define COMP1_CSR_COMP1INSEL_Pos (4U)
2499 #define COMP1_CSR_COMP1INSEL_Msk (0x7U << COMP1_CSR_COMP1INSEL_Pos) /*!< 0x00000070 */
2500 #define COMP1_CSR_COMP1INSEL COMP1_CSR_COMP1INSEL_Msk /*!< COMP1 inverting input select */
2501 #define COMP1_CSR_COMP1INSEL_0 (0x1U << COMP1_CSR_COMP1INSEL_Pos) /*!< 0x00000010 */
2502 #define COMP1_CSR_COMP1INSEL_1 (0x2U << COMP1_CSR_COMP1INSEL_Pos) /*!< 0x00000020 */
2503 #define COMP1_CSR_COMP1INSEL_2 (0x4U << COMP1_CSR_COMP1INSEL_Pos) /*!< 0x00000040 */
2504 #define COMP1_CSR_COMP1OUTSEL_Pos (10U)
2505 #define COMP1_CSR_COMP1OUTSEL_Msk (0xFU << COMP1_CSR_COMP1OUTSEL_Pos) /*!< 0x00003C00 */
2506 #define COMP1_CSR_COMP1OUTSEL COMP1_CSR_COMP1OUTSEL_Msk /*!< COMP1 output select */
2507 #define COMP1_CSR_COMP1OUTSEL_0 (0x1U << COMP1_CSR_COMP1OUTSEL_Pos) /*!< 0x00000400 */
2508 #define COMP1_CSR_COMP1OUTSEL_1 (0x2U << COMP1_CSR_COMP1OUTSEL_Pos) /*!< 0x00000800 */
2509 #define COMP1_CSR_COMP1OUTSEL_2 (0x4U << COMP1_CSR_COMP1OUTSEL_Pos) /*!< 0x00001000 */
2510 #define COMP1_CSR_COMP1OUTSEL_3 (0x8U << COMP1_CSR_COMP1OUTSEL_Pos) /*!< 0x00002000 */
2511 #define COMP1_CSR_COMP1POL_Pos (15U)
2512 #define COMP1_CSR_COMP1POL_Msk (0x1U << COMP1_CSR_COMP1POL_Pos) /*!< 0x00008000 */
2513 #define COMP1_CSR_COMP1POL COMP1_CSR_COMP1POL_Msk /*!< COMP1 output polarity */
2514 #define COMP1_CSR_COMP1BLANKING_Pos (18U)
2515 #define COMP1_CSR_COMP1BLANKING_Msk (0x3U << COMP1_CSR_COMP1BLANKING_Pos) /*!< 0x000C0000 */
2516 #define COMP1_CSR_COMP1BLANKING COMP1_CSR_COMP1BLANKING_Msk /*!< COMP1 blanking */
2517 #define COMP1_CSR_COMP1BLANKING_0 (0x1U << COMP1_CSR_COMP1BLANKING_Pos) /*!< 0x00040000 */
2518 #define COMP1_CSR_COMP1BLANKING_1 (0x2U << COMP1_CSR_COMP1BLANKING_Pos) /*!< 0x00080000 */
2519 #define COMP1_CSR_COMP1BLANKING_2 (0x4U << COMP1_CSR_COMP1BLANKING_Pos) /*!< 0x00100000 */
2520 #define COMP1_CSR_COMP1OUT_Pos (30U)
2521 #define COMP1_CSR_COMP1OUT_Msk (0x1U << COMP1_CSR_COMP1OUT_Pos) /*!< 0x40000000 */
2522 #define COMP1_CSR_COMP1OUT COMP1_CSR_COMP1OUT_Msk /*!< COMP1 output level */
2523 #define COMP1_CSR_COMP1LOCK_Pos (31U)
2524 #define COMP1_CSR_COMP1LOCK_Msk (0x1U << COMP1_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
2525 #define COMP1_CSR_COMP1LOCK COMP1_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
2526
2527 /********************** Bit definition for COMP2_CSR register ***************/
2528 #define COMP2_CSR_COMP2EN_Pos (0U)
2529 #define COMP2_CSR_COMP2EN_Msk (0x1U << COMP2_CSR_COMP2EN_Pos) /*!< 0x00000001 */
2530 #define COMP2_CSR_COMP2EN COMP2_CSR_COMP2EN_Msk /*!< COMP2 enable */
2531 #define COMP2_CSR_COMP2INSEL_Pos (4U)
2532 #define COMP2_CSR_COMP2INSEL_Msk (0x7U << COMP2_CSR_COMP2INSEL_Pos) /*!< 0x00000070 */
2533 #define COMP2_CSR_COMP2INSEL COMP2_CSR_COMP2INSEL_Msk /*!< COMP2 inverting input select */
2534 #define COMP2_CSR_COMP2INSEL_0 (0x00000010U) /*!< COMP2 inverting input select bit 0 */
2535 #define COMP2_CSR_COMP2INSEL_1 (0x00000020U) /*!< COMP2 inverting input select bit 1 */
2536 #define COMP2_CSR_COMP2INSEL_2 (0x00000040U) /*!< COMP2 inverting input select bit 2 */
2537 #define COMP2_CSR_COMP2OUTSEL_Pos (10U)
2538 #define COMP2_CSR_COMP2OUTSEL_Msk (0xFU << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00003C00 */
2539 #define COMP2_CSR_COMP2OUTSEL COMP2_CSR_COMP2OUTSEL_Msk /*!< COMP2 output select */
2540 #define COMP2_CSR_COMP2OUTSEL_0 (0x1U << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00000400 */
2541 #define COMP2_CSR_COMP2OUTSEL_1 (0x2U << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00000800 */
2542 #define COMP2_CSR_COMP2OUTSEL_2 (0x4U << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00001000 */
2543 #define COMP2_CSR_COMP2OUTSEL_3 (0x8U << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00002000 */
2544 #define COMP2_CSR_COMP2POL_Pos (15U)
2545 #define COMP2_CSR_COMP2POL_Msk (0x1U << COMP2_CSR_COMP2POL_Pos) /*!< 0x00008000 */
2546 #define COMP2_CSR_COMP2POL COMP2_CSR_COMP2POL_Msk /*!< COMP2 output polarity */
2547 #define COMP2_CSR_COMP2BLANKING_Pos (18U)
2548 #define COMP2_CSR_COMP2BLANKING_Msk (0x3U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x000C0000 */
2549 #define COMP2_CSR_COMP2BLANKING COMP2_CSR_COMP2BLANKING_Msk /*!< COMP2 blanking */
2550 #define COMP2_CSR_COMP2BLANKING_0 (0x1U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00040000 */
2551 #define COMP2_CSR_COMP2BLANKING_1 (0x2U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00080000 */
2552 #define COMP2_CSR_COMP2BLANKING_2 (0x4U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00100000 */
2553 #define COMP2_CSR_COMP2OUT_Pos (30U)
2554 #define COMP2_CSR_COMP2OUT_Msk (0x1U << COMP2_CSR_COMP2OUT_Pos) /*!< 0x40000000 */
2555 #define COMP2_CSR_COMP2OUT COMP2_CSR_COMP2OUT_Msk /*!< COMP2 output level */
2556 #define COMP2_CSR_COMP2LOCK_Pos (31U)
2557 #define COMP2_CSR_COMP2LOCK_Msk (0x1U << COMP2_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
2558 #define COMP2_CSR_COMP2LOCK COMP2_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
2559
2560 /********************** Bit definition for COMP3_CSR register ***************/
2561 #define COMP3_CSR_COMP3EN_Pos (0U)
2562 #define COMP3_CSR_COMP3EN_Msk (0x1U << COMP3_CSR_COMP3EN_Pos) /*!< 0x00000001 */
2563 #define COMP3_CSR_COMP3EN COMP3_CSR_COMP3EN_Msk /*!< COMP3 enable */
2564 #define COMP3_CSR_COMP3INSEL_Pos (4U)
2565 #define COMP3_CSR_COMP3INSEL_Msk (0x7U << COMP3_CSR_COMP3INSEL_Pos) /*!< 0x00000070 */
2566 #define COMP3_CSR_COMP3INSEL COMP3_CSR_COMP3INSEL_Msk /*!< COMP3 inverting input select */
2567 #define COMP3_CSR_COMP3INSEL_0 (0x1U << COMP3_CSR_COMP3INSEL_Pos) /*!< 0x00000010 */
2568 #define COMP3_CSR_COMP3INSEL_1 (0x2U << COMP3_CSR_COMP3INSEL_Pos) /*!< 0x00000020 */
2569 #define COMP3_CSR_COMP3INSEL_2 (0x4U << COMP3_CSR_COMP3INSEL_Pos) /*!< 0x00000040 */
2570 #define COMP3_CSR_COMP3OUTSEL_Pos (10U)
2571 #define COMP3_CSR_COMP3OUTSEL_Msk (0xFU << COMP3_CSR_COMP3OUTSEL_Pos) /*!< 0x00003C00 */
2572 #define COMP3_CSR_COMP3OUTSEL COMP3_CSR_COMP3OUTSEL_Msk /*!< COMP3 output select */
2573 #define COMP3_CSR_COMP3OUTSEL_0 (0x1U << COMP3_CSR_COMP3OUTSEL_Pos) /*!< 0x00000400 */
2574 #define COMP3_CSR_COMP3OUTSEL_1 (0x2U << COMP3_CSR_COMP3OUTSEL_Pos) /*!< 0x00000800 */
2575 #define COMP3_CSR_COMP3OUTSEL_2 (0x4U << COMP3_CSR_COMP3OUTSEL_Pos) /*!< 0x00001000 */
2576 #define COMP3_CSR_COMP3OUTSEL_3 (0x8U << COMP3_CSR_COMP3OUTSEL_Pos) /*!< 0x00002000 */
2577 #define COMP3_CSR_COMP3POL_Pos (15U)
2578 #define COMP3_CSR_COMP3POL_Msk (0x1U << COMP3_CSR_COMP3POL_Pos) /*!< 0x00008000 */
2579 #define COMP3_CSR_COMP3POL COMP3_CSR_COMP3POL_Msk /*!< COMP3 output polarity */
2580 #define COMP3_CSR_COMP3BLANKING_Pos (18U)
2581 #define COMP3_CSR_COMP3BLANKING_Msk (0x3U << COMP3_CSR_COMP3BLANKING_Pos) /*!< 0x000C0000 */
2582 #define COMP3_CSR_COMP3BLANKING COMP3_CSR_COMP3BLANKING_Msk /*!< COMP3 blanking */
2583 #define COMP3_CSR_COMP3BLANKING_0 (0x1U << COMP3_CSR_COMP3BLANKING_Pos) /*!< 0x00040000 */
2584 #define COMP3_CSR_COMP3BLANKING_1 (0x2U << COMP3_CSR_COMP3BLANKING_Pos) /*!< 0x00080000 */
2585 #define COMP3_CSR_COMP3BLANKING_2 (0x4U << COMP3_CSR_COMP3BLANKING_Pos) /*!< 0x00100000 */
2586 #define COMP3_CSR_COMP3OUT_Pos (30U)
2587 #define COMP3_CSR_COMP3OUT_Msk (0x1U << COMP3_CSR_COMP3OUT_Pos) /*!< 0x40000000 */
2588 #define COMP3_CSR_COMP3OUT COMP3_CSR_COMP3OUT_Msk /*!< COMP3 output level */
2589 #define COMP3_CSR_COMP3LOCK_Pos (31U)
2590 #define COMP3_CSR_COMP3LOCK_Msk (0x1U << COMP3_CSR_COMP3LOCK_Pos) /*!< 0x80000000 */
2591 #define COMP3_CSR_COMP3LOCK COMP3_CSR_COMP3LOCK_Msk /*!< COMP3 lock */
2592
2593 /********************** Bit definition for COMP4_CSR register ***************/
2594 #define COMP4_CSR_COMP4EN_Pos (0U)
2595 #define COMP4_CSR_COMP4EN_Msk (0x1U << COMP4_CSR_COMP4EN_Pos) /*!< 0x00000001 */
2596 #define COMP4_CSR_COMP4EN COMP4_CSR_COMP4EN_Msk /*!< COMP4 enable */
2597 #define COMP4_CSR_COMP4INSEL_Pos (4U)
2598 #define COMP4_CSR_COMP4INSEL_Msk (0x7U << COMP4_CSR_COMP4INSEL_Pos) /*!< 0x00000070 */
2599 #define COMP4_CSR_COMP4INSEL COMP4_CSR_COMP4INSEL_Msk /*!< COMP4 inverting input select */
2600 #define COMP4_CSR_COMP4INSEL_0 (0x00000010U) /*!< COMP4 inverting input select bit 0 */
2601 #define COMP4_CSR_COMP4INSEL_1 (0x00000020U) /*!< COMP4 inverting input select bit 1 */
2602 #define COMP4_CSR_COMP4INSEL_2 (0x00000040U) /*!< COMP4 inverting input select bit 2 */
2603 #define COMP4_CSR_COMP4OUTSEL_Pos (10U)
2604 #define COMP4_CSR_COMP4OUTSEL_Msk (0xFU << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00003C00 */
2605 #define COMP4_CSR_COMP4OUTSEL COMP4_CSR_COMP4OUTSEL_Msk /*!< COMP4 output select */
2606 #define COMP4_CSR_COMP4OUTSEL_0 (0x1U << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00000400 */
2607 #define COMP4_CSR_COMP4OUTSEL_1 (0x2U << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00000800 */
2608 #define COMP4_CSR_COMP4OUTSEL_2 (0x4U << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00001000 */
2609 #define COMP4_CSR_COMP4OUTSEL_3 (0x8U << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00002000 */
2610 #define COMP4_CSR_COMP4POL_Pos (15U)
2611 #define COMP4_CSR_COMP4POL_Msk (0x1U << COMP4_CSR_COMP4POL_Pos) /*!< 0x00008000 */
2612 #define COMP4_CSR_COMP4POL COMP4_CSR_COMP4POL_Msk /*!< COMP4 output polarity */
2613 #define COMP4_CSR_COMP4BLANKING_Pos (18U)
2614 #define COMP4_CSR_COMP4BLANKING_Msk (0x3U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x000C0000 */
2615 #define COMP4_CSR_COMP4BLANKING COMP4_CSR_COMP4BLANKING_Msk /*!< COMP4 blanking */
2616 #define COMP4_CSR_COMP4BLANKING_0 (0x1U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00040000 */
2617 #define COMP4_CSR_COMP4BLANKING_1 (0x2U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00080000 */
2618 #define COMP4_CSR_COMP4BLANKING_2 (0x4U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00100000 */
2619 #define COMP4_CSR_COMP4OUT_Pos (30U)
2620 #define COMP4_CSR_COMP4OUT_Msk (0x1U << COMP4_CSR_COMP4OUT_Pos) /*!< 0x40000000 */
2621 #define COMP4_CSR_COMP4OUT COMP4_CSR_COMP4OUT_Msk /*!< COMP4 output level */
2622 #define COMP4_CSR_COMP4LOCK_Pos (31U)
2623 #define COMP4_CSR_COMP4LOCK_Msk (0x1U << COMP4_CSR_COMP4LOCK_Pos) /*!< 0x80000000 */
2624 #define COMP4_CSR_COMP4LOCK COMP4_CSR_COMP4LOCK_Msk /*!< COMP4 lock */
2625
2626 /********************** Bit definition for COMP5_CSR register ***************/
2627 #define COMP5_CSR_COMP5EN_Pos (0U)
2628 #define COMP5_CSR_COMP5EN_Msk (0x1U << COMP5_CSR_COMP5EN_Pos) /*!< 0x00000001 */
2629 #define COMP5_CSR_COMP5EN COMP5_CSR_COMP5EN_Msk /*!< COMP5 enable */
2630 #define COMP5_CSR_COMP5INSEL_Pos (4U)
2631 #define COMP5_CSR_COMP5INSEL_Msk (0x7U << COMP5_CSR_COMP5INSEL_Pos) /*!< 0x00000070 */
2632 #define COMP5_CSR_COMP5INSEL COMP5_CSR_COMP5INSEL_Msk /*!< COMP5 inverting input select */
2633 #define COMP5_CSR_COMP5INSEL_0 (0x1U << COMP5_CSR_COMP5INSEL_Pos) /*!< 0x00000010 */
2634 #define COMP5_CSR_COMP5INSEL_1 (0x2U << COMP5_CSR_COMP5INSEL_Pos) /*!< 0x00000020 */
2635 #define COMP5_CSR_COMP5INSEL_2 (0x4U << COMP5_CSR_COMP5INSEL_Pos) /*!< 0x00000040 */
2636 #define COMP5_CSR_COMP5OUTSEL_Pos (10U)
2637 #define COMP5_CSR_COMP5OUTSEL_Msk (0xFU << COMP5_CSR_COMP5OUTSEL_Pos) /*!< 0x00003C00 */
2638 #define COMP5_CSR_COMP5OUTSEL COMP5_CSR_COMP5OUTSEL_Msk /*!< COMP5 output select */
2639 #define COMP5_CSR_COMP5OUTSEL_0 (0x1U << COMP5_CSR_COMP5OUTSEL_Pos) /*!< 0x00000400 */
2640 #define COMP5_CSR_COMP5OUTSEL_1 (0x2U << COMP5_CSR_COMP5OUTSEL_Pos) /*!< 0x00000800 */
2641 #define COMP5_CSR_COMP5OUTSEL_2 (0x4U << COMP5_CSR_COMP5OUTSEL_Pos) /*!< 0x00001000 */
2642 #define COMP5_CSR_COMP5OUTSEL_3 (0x8U << COMP5_CSR_COMP5OUTSEL_Pos) /*!< 0x00002000 */
2643 #define COMP5_CSR_COMP5POL_Pos (15U)
2644 #define COMP5_CSR_COMP5POL_Msk (0x1U << COMP5_CSR_COMP5POL_Pos) /*!< 0x00008000 */
2645 #define COMP5_CSR_COMP5POL COMP5_CSR_COMP5POL_Msk /*!< COMP5 output polarity */
2646 #define COMP5_CSR_COMP5BLANKING_Pos (18U)
2647 #define COMP5_CSR_COMP5BLANKING_Msk (0x3U << COMP5_CSR_COMP5BLANKING_Pos) /*!< 0x000C0000 */
2648 #define COMP5_CSR_COMP5BLANKING COMP5_CSR_COMP5BLANKING_Msk /*!< COMP5 blanking */
2649 #define COMP5_CSR_COMP5BLANKING_0 (0x1U << COMP5_CSR_COMP5BLANKING_Pos) /*!< 0x00040000 */
2650 #define COMP5_CSR_COMP5BLANKING_1 (0x2U << COMP5_CSR_COMP5BLANKING_Pos) /*!< 0x00080000 */
2651 #define COMP5_CSR_COMP5BLANKING_2 (0x4U << COMP5_CSR_COMP5BLANKING_Pos) /*!< 0x00100000 */
2652 #define COMP5_CSR_COMP5OUT_Pos (30U)
2653 #define COMP5_CSR_COMP5OUT_Msk (0x1U << COMP5_CSR_COMP5OUT_Pos) /*!< 0x40000000 */
2654 #define COMP5_CSR_COMP5OUT COMP5_CSR_COMP5OUT_Msk /*!< COMP5 output level */
2655 #define COMP5_CSR_COMP5LOCK_Pos (31U)
2656 #define COMP5_CSR_COMP5LOCK_Msk (0x1U << COMP5_CSR_COMP5LOCK_Pos) /*!< 0x80000000 */
2657 #define COMP5_CSR_COMP5LOCK COMP5_CSR_COMP5LOCK_Msk /*!< COMP5 lock */
2658
2659 /********************** Bit definition for COMP6_CSR register ***************/
2660 #define COMP6_CSR_COMP6EN_Pos (0U)
2661 #define COMP6_CSR_COMP6EN_Msk (0x1U << COMP6_CSR_COMP6EN_Pos) /*!< 0x00000001 */
2662 #define COMP6_CSR_COMP6EN COMP6_CSR_COMP6EN_Msk /*!< COMP6 enable */
2663 #define COMP6_CSR_COMP6INSEL_Pos (4U)
2664 #define COMP6_CSR_COMP6INSEL_Msk (0x7U << COMP6_CSR_COMP6INSEL_Pos) /*!< 0x00000070 */
2665 #define COMP6_CSR_COMP6INSEL COMP6_CSR_COMP6INSEL_Msk /*!< COMP6 inverting input select */
2666 #define COMP6_CSR_COMP6INSEL_0 (0x00000010U) /*!< COMP6 inverting input select bit 0 */
2667 #define COMP6_CSR_COMP6INSEL_1 (0x00000020U) /*!< COMP6 inverting input select bit 1 */
2668 #define COMP6_CSR_COMP6INSEL_2 (0x00000040U) /*!< COMP6 inverting input select bit 2 */
2669 #define COMP6_CSR_COMP6OUTSEL_Pos (10U)
2670 #define COMP6_CSR_COMP6OUTSEL_Msk (0xFU << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00003C00 */
2671 #define COMP6_CSR_COMP6OUTSEL COMP6_CSR_COMP6OUTSEL_Msk /*!< COMP6 output select */
2672 #define COMP6_CSR_COMP6OUTSEL_0 (0x1U << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00000400 */
2673 #define COMP6_CSR_COMP6OUTSEL_1 (0x2U << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00000800 */
2674 #define COMP6_CSR_COMP6OUTSEL_2 (0x4U << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00001000 */
2675 #define COMP6_CSR_COMP6OUTSEL_3 (0x8U << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00002000 */
2676 #define COMP6_CSR_COMP6POL_Pos (15U)
2677 #define COMP6_CSR_COMP6POL_Msk (0x1U << COMP6_CSR_COMP6POL_Pos) /*!< 0x00008000 */
2678 #define COMP6_CSR_COMP6POL COMP6_CSR_COMP6POL_Msk /*!< COMP6 output polarity */
2679 #define COMP6_CSR_COMP6BLANKING_Pos (18U)
2680 #define COMP6_CSR_COMP6BLANKING_Msk (0x3U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x000C0000 */
2681 #define COMP6_CSR_COMP6BLANKING COMP6_CSR_COMP6BLANKING_Msk /*!< COMP6 blanking */
2682 #define COMP6_CSR_COMP6BLANKING_0 (0x1U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00040000 */
2683 #define COMP6_CSR_COMP6BLANKING_1 (0x2U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00080000 */
2684 #define COMP6_CSR_COMP6BLANKING_2 (0x4U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00100000 */
2685 #define COMP6_CSR_COMP6OUT_Pos (30U)
2686 #define COMP6_CSR_COMP6OUT_Msk (0x1U << COMP6_CSR_COMP6OUT_Pos) /*!< 0x40000000 */
2687 #define COMP6_CSR_COMP6OUT COMP6_CSR_COMP6OUT_Msk /*!< COMP6 output level */
2688 #define COMP6_CSR_COMP6LOCK_Pos (31U)
2689 #define COMP6_CSR_COMP6LOCK_Msk (0x1U << COMP6_CSR_COMP6LOCK_Pos) /*!< 0x80000000 */
2690 #define COMP6_CSR_COMP6LOCK COMP6_CSR_COMP6LOCK_Msk /*!< COMP6 lock */
2691
2692 /********************** Bit definition for COMP7_CSR register ***************/
2693 #define COMP7_CSR_COMP7EN_Pos (0U)
2694 #define COMP7_CSR_COMP7EN_Msk (0x1U << COMP7_CSR_COMP7EN_Pos) /*!< 0x00000001 */
2695 #define COMP7_CSR_COMP7EN COMP7_CSR_COMP7EN_Msk /*!< COMP7 enable */
2696 #define COMP7_CSR_COMP7INSEL_Pos (4U)
2697 #define COMP7_CSR_COMP7INSEL_Msk (0x7U << COMP7_CSR_COMP7INSEL_Pos) /*!< 0x00000070 */
2698 #define COMP7_CSR_COMP7INSEL COMP7_CSR_COMP7INSEL_Msk /*!< COMP7 inverting input select */
2699 #define COMP7_CSR_COMP7INSEL_0 (0x1U << COMP7_CSR_COMP7INSEL_Pos) /*!< 0x00000010 */
2700 #define COMP7_CSR_COMP7INSEL_1 (0x2U << COMP7_CSR_COMP7INSEL_Pos) /*!< 0x00000020 */
2701 #define COMP7_CSR_COMP7INSEL_2 (0x4U << COMP7_CSR_COMP7INSEL_Pos) /*!< 0x00000040 */
2702 #define COMP7_CSR_COMP7OUTSEL_Pos (10U)
2703 #define COMP7_CSR_COMP7OUTSEL_Msk (0xFU << COMP7_CSR_COMP7OUTSEL_Pos) /*!< 0x00003C00 */
2704 #define COMP7_CSR_COMP7OUTSEL COMP7_CSR_COMP7OUTSEL_Msk /*!< COMP7 output select */
2705 #define COMP7_CSR_COMP7OUTSEL_0 (0x1U << COMP7_CSR_COMP7OUTSEL_Pos) /*!< 0x00000400 */
2706 #define COMP7_CSR_COMP7OUTSEL_1 (0x2U << COMP7_CSR_COMP7OUTSEL_Pos) /*!< 0x00000800 */
2707 #define COMP7_CSR_COMP7OUTSEL_2 (0x4U << COMP7_CSR_COMP7OUTSEL_Pos) /*!< 0x00001000 */
2708 #define COMP7_CSR_COMP7OUTSEL_3 (0x8U << COMP7_CSR_COMP7OUTSEL_Pos) /*!< 0x00002000 */
2709 #define COMP7_CSR_COMP7POL_Pos (15U)
2710 #define COMP7_CSR_COMP7POL_Msk (0x1U << COMP7_CSR_COMP7POL_Pos) /*!< 0x00008000 */
2711 #define COMP7_CSR_COMP7POL COMP7_CSR_COMP7POL_Msk /*!< COMP7 output polarity */
2712 #define COMP7_CSR_COMP7BLANKING_Pos (18U)
2713 #define COMP7_CSR_COMP7BLANKING_Msk (0x3U << COMP7_CSR_COMP7BLANKING_Pos) /*!< 0x000C0000 */
2714 #define COMP7_CSR_COMP7BLANKING COMP7_CSR_COMP7BLANKING_Msk /*!< COMP7 blanking */
2715 #define COMP7_CSR_COMP7BLANKING_0 (0x1U << COMP7_CSR_COMP7BLANKING_Pos) /*!< 0x00040000 */
2716 #define COMP7_CSR_COMP7BLANKING_1 (0x2U << COMP7_CSR_COMP7BLANKING_Pos) /*!< 0x00080000 */
2717 #define COMP7_CSR_COMP7BLANKING_2 (0x4U << COMP7_CSR_COMP7BLANKING_Pos) /*!< 0x00100000 */
2718 #define COMP7_CSR_COMP7OUT_Pos (30U)
2719 #define COMP7_CSR_COMP7OUT_Msk (0x1U << COMP7_CSR_COMP7OUT_Pos) /*!< 0x40000000 */
2720 #define COMP7_CSR_COMP7OUT COMP7_CSR_COMP7OUT_Msk /*!< COMP7 output level */
2721 #define COMP7_CSR_COMP7LOCK_Pos (31U)
2722 #define COMP7_CSR_COMP7LOCK_Msk (0x1U << COMP7_CSR_COMP7LOCK_Pos) /*!< 0x80000000 */
2723 #define COMP7_CSR_COMP7LOCK COMP7_CSR_COMP7LOCK_Msk /*!< COMP7 lock */
2724
2725 /********************** Bit definition for COMP_CSR register ****************/
2726 #define COMP_CSR_COMPxEN_Pos (0U)
2727 #define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
2728 #define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
2729 #define COMP_CSR_COMPxSW1_Pos (1U)
2730 #define COMP_CSR_COMPxSW1_Msk (0x1U << COMP_CSR_COMPxSW1_Pos) /*!< 0x00000002 */
2731 #define COMP_CSR_COMPxSW1 COMP_CSR_COMPxSW1_Msk /*!< COMPx SW1 switch control */
2732 #define COMP_CSR_COMPxINSEL_Pos (4U)
2733 #define COMP_CSR_COMPxINSEL_Msk (0x7U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000070 */
2734 #define COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk /*!< COMPx inverting input select */
2735 #define COMP_CSR_COMPxINSEL_0 (0x00000010U) /*!< COMPx inverting input select bit 0 */
2736 #define COMP_CSR_COMPxINSEL_1 (0x00000020U) /*!< COMPx inverting input select bit 1 */
2737 #define COMP_CSR_COMPxINSEL_2 (0x00000040U) /*!< COMPx inverting input select bit 2 */
2738 #define COMP_CSR_COMPxOUTSEL_Pos (10U)
2739 #define COMP_CSR_COMPxOUTSEL_Msk (0xFU << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00003C00 */
2740 #define COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk /*!< COMPx output select */
2741 #define COMP_CSR_COMPxOUTSEL_0 (0x1U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000400 */
2742 #define COMP_CSR_COMPxOUTSEL_1 (0x2U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000800 */
2743 #define COMP_CSR_COMPxOUTSEL_2 (0x4U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00001000 */
2744 #define COMP_CSR_COMPxOUTSEL_3 (0x8U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00002000 */
2745 #define COMP_CSR_COMPxPOL_Pos (15U)
2746 #define COMP_CSR_COMPxPOL_Msk (0x1U << COMP_CSR_COMPxPOL_Pos) /*!< 0x00008000 */
2747 #define COMP_CSR_COMPxPOL COMP_CSR_COMPxPOL_Msk /*!< COMPx output polarity */
2748 #define COMP_CSR_COMPxBLANKING_Pos (18U)
2749 #define COMP_CSR_COMPxBLANKING_Msk (0x3U << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x000C0000 */
2750 #define COMP_CSR_COMPxBLANKING COMP_CSR_COMPxBLANKING_Msk /*!< COMPx blanking */
2751 #define COMP_CSR_COMPxBLANKING_0 (0x1U << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x00040000 */
2752 #define COMP_CSR_COMPxBLANKING_1 (0x2U << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x00080000 */
2753 #define COMP_CSR_COMPxBLANKING_2 (0x4U << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x00100000 */
2754 #define COMP_CSR_COMPxOUT_Pos (30U)
2755 #define COMP_CSR_COMPxOUT_Msk (0x1U << COMP_CSR_COMPxOUT_Pos) /*!< 0x40000000 */
2756 #define COMP_CSR_COMPxOUT COMP_CSR_COMPxOUT_Msk /*!< COMPx output level */
2757 #define COMP_CSR_COMPxLOCK_Pos (31U)
2758 #define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
2759 #define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
2760
2761 /******************************************************************************/
2762 /* */
2763 /* Operational Amplifier (OPAMP) */
2764 /* */
2765 /******************************************************************************/
2766 /********************* Bit definition for OPAMP1_CSR register ***************/
2767 #define OPAMP1_CSR_OPAMP1EN_Pos (0U)
2768 #define OPAMP1_CSR_OPAMP1EN_Msk (0x1U << OPAMP1_CSR_OPAMP1EN_Pos) /*!< 0x00000001 */
2769 #define OPAMP1_CSR_OPAMP1EN OPAMP1_CSR_OPAMP1EN_Msk /*!< OPAMP1 enable */
2770 #define OPAMP1_CSR_FORCEVP_Pos (1U)
2771 #define OPAMP1_CSR_FORCEVP_Msk (0x1U << OPAMP1_CSR_FORCEVP_Pos) /*!< 0x00000002 */
2772 #define OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
2773 #define OPAMP1_CSR_VPSEL_Pos (2U)
2774 #define OPAMP1_CSR_VPSEL_Msk (0x3U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
2775 #define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverting input selection */
2776 #define OPAMP1_CSR_VPSEL_0 (0x1U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
2777 #define OPAMP1_CSR_VPSEL_1 (0x2U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
2778 #define OPAMP1_CSR_VMSEL_Pos (5U)
2779 #define OPAMP1_CSR_VMSEL_Msk (0x3U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000060 */
2780 #define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
2781 #define OPAMP1_CSR_VMSEL_0 (0x1U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000020 */
2782 #define OPAMP1_CSR_VMSEL_1 (0x2U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000040 */
2783 #define OPAMP1_CSR_TCMEN_Pos (7U)
2784 #define OPAMP1_CSR_TCMEN_Msk (0x1U << OPAMP1_CSR_TCMEN_Pos) /*!< 0x00000080 */
2785 #define OPAMP1_CSR_TCMEN OPAMP1_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */
2786 #define OPAMP1_CSR_VMSSEL_Pos (8U)
2787 #define OPAMP1_CSR_VMSSEL_Msk (0x1U << OPAMP1_CSR_VMSSEL_Pos) /*!< 0x00000100 */
2788 #define OPAMP1_CSR_VMSSEL OPAMP1_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */
2789 #define OPAMP1_CSR_VPSSEL_Pos (9U)
2790 #define OPAMP1_CSR_VPSSEL_Msk (0x3U << OPAMP1_CSR_VPSSEL_Pos) /*!< 0x00000600 */
2791 #define OPAMP1_CSR_VPSSEL OPAMP1_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */
2792 #define OPAMP1_CSR_VPSSEL_0 (0x1U << OPAMP1_CSR_VPSSEL_Pos) /*!< 0x00000200 */
2793 #define OPAMP1_CSR_VPSSEL_1 (0x2U << OPAMP1_CSR_VPSSEL_Pos) /*!< 0x00000400 */
2794 #define OPAMP1_CSR_CALON_Pos (11U)
2795 #define OPAMP1_CSR_CALON_Msk (0x1U << OPAMP1_CSR_CALON_Pos) /*!< 0x00000800 */
2796 #define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
2797 #define OPAMP1_CSR_CALSEL_Pos (12U)
2798 #define OPAMP1_CSR_CALSEL_Msk (0x3U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00003000 */
2799 #define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
2800 #define OPAMP1_CSR_CALSEL_0 (0x1U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00001000 */
2801 #define OPAMP1_CSR_CALSEL_1 (0x2U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
2802 #define OPAMP1_CSR_PGGAIN_Pos (14U)
2803 #define OPAMP1_CSR_PGGAIN_Msk (0xFU << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
2804 #define OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
2805 #define OPAMP1_CSR_PGGAIN_0 (0x1U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00004000 */
2806 #define OPAMP1_CSR_PGGAIN_1 (0x2U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00008000 */
2807 #define OPAMP1_CSR_PGGAIN_2 (0x4U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00010000 */
2808 #define OPAMP1_CSR_PGGAIN_3 (0x8U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00020000 */
2809 #define OPAMP1_CSR_USERTRIM_Pos (18U)
2810 #define OPAMP1_CSR_USERTRIM_Msk (0x1U << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00040000 */
2811 #define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
2812 #define OPAMP1_CSR_TRIMOFFSETP_Pos (19U)
2813 #define OPAMP1_CSR_TRIMOFFSETP_Msk (0x1FU << OPAMP1_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
2814 #define OPAMP1_CSR_TRIMOFFSETP OPAMP1_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
2815 #define OPAMP1_CSR_TRIMOFFSETN_Pos (24U)
2816 #define OPAMP1_CSR_TRIMOFFSETN_Msk (0x1FU << OPAMP1_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
2817 #define OPAMP1_CSR_TRIMOFFSETN OPAMP1_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
2818 #define OPAMP1_CSR_TSTREF_Pos (29U)
2819 #define OPAMP1_CSR_TSTREF_Msk (0x1U << OPAMP1_CSR_TSTREF_Pos) /*!< 0x20000000 */
2820 #define OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */
2821 #define OPAMP1_CSR_OUTCAL_Pos (30U)
2822 #define OPAMP1_CSR_OUTCAL_Msk (0x1U << OPAMP1_CSR_OUTCAL_Pos) /*!< 0x40000000 */
2823 #define OPAMP1_CSR_OUTCAL OPAMP1_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
2824 #define OPAMP1_CSR_LOCK_Pos (31U)
2825 #define OPAMP1_CSR_LOCK_Msk (0x1U << OPAMP1_CSR_LOCK_Pos) /*!< 0x80000000 */
2826 #define OPAMP1_CSR_LOCK OPAMP1_CSR_LOCK_Msk /*!< OPAMP lock */
2827
2828 /********************* Bit definition for OPAMP2_CSR register ***************/
2829 #define OPAMP2_CSR_OPAMP2EN_Pos (0U)
2830 #define OPAMP2_CSR_OPAMP2EN_Msk (0x1U << OPAMP2_CSR_OPAMP2EN_Pos) /*!< 0x00000001 */
2831 #define OPAMP2_CSR_OPAMP2EN OPAMP2_CSR_OPAMP2EN_Msk /*!< OPAMP2 enable */
2832 #define OPAMP2_CSR_FORCEVP_Pos (1U)
2833 #define OPAMP2_CSR_FORCEVP_Msk (0x1U << OPAMP2_CSR_FORCEVP_Pos) /*!< 0x00000002 */
2834 #define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
2835 #define OPAMP2_CSR_VPSEL_Pos (2U)
2836 #define OPAMP2_CSR_VPSEL_Msk (0x3U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x0000000C */
2837 #define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverting input selection */
2838 #define OPAMP2_CSR_VPSEL_0 (0x1U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000004 */
2839 #define OPAMP2_CSR_VPSEL_1 (0x2U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000008 */
2840 #define OPAMP2_CSR_VMSEL_Pos (5U)
2841 #define OPAMP2_CSR_VMSEL_Msk (0x3U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000060 */
2842 #define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */
2843 #define OPAMP2_CSR_VMSEL_0 (0x1U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000020 */
2844 #define OPAMP2_CSR_VMSEL_1 (0x2U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000040 */
2845 #define OPAMP2_CSR_TCMEN_Pos (7U)
2846 #define OPAMP2_CSR_TCMEN_Msk (0x1U << OPAMP2_CSR_TCMEN_Pos) /*!< 0x00000080 */
2847 #define OPAMP2_CSR_TCMEN OPAMP2_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */
2848 #define OPAMP2_CSR_VMSSEL_Pos (8U)
2849 #define OPAMP2_CSR_VMSSEL_Msk (0x1U << OPAMP2_CSR_VMSSEL_Pos) /*!< 0x00000100 */
2850 #define OPAMP2_CSR_VMSSEL OPAMP2_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */
2851 #define OPAMP2_CSR_VPSSEL_Pos (9U)
2852 #define OPAMP2_CSR_VPSSEL_Msk (0x3U << OPAMP2_CSR_VPSSEL_Pos) /*!< 0x00000600 */
2853 #define OPAMP2_CSR_VPSSEL OPAMP2_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */
2854 #define OPAMP2_CSR_VPSSEL_0 (0x1U << OPAMP2_CSR_VPSSEL_Pos) /*!< 0x00000200 */
2855 #define OPAMP2_CSR_VPSSEL_1 (0x2U << OPAMP2_CSR_VPSSEL_Pos) /*!< 0x00000400 */
2856 #define OPAMP2_CSR_CALON_Pos (11U)
2857 #define OPAMP2_CSR_CALON_Msk (0x1U << OPAMP2_CSR_CALON_Pos) /*!< 0x00000800 */
2858 #define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */
2859 #define OPAMP2_CSR_CALSEL_Pos (12U)
2860 #define OPAMP2_CSR_CALSEL_Msk (0x3U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00003000 */
2861 #define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */
2862 #define OPAMP2_CSR_CALSEL_0 (0x1U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00001000 */
2863 #define OPAMP2_CSR_CALSEL_1 (0x2U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */
2864 #define OPAMP2_CSR_PGGAIN_Pos (14U)
2865 #define OPAMP2_CSR_PGGAIN_Msk (0xFU << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
2866 #define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
2867 #define OPAMP2_CSR_PGGAIN_0 (0x1U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00004000 */
2868 #define OPAMP2_CSR_PGGAIN_1 (0x2U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00008000 */
2869 #define OPAMP2_CSR_PGGAIN_2 (0x4U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00010000 */
2870 #define OPAMP2_CSR_PGGAIN_3 (0x8U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00020000 */
2871 #define OPAMP2_CSR_USERTRIM_Pos (18U)
2872 #define OPAMP2_CSR_USERTRIM_Msk (0x1U << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00040000 */
2873 #define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */
2874 #define OPAMP2_CSR_TRIMOFFSETP_Pos (19U)
2875 #define OPAMP2_CSR_TRIMOFFSETP_Msk (0x1FU << OPAMP2_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
2876 #define OPAMP2_CSR_TRIMOFFSETP OPAMP2_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
2877 #define OPAMP2_CSR_TRIMOFFSETN_Pos (24U)
2878 #define OPAMP2_CSR_TRIMOFFSETN_Msk (0x1FU << OPAMP2_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
2879 #define OPAMP2_CSR_TRIMOFFSETN OPAMP2_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
2880 #define OPAMP2_CSR_TSTREF_Pos (29U)
2881 #define OPAMP2_CSR_TSTREF_Msk (0x1U << OPAMP2_CSR_TSTREF_Pos) /*!< 0x20000000 */
2882 #define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */
2883 #define OPAMP2_CSR_OUTCAL_Pos (30U)
2884 #define OPAMP2_CSR_OUTCAL_Msk (0x1U << OPAMP2_CSR_OUTCAL_Pos) /*!< 0x40000000 */
2885 #define OPAMP2_CSR_OUTCAL OPAMP2_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
2886 #define OPAMP2_CSR_LOCK_Pos (31U)
2887 #define OPAMP2_CSR_LOCK_Msk (0x1U << OPAMP2_CSR_LOCK_Pos) /*!< 0x80000000 */
2888 #define OPAMP2_CSR_LOCK OPAMP2_CSR_LOCK_Msk /*!< OPAMP lock */
2889
2890 /********************* Bit definition for OPAMP3_CSR register ***************/
2891 #define OPAMP3_CSR_OPAMP3EN_Pos (0U)
2892 #define OPAMP3_CSR_OPAMP3EN_Msk (0x1U << OPAMP3_CSR_OPAMP3EN_Pos) /*!< 0x00000001 */
2893 #define OPAMP3_CSR_OPAMP3EN OPAMP3_CSR_OPAMP3EN_Msk /*!< OPAMP3 enable */
2894 #define OPAMP3_CSR_FORCEVP_Pos (1U)
2895 #define OPAMP3_CSR_FORCEVP_Msk (0x1U << OPAMP3_CSR_FORCEVP_Pos) /*!< 0x00000002 */
2896 #define OPAMP3_CSR_FORCEVP OPAMP3_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
2897 #define OPAMP3_CSR_VPSEL_Pos (2U)
2898 #define OPAMP3_CSR_VPSEL_Msk (0x3U << OPAMP3_CSR_VPSEL_Pos) /*!< 0x0000000C */
2899 #define OPAMP3_CSR_VPSEL OPAMP3_CSR_VPSEL_Msk /*!< Non inverting input selection */
2900 #define OPAMP3_CSR_VPSEL_0 (0x1U << OPAMP3_CSR_VPSEL_Pos) /*!< 0x00000004 */
2901 #define OPAMP3_CSR_VPSEL_1 (0x2U << OPAMP3_CSR_VPSEL_Pos) /*!< 0x00000008 */
2902 #define OPAMP3_CSR_VMSEL_Pos (5U)
2903 #define OPAMP3_CSR_VMSEL_Msk (0x3U << OPAMP3_CSR_VMSEL_Pos) /*!< 0x00000060 */
2904 #define OPAMP3_CSR_VMSEL OPAMP3_CSR_VMSEL_Msk /*!< Inverting input selection */
2905 #define OPAMP3_CSR_VMSEL_0 (0x1U << OPAMP3_CSR_VMSEL_Pos) /*!< 0x00000020 */
2906 #define OPAMP3_CSR_VMSEL_1 (0x2U << OPAMP3_CSR_VMSEL_Pos) /*!< 0x00000040 */
2907 #define OPAMP3_CSR_TCMEN_Pos (7U)
2908 #define OPAMP3_CSR_TCMEN_Msk (0x1U << OPAMP3_CSR_TCMEN_Pos) /*!< 0x00000080 */
2909 #define OPAMP3_CSR_TCMEN OPAMP3_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */
2910 #define OPAMP3_CSR_VMSSEL_Pos (8U)
2911 #define OPAMP3_CSR_VMSSEL_Msk (0x1U << OPAMP3_CSR_VMSSEL_Pos) /*!< 0x00000100 */
2912 #define OPAMP3_CSR_VMSSEL OPAMP3_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */
2913 #define OPAMP3_CSR_VPSSEL_Pos (9U)
2914 #define OPAMP3_CSR_VPSSEL_Msk (0x3U << OPAMP3_CSR_VPSSEL_Pos) /*!< 0x00000600 */
2915 #define OPAMP3_CSR_VPSSEL OPAMP3_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */
2916 #define OPAMP3_CSR_VPSSEL_0 (0x1U << OPAMP3_CSR_VPSSEL_Pos) /*!< 0x00000200 */
2917 #define OPAMP3_CSR_VPSSEL_1 (0x2U << OPAMP3_CSR_VPSSEL_Pos) /*!< 0x00000400 */
2918 #define OPAMP3_CSR_CALON_Pos (11U)
2919 #define OPAMP3_CSR_CALON_Msk (0x1U << OPAMP3_CSR_CALON_Pos) /*!< 0x00000800 */
2920 #define OPAMP3_CSR_CALON OPAMP3_CSR_CALON_Msk /*!< Calibration mode enable */
2921 #define OPAMP3_CSR_CALSEL_Pos (12U)
2922 #define OPAMP3_CSR_CALSEL_Msk (0x3U << OPAMP3_CSR_CALSEL_Pos) /*!< 0x00003000 */
2923 #define OPAMP3_CSR_CALSEL OPAMP3_CSR_CALSEL_Msk /*!< Calibration selection */
2924 #define OPAMP3_CSR_CALSEL_0 (0x1U << OPAMP3_CSR_CALSEL_Pos) /*!< 0x00001000 */
2925 #define OPAMP3_CSR_CALSEL_1 (0x2U << OPAMP3_CSR_CALSEL_Pos) /*!< 0x00002000 */
2926 #define OPAMP3_CSR_PGGAIN_Pos (14U)
2927 #define OPAMP3_CSR_PGGAIN_Msk (0xFU << OPAMP3_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
2928 #define OPAMP3_CSR_PGGAIN OPAMP3_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
2929 #define OPAMP3_CSR_PGGAIN_0 (0x1U << OPAMP3_CSR_PGGAIN_Pos) /*!< 0x00004000 */
2930 #define OPAMP3_CSR_PGGAIN_1 (0x2U << OPAMP3_CSR_PGGAIN_Pos) /*!< 0x00008000 */
2931 #define OPAMP3_CSR_PGGAIN_2 (0x4U << OPAMP3_CSR_PGGAIN_Pos) /*!< 0x00010000 */
2932 #define OPAMP3_CSR_PGGAIN_3 (0x8U << OPAMP3_CSR_PGGAIN_Pos) /*!< 0x00020000 */
2933 #define OPAMP3_CSR_USERTRIM_Pos (18U)
2934 #define OPAMP3_CSR_USERTRIM_Msk (0x1U << OPAMP3_CSR_USERTRIM_Pos) /*!< 0x00040000 */
2935 #define OPAMP3_CSR_USERTRIM OPAMP3_CSR_USERTRIM_Msk /*!< User trimming enable */
2936 #define OPAMP3_CSR_TRIMOFFSETP_Pos (19U)
2937 #define OPAMP3_CSR_TRIMOFFSETP_Msk (0x1FU << OPAMP3_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
2938 #define OPAMP3_CSR_TRIMOFFSETP OPAMP3_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
2939 #define OPAMP3_CSR_TRIMOFFSETN_Pos (24U)
2940 #define OPAMP3_CSR_TRIMOFFSETN_Msk (0x1FU << OPAMP3_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
2941 #define OPAMP3_CSR_TRIMOFFSETN OPAMP3_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
2942 #define OPAMP3_CSR_TSTREF_Pos (29U)
2943 #define OPAMP3_CSR_TSTREF_Msk (0x1U << OPAMP3_CSR_TSTREF_Pos) /*!< 0x20000000 */
2944 #define OPAMP3_CSR_TSTREF OPAMP3_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */
2945 #define OPAMP3_CSR_OUTCAL_Pos (30U)
2946 #define OPAMP3_CSR_OUTCAL_Msk (0x1U << OPAMP3_CSR_OUTCAL_Pos) /*!< 0x40000000 */
2947 #define OPAMP3_CSR_OUTCAL OPAMP3_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
2948 #define OPAMP3_CSR_LOCK_Pos (31U)
2949 #define OPAMP3_CSR_LOCK_Msk (0x1U << OPAMP3_CSR_LOCK_Pos) /*!< 0x80000000 */
2950 #define OPAMP3_CSR_LOCK OPAMP3_CSR_LOCK_Msk /*!< OPAMP lock */
2951
2952 /********************* Bit definition for OPAMP4_CSR register ***************/
2953 #define OPAMP4_CSR_OPAMP4EN_Pos (0U)
2954 #define OPAMP4_CSR_OPAMP4EN_Msk (0x1U << OPAMP4_CSR_OPAMP4EN_Pos) /*!< 0x00000001 */
2955 #define OPAMP4_CSR_OPAMP4EN OPAMP4_CSR_OPAMP4EN_Msk /*!< OPAMP4 enable */
2956 #define OPAMP4_CSR_FORCEVP_Pos (1U)
2957 #define OPAMP4_CSR_FORCEVP_Msk (0x1U << OPAMP4_CSR_FORCEVP_Pos) /*!< 0x00000002 */
2958 #define OPAMP4_CSR_FORCEVP OPAMP4_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
2959 #define OPAMP4_CSR_VPSEL_Pos (2U)
2960 #define OPAMP4_CSR_VPSEL_Msk (0x3U << OPAMP4_CSR_VPSEL_Pos) /*!< 0x0000000C */
2961 #define OPAMP4_CSR_VPSEL OPAMP4_CSR_VPSEL_Msk /*!< Non inverting input selection */
2962 #define OPAMP4_CSR_VPSEL_0 (0x1U << OPAMP4_CSR_VPSEL_Pos) /*!< 0x00000004 */
2963 #define OPAMP4_CSR_VPSEL_1 (0x2U << OPAMP4_CSR_VPSEL_Pos) /*!< 0x00000008 */
2964 #define OPAMP4_CSR_VMSEL_Pos (5U)
2965 #define OPAMP4_CSR_VMSEL_Msk (0x3U << OPAMP4_CSR_VMSEL_Pos) /*!< 0x00000060 */
2966 #define OPAMP4_CSR_VMSEL OPAMP4_CSR_VMSEL_Msk /*!< Inverting input selection */
2967 #define OPAMP4_CSR_VMSEL_0 (0x1U << OPAMP4_CSR_VMSEL_Pos) /*!< 0x00000020 */
2968 #define OPAMP4_CSR_VMSEL_1 (0x2U << OPAMP4_CSR_VMSEL_Pos) /*!< 0x00000040 */
2969 #define OPAMP4_CSR_TCMEN_Pos (7U)
2970 #define OPAMP4_CSR_TCMEN_Msk (0x1U << OPAMP4_CSR_TCMEN_Pos) /*!< 0x00000080 */
2971 #define OPAMP4_CSR_TCMEN OPAMP4_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */
2972 #define OPAMP4_CSR_VMSSEL_Pos (8U)
2973 #define OPAMP4_CSR_VMSSEL_Msk (0x1U << OPAMP4_CSR_VMSSEL_Pos) /*!< 0x00000100 */
2974 #define OPAMP4_CSR_VMSSEL OPAMP4_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */
2975 #define OPAMP4_CSR_VPSSEL_Pos (9U)
2976 #define OPAMP4_CSR_VPSSEL_Msk (0x3U << OPAMP4_CSR_VPSSEL_Pos) /*!< 0x00000600 */
2977 #define OPAMP4_CSR_VPSSEL OPAMP4_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */
2978 #define OPAMP4_CSR_VPSSEL_0 (0x1U << OPAMP4_CSR_VPSSEL_Pos) /*!< 0x00000200 */
2979 #define OPAMP4_CSR_VPSSEL_1 (0x2U << OPAMP4_CSR_VPSSEL_Pos) /*!< 0x00000400 */
2980 #define OPAMP4_CSR_CALON_Pos (11U)
2981 #define OPAMP4_CSR_CALON_Msk (0x1U << OPAMP4_CSR_CALON_Pos) /*!< 0x00000800 */
2982 #define OPAMP4_CSR_CALON OPAMP4_CSR_CALON_Msk /*!< Calibration mode enable */
2983 #define OPAMP4_CSR_CALSEL_Pos (12U)
2984 #define OPAMP4_CSR_CALSEL_Msk (0x3U << OPAMP4_CSR_CALSEL_Pos) /*!< 0x00003000 */
2985 #define OPAMP4_CSR_CALSEL OPAMP4_CSR_CALSEL_Msk /*!< Calibration selection */
2986 #define OPAMP4_CSR_CALSEL_0 (0x1U << OPAMP4_CSR_CALSEL_Pos) /*!< 0x00001000 */
2987 #define OPAMP4_CSR_CALSEL_1 (0x2U << OPAMP4_CSR_CALSEL_Pos) /*!< 0x00002000 */
2988 #define OPAMP4_CSR_PGGAIN_Pos (14U)
2989 #define OPAMP4_CSR_PGGAIN_Msk (0xFU << OPAMP4_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
2990 #define OPAMP4_CSR_PGGAIN OPAMP4_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
2991 #define OPAMP4_CSR_PGGAIN_0 (0x1U << OPAMP4_CSR_PGGAIN_Pos) /*!< 0x00004000 */
2992 #define OPAMP4_CSR_PGGAIN_1 (0x2U << OPAMP4_CSR_PGGAIN_Pos) /*!< 0x00008000 */
2993 #define OPAMP4_CSR_PGGAIN_2 (0x4U << OPAMP4_CSR_PGGAIN_Pos) /*!< 0x00010000 */
2994 #define OPAMP4_CSR_PGGAIN_3 (0x8U << OPAMP4_CSR_PGGAIN_Pos) /*!< 0x00020000 */
2995 #define OPAMP4_CSR_USERTRIM_Pos (18U)
2996 #define OPAMP4_CSR_USERTRIM_Msk (0x1U << OPAMP4_CSR_USERTRIM_Pos) /*!< 0x00040000 */
2997 #define OPAMP4_CSR_USERTRIM OPAMP4_CSR_USERTRIM_Msk /*!< User trimming enable */
2998 #define OPAMP4_CSR_TRIMOFFSETP_Pos (19U)
2999 #define OPAMP4_CSR_TRIMOFFSETP_Msk (0x1FU << OPAMP4_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
3000 #define OPAMP4_CSR_TRIMOFFSETP OPAMP4_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
3001 #define OPAMP4_CSR_TRIMOFFSETN_Pos (24U)
3002 #define OPAMP4_CSR_TRIMOFFSETN_Msk (0x1FU << OPAMP4_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
3003 #define OPAMP4_CSR_TRIMOFFSETN OPAMP4_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
3004 #define OPAMP4_CSR_TSTREF_Pos (29U)
3005 #define OPAMP4_CSR_TSTREF_Msk (0x1U << OPAMP4_CSR_TSTREF_Pos) /*!< 0x20000000 */
3006 #define OPAMP4_CSR_TSTREF OPAMP4_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */
3007 #define OPAMP4_CSR_OUTCAL_Pos (30U)
3008 #define OPAMP4_CSR_OUTCAL_Msk (0x1U << OPAMP4_CSR_OUTCAL_Pos) /*!< 0x40000000 */
3009 #define OPAMP4_CSR_OUTCAL OPAMP4_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
3010 #define OPAMP4_CSR_LOCK_Pos (31U)
3011 #define OPAMP4_CSR_LOCK_Msk (0x1U << OPAMP4_CSR_LOCK_Pos) /*!< 0x80000000 */
3012 #define OPAMP4_CSR_LOCK OPAMP4_CSR_LOCK_Msk /*!< OPAMP lock */
3013
3014 /********************* Bit definition for OPAMPx_CSR register ***************/
3015 #define OPAMP_CSR_OPAMPxEN_Pos (0U)
3016 #define OPAMP_CSR_OPAMPxEN_Msk (0x1U << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
3017 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
3018 #define OPAMP_CSR_FORCEVP_Pos (1U)
3019 #define OPAMP_CSR_FORCEVP_Msk (0x1U << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
3020 #define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
3021 #define OPAMP_CSR_VPSEL_Pos (2U)
3022 #define OPAMP_CSR_VPSEL_Msk (0x3U << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
3023 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverting input selection */
3024 #define OPAMP_CSR_VPSEL_0 (0x1U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
3025 #define OPAMP_CSR_VPSEL_1 (0x2U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
3026 #define OPAMP_CSR_VMSEL_Pos (5U)
3027 #define OPAMP_CSR_VMSEL_Msk (0x3U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
3028 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
3029 #define OPAMP_CSR_VMSEL_0 (0x1U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
3030 #define OPAMP_CSR_VMSEL_1 (0x2U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
3031 #define OPAMP_CSR_TCMEN_Pos (7U)
3032 #define OPAMP_CSR_TCMEN_Msk (0x1U << OPAMP_CSR_TCMEN_Pos) /*!< 0x00000080 */
3033 #define OPAMP_CSR_TCMEN OPAMP_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */
3034 #define OPAMP_CSR_VMSSEL_Pos (8U)
3035 #define OPAMP_CSR_VMSSEL_Msk (0x1U << OPAMP_CSR_VMSSEL_Pos) /*!< 0x00000100 */
3036 #define OPAMP_CSR_VMSSEL OPAMP_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */
3037 #define OPAMP_CSR_VPSSEL_Pos (9U)
3038 #define OPAMP_CSR_VPSSEL_Msk (0x3U << OPAMP_CSR_VPSSEL_Pos) /*!< 0x00000600 */
3039 #define OPAMP_CSR_VPSSEL OPAMP_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */
3040 #define OPAMP_CSR_VPSSEL_0 (0x1U << OPAMP_CSR_VPSSEL_Pos) /*!< 0x00000200 */
3041 #define OPAMP_CSR_VPSSEL_1 (0x2U << OPAMP_CSR_VPSSEL_Pos) /*!< 0x00000400 */
3042 #define OPAMP_CSR_CALON_Pos (11U)
3043 #define OPAMP_CSR_CALON_Msk (0x1U << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
3044 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
3045 #define OPAMP_CSR_CALSEL_Pos (12U)
3046 #define OPAMP_CSR_CALSEL_Msk (0x3U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
3047 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
3048 #define OPAMP_CSR_CALSEL_0 (0x1U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
3049 #define OPAMP_CSR_CALSEL_1 (0x2U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
3050 #define OPAMP_CSR_PGGAIN_Pos (14U)
3051 #define OPAMP_CSR_PGGAIN_Msk (0xFU << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
3052 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
3053 #define OPAMP_CSR_PGGAIN_0 (0x1U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
3054 #define OPAMP_CSR_PGGAIN_1 (0x2U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
3055 #define OPAMP_CSR_PGGAIN_2 (0x4U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
3056 #define OPAMP_CSR_PGGAIN_3 (0x8U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
3057 #define OPAMP_CSR_USERTRIM_Pos (18U)
3058 #define OPAMP_CSR_USERTRIM_Msk (0x1U << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00040000 */
3059 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
3060 #define OPAMP_CSR_TRIMOFFSETP_Pos (19U)
3061 #define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FU << OPAMP_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
3062 #define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
3063 #define OPAMP_CSR_TRIMOFFSETN_Pos (24U)
3064 #define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FU << OPAMP_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
3065 #define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
3066 #define OPAMP_CSR_TSTREF_Pos (29U)
3067 #define OPAMP_CSR_TSTREF_Msk (0x1U << OPAMP_CSR_TSTREF_Pos) /*!< 0x20000000 */
3068 #define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */
3069 #define OPAMP_CSR_OUTCAL_Pos (30U)
3070 #define OPAMP_CSR_OUTCAL_Msk (0x1U << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */
3071 #define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
3072 #define OPAMP_CSR_LOCK_Pos (31U)
3073 #define OPAMP_CSR_LOCK_Msk (0x1U << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */
3074 #define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP lock */
3075
3076 /******************************************************************************/
3077 /* */
3078 /* Controller Area Network (CAN ) */
3079 /* */
3080 /******************************************************************************/
3081 /******************* Bit definition for CAN_MCR register ********************/
3082 #define CAN_MCR_INRQ_Pos (0U)
3083 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
3084 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
3085 #define CAN_MCR_SLEEP_Pos (1U)
3086 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
3087 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
3088 #define CAN_MCR_TXFP_Pos (2U)
3089 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
3090 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
3091 #define CAN_MCR_RFLM_Pos (3U)
3092 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
3093 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
3094 #define CAN_MCR_NART_Pos (4U)
3095 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
3096 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
3097 #define CAN_MCR_AWUM_Pos (5U)
3098 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
3099 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
3100 #define CAN_MCR_ABOM_Pos (6U)
3101 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
3102 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
3103 #define CAN_MCR_TTCM_Pos (7U)
3104 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
3105 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
3106 #define CAN_MCR_RESET_Pos (15U)
3107 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
3108 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
3109
3110 /******************* Bit definition for CAN_MSR register ********************/
3111 #define CAN_MSR_INAK_Pos (0U)
3112 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
3113 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
3114 #define CAN_MSR_SLAK_Pos (1U)
3115 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
3116 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
3117 #define CAN_MSR_ERRI_Pos (2U)
3118 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
3119 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
3120 #define CAN_MSR_WKUI_Pos (3U)
3121 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
3122 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
3123 #define CAN_MSR_SLAKI_Pos (4U)
3124 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
3125 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
3126 #define CAN_MSR_TXM_Pos (8U)
3127 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
3128 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
3129 #define CAN_MSR_RXM_Pos (9U)
3130 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
3131 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
3132 #define CAN_MSR_SAMP_Pos (10U)
3133 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
3134 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
3135 #define CAN_MSR_RX_Pos (11U)
3136 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
3137 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
3138
3139 /******************* Bit definition for CAN_TSR register ********************/
3140 #define CAN_TSR_RQCP0_Pos (0U)
3141 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
3142 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
3143 #define CAN_TSR_TXOK0_Pos (1U)
3144 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
3145 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
3146 #define CAN_TSR_ALST0_Pos (2U)
3147 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
3148 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
3149 #define CAN_TSR_TERR0_Pos (3U)
3150 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
3151 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
3152 #define CAN_TSR_ABRQ0_Pos (7U)
3153 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
3154 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
3155 #define CAN_TSR_RQCP1_Pos (8U)
3156 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
3157 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
3158 #define CAN_TSR_TXOK1_Pos (9U)
3159 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
3160 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
3161 #define CAN_TSR_ALST1_Pos (10U)
3162 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
3163 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
3164 #define CAN_TSR_TERR1_Pos (11U)
3165 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
3166 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
3167 #define CAN_TSR_ABRQ1_Pos (15U)
3168 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
3169 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
3170 #define CAN_TSR_RQCP2_Pos (16U)
3171 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
3172 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
3173 #define CAN_TSR_TXOK2_Pos (17U)
3174 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
3175 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
3176 #define CAN_TSR_ALST2_Pos (18U)
3177 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
3178 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
3179 #define CAN_TSR_TERR2_Pos (19U)
3180 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
3181 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
3182 #define CAN_TSR_ABRQ2_Pos (23U)
3183 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
3184 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
3185 #define CAN_TSR_CODE_Pos (24U)
3186 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
3187 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
3188
3189 #define CAN_TSR_TME_Pos (26U)
3190 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
3191 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
3192 #define CAN_TSR_TME0_Pos (26U)
3193 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
3194 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
3195 #define CAN_TSR_TME1_Pos (27U)
3196 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
3197 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
3198 #define CAN_TSR_TME2_Pos (28U)
3199 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
3200 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
3201
3202 #define CAN_TSR_LOW_Pos (29U)
3203 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
3204 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
3205 #define CAN_TSR_LOW0_Pos (29U)
3206 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
3207 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
3208 #define CAN_TSR_LOW1_Pos (30U)
3209 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
3210 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
3211 #define CAN_TSR_LOW2_Pos (31U)
3212 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
3213 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
3214
3215 /******************* Bit definition for CAN_RF0R register *******************/
3216 #define CAN_RF0R_FMP0_Pos (0U)
3217 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
3218 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
3219 #define CAN_RF0R_FULL0_Pos (3U)
3220 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
3221 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
3222 #define CAN_RF0R_FOVR0_Pos (4U)
3223 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
3224 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
3225 #define CAN_RF0R_RFOM0_Pos (5U)
3226 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
3227 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
3228
3229 /******************* Bit definition for CAN_RF1R register *******************/
3230 #define CAN_RF1R_FMP1_Pos (0U)
3231 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
3232 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
3233 #define CAN_RF1R_FULL1_Pos (3U)
3234 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
3235 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
3236 #define CAN_RF1R_FOVR1_Pos (4U)
3237 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
3238 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
3239 #define CAN_RF1R_RFOM1_Pos (5U)
3240 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
3241 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
3242
3243 /******************** Bit definition for CAN_IER register *******************/
3244 #define CAN_IER_TMEIE_Pos (0U)
3245 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
3246 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
3247 #define CAN_IER_FMPIE0_Pos (1U)
3248 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
3249 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
3250 #define CAN_IER_FFIE0_Pos (2U)
3251 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
3252 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
3253 #define CAN_IER_FOVIE0_Pos (3U)
3254 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
3255 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
3256 #define CAN_IER_FMPIE1_Pos (4U)
3257 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
3258 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
3259 #define CAN_IER_FFIE1_Pos (5U)
3260 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
3261 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
3262 #define CAN_IER_FOVIE1_Pos (6U)
3263 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
3264 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
3265 #define CAN_IER_EWGIE_Pos (8U)
3266 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
3267 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
3268 #define CAN_IER_EPVIE_Pos (9U)
3269 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
3270 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
3271 #define CAN_IER_BOFIE_Pos (10U)
3272 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
3273 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
3274 #define CAN_IER_LECIE_Pos (11U)
3275 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
3276 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
3277 #define CAN_IER_ERRIE_Pos (15U)
3278 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
3279 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
3280 #define CAN_IER_WKUIE_Pos (16U)
3281 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
3282 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
3283 #define CAN_IER_SLKIE_Pos (17U)
3284 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
3285 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
3286
3287 /******************** Bit definition for CAN_ESR register *******************/
3288 #define CAN_ESR_EWGF_Pos (0U)
3289 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
3290 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
3291 #define CAN_ESR_EPVF_Pos (1U)
3292 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
3293 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
3294 #define CAN_ESR_BOFF_Pos (2U)
3295 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
3296 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
3297
3298 #define CAN_ESR_LEC_Pos (4U)
3299 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
3300 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
3301 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
3302 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
3303 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
3304
3305 #define CAN_ESR_TEC_Pos (16U)
3306 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
3307 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
3308 #define CAN_ESR_REC_Pos (24U)
3309 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
3310 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
3311
3312 /******************* Bit definition for CAN_BTR register ********************/
3313 #define CAN_BTR_BRP_Pos (0U)
3314 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
3315 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
3316 #define CAN_BTR_TS1_Pos (16U)
3317 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
3318 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
3319 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
3320 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
3321 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
3322 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
3323 #define CAN_BTR_TS2_Pos (20U)
3324 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
3325 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
3326 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
3327 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
3328 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
3329 #define CAN_BTR_SJW_Pos (24U)
3330 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
3331 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
3332 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
3333 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
3334 #define CAN_BTR_LBKM_Pos (30U)
3335 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
3336 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
3337 #define CAN_BTR_SILM_Pos (31U)
3338 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
3339 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
3340
3341 /*!<Mailbox registers */
3342 /****************** Bit definition for CAN_TI0R register ********************/
3343 #define CAN_TI0R_TXRQ_Pos (0U)
3344 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
3345 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
3346 #define CAN_TI0R_RTR_Pos (1U)
3347 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
3348 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
3349 #define CAN_TI0R_IDE_Pos (2U)
3350 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
3351 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
3352 #define CAN_TI0R_EXID_Pos (3U)
3353 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
3354 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
3355 #define CAN_TI0R_STID_Pos (21U)
3356 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
3357 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
3358
3359 /****************** Bit definition for CAN_TDT0R register *******************/
3360 #define CAN_TDT0R_DLC_Pos (0U)
3361 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
3362 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
3363 #define CAN_TDT0R_TGT_Pos (8U)
3364 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
3365 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
3366 #define CAN_TDT0R_TIME_Pos (16U)
3367 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
3368 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
3369
3370 /****************** Bit definition for CAN_TDL0R register *******************/
3371 #define CAN_TDL0R_DATA0_Pos (0U)
3372 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
3373 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
3374 #define CAN_TDL0R_DATA1_Pos (8U)
3375 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
3376 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
3377 #define CAN_TDL0R_DATA2_Pos (16U)
3378 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
3379 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
3380 #define CAN_TDL0R_DATA3_Pos (24U)
3381 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
3382 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
3383
3384 /****************** Bit definition for CAN_TDH0R register *******************/
3385 #define CAN_TDH0R_DATA4_Pos (0U)
3386 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
3387 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
3388 #define CAN_TDH0R_DATA5_Pos (8U)
3389 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
3390 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
3391 #define CAN_TDH0R_DATA6_Pos (16U)
3392 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
3393 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
3394 #define CAN_TDH0R_DATA7_Pos (24U)
3395 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
3396 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
3397
3398 /******************* Bit definition for CAN_TI1R register *******************/
3399 #define CAN_TI1R_TXRQ_Pos (0U)
3400 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
3401 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
3402 #define CAN_TI1R_RTR_Pos (1U)
3403 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
3404 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
3405 #define CAN_TI1R_IDE_Pos (2U)
3406 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
3407 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
3408 #define CAN_TI1R_EXID_Pos (3U)
3409 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
3410 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
3411 #define CAN_TI1R_STID_Pos (21U)
3412 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
3413 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
3414
3415 /******************* Bit definition for CAN_TDT1R register ******************/
3416 #define CAN_TDT1R_DLC_Pos (0U)
3417 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
3418 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
3419 #define CAN_TDT1R_TGT_Pos (8U)
3420 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
3421 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
3422 #define CAN_TDT1R_TIME_Pos (16U)
3423 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
3424 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
3425
3426 /******************* Bit definition for CAN_TDL1R register ******************/
3427 #define CAN_TDL1R_DATA0_Pos (0U)
3428 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
3429 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
3430 #define CAN_TDL1R_DATA1_Pos (8U)
3431 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
3432 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
3433 #define CAN_TDL1R_DATA2_Pos (16U)
3434 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
3435 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
3436 #define CAN_TDL1R_DATA3_Pos (24U)
3437 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
3438 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
3439
3440 /******************* Bit definition for CAN_TDH1R register ******************/
3441 #define CAN_TDH1R_DATA4_Pos (0U)
3442 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
3443 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
3444 #define CAN_TDH1R_DATA5_Pos (8U)
3445 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
3446 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
3447 #define CAN_TDH1R_DATA6_Pos (16U)
3448 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
3449 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
3450 #define CAN_TDH1R_DATA7_Pos (24U)
3451 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
3452 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
3453
3454 /******************* Bit definition for CAN_TI2R register *******************/
3455 #define CAN_TI2R_TXRQ_Pos (0U)
3456 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
3457 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
3458 #define CAN_TI2R_RTR_Pos (1U)
3459 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
3460 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
3461 #define CAN_TI2R_IDE_Pos (2U)
3462 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
3463 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
3464 #define CAN_TI2R_EXID_Pos (3U)
3465 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
3466 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
3467 #define CAN_TI2R_STID_Pos (21U)
3468 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
3469 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
3470
3471 /******************* Bit definition for CAN_TDT2R register ******************/
3472 #define CAN_TDT2R_DLC_Pos (0U)
3473 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
3474 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
3475 #define CAN_TDT2R_TGT_Pos (8U)
3476 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
3477 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
3478 #define CAN_TDT2R_TIME_Pos (16U)
3479 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
3480 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
3481
3482 /******************* Bit definition for CAN_TDL2R register ******************/
3483 #define CAN_TDL2R_DATA0_Pos (0U)
3484 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
3485 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
3486 #define CAN_TDL2R_DATA1_Pos (8U)
3487 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
3488 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
3489 #define CAN_TDL2R_DATA2_Pos (16U)
3490 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
3491 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
3492 #define CAN_TDL2R_DATA3_Pos (24U)
3493 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
3494 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
3495
3496 /******************* Bit definition for CAN_TDH2R register ******************/
3497 #define CAN_TDH2R_DATA4_Pos (0U)
3498 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
3499 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
3500 #define CAN_TDH2R_DATA5_Pos (8U)
3501 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
3502 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
3503 #define CAN_TDH2R_DATA6_Pos (16U)
3504 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
3505 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
3506 #define CAN_TDH2R_DATA7_Pos (24U)
3507 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
3508 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
3509
3510 /******************* Bit definition for CAN_RI0R register *******************/
3511 #define CAN_RI0R_RTR_Pos (1U)
3512 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
3513 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
3514 #define CAN_RI0R_IDE_Pos (2U)
3515 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
3516 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
3517 #define CAN_RI0R_EXID_Pos (3U)
3518 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
3519 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
3520 #define CAN_RI0R_STID_Pos (21U)
3521 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
3522 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
3523
3524 /******************* Bit definition for CAN_RDT0R register ******************/
3525 #define CAN_RDT0R_DLC_Pos (0U)
3526 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
3527 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
3528 #define CAN_RDT0R_FMI_Pos (8U)
3529 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
3530 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
3531 #define CAN_RDT0R_TIME_Pos (16U)
3532 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
3533 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
3534
3535 /******************* Bit definition for CAN_RDL0R register ******************/
3536 #define CAN_RDL0R_DATA0_Pos (0U)
3537 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
3538 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
3539 #define CAN_RDL0R_DATA1_Pos (8U)
3540 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
3541 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
3542 #define CAN_RDL0R_DATA2_Pos (16U)
3543 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
3544 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
3545 #define CAN_RDL0R_DATA3_Pos (24U)
3546 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
3547 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
3548
3549 /******************* Bit definition for CAN_RDH0R register ******************/
3550 #define CAN_RDH0R_DATA4_Pos (0U)
3551 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
3552 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
3553 #define CAN_RDH0R_DATA5_Pos (8U)
3554 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
3555 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
3556 #define CAN_RDH0R_DATA6_Pos (16U)
3557 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
3558 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
3559 #define CAN_RDH0R_DATA7_Pos (24U)
3560 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
3561 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
3562
3563 /******************* Bit definition for CAN_RI1R register *******************/
3564 #define CAN_RI1R_RTR_Pos (1U)
3565 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
3566 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
3567 #define CAN_RI1R_IDE_Pos (2U)
3568 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
3569 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
3570 #define CAN_RI1R_EXID_Pos (3U)
3571 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
3572 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
3573 #define CAN_RI1R_STID_Pos (21U)
3574 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
3575 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
3576
3577 /******************* Bit definition for CAN_RDT1R register ******************/
3578 #define CAN_RDT1R_DLC_Pos (0U)
3579 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
3580 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
3581 #define CAN_RDT1R_FMI_Pos (8U)
3582 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
3583 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
3584 #define CAN_RDT1R_TIME_Pos (16U)
3585 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
3586 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
3587
3588 /******************* Bit definition for CAN_RDL1R register ******************/
3589 #define CAN_RDL1R_DATA0_Pos (0U)
3590 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
3591 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
3592 #define CAN_RDL1R_DATA1_Pos (8U)
3593 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
3594 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
3595 #define CAN_RDL1R_DATA2_Pos (16U)
3596 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
3597 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
3598 #define CAN_RDL1R_DATA3_Pos (24U)
3599 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
3600 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
3601
3602 /******************* Bit definition for CAN_RDH1R register ******************/
3603 #define CAN_RDH1R_DATA4_Pos (0U)
3604 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
3605 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
3606 #define CAN_RDH1R_DATA5_Pos (8U)
3607 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
3608 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
3609 #define CAN_RDH1R_DATA6_Pos (16U)
3610 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
3611 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
3612 #define CAN_RDH1R_DATA7_Pos (24U)
3613 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
3614 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
3615
3616 /*!<CAN filter registers */
3617 /******************* Bit definition for CAN_FMR register ********************/
3618 #define CAN_FMR_FINIT_Pos (0U)
3619 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
3620 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
3621
3622 /******************* Bit definition for CAN_FM1R register *******************/
3623 #define CAN_FM1R_FBM_Pos (0U)
3624 #define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
3625 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
3626 #define CAN_FM1R_FBM0_Pos (0U)
3627 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
3628 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
3629 #define CAN_FM1R_FBM1_Pos (1U)
3630 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
3631 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
3632 #define CAN_FM1R_FBM2_Pos (2U)
3633 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
3634 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
3635 #define CAN_FM1R_FBM3_Pos (3U)
3636 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
3637 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
3638 #define CAN_FM1R_FBM4_Pos (4U)
3639 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
3640 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
3641 #define CAN_FM1R_FBM5_Pos (5U)
3642 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
3643 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
3644 #define CAN_FM1R_FBM6_Pos (6U)
3645 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
3646 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
3647 #define CAN_FM1R_FBM7_Pos (7U)
3648 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
3649 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
3650 #define CAN_FM1R_FBM8_Pos (8U)
3651 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
3652 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
3653 #define CAN_FM1R_FBM9_Pos (9U)
3654 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
3655 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
3656 #define CAN_FM1R_FBM10_Pos (10U)
3657 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
3658 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
3659 #define CAN_FM1R_FBM11_Pos (11U)
3660 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
3661 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
3662 #define CAN_FM1R_FBM12_Pos (12U)
3663 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
3664 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
3665 #define CAN_FM1R_FBM13_Pos (13U)
3666 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
3667 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
3668
3669 /******************* Bit definition for CAN_FS1R register *******************/
3670 #define CAN_FS1R_FSC_Pos (0U)
3671 #define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
3672 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
3673 #define CAN_FS1R_FSC0_Pos (0U)
3674 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
3675 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
3676 #define CAN_FS1R_FSC1_Pos (1U)
3677 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
3678 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
3679 #define CAN_FS1R_FSC2_Pos (2U)
3680 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
3681 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
3682 #define CAN_FS1R_FSC3_Pos (3U)
3683 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
3684 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
3685 #define CAN_FS1R_FSC4_Pos (4U)
3686 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
3687 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
3688 #define CAN_FS1R_FSC5_Pos (5U)
3689 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
3690 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
3691 #define CAN_FS1R_FSC6_Pos (6U)
3692 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
3693 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
3694 #define CAN_FS1R_FSC7_Pos (7U)
3695 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
3696 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
3697 #define CAN_FS1R_FSC8_Pos (8U)
3698 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
3699 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
3700 #define CAN_FS1R_FSC9_Pos (9U)
3701 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
3702 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
3703 #define CAN_FS1R_FSC10_Pos (10U)
3704 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
3705 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
3706 #define CAN_FS1R_FSC11_Pos (11U)
3707 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
3708 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
3709 #define CAN_FS1R_FSC12_Pos (12U)
3710 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
3711 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
3712 #define CAN_FS1R_FSC13_Pos (13U)
3713 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
3714 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
3715
3716 /****************** Bit definition for CAN_FFA1R register *******************/
3717 #define CAN_FFA1R_FFA_Pos (0U)
3718 #define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
3719 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
3720 #define CAN_FFA1R_FFA0_Pos (0U)
3721 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
3722 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
3723 #define CAN_FFA1R_FFA1_Pos (1U)
3724 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
3725 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
3726 #define CAN_FFA1R_FFA2_Pos (2U)
3727 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
3728 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
3729 #define CAN_FFA1R_FFA3_Pos (3U)
3730 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
3731 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
3732 #define CAN_FFA1R_FFA4_Pos (4U)
3733 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
3734 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
3735 #define CAN_FFA1R_FFA5_Pos (5U)
3736 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
3737 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
3738 #define CAN_FFA1R_FFA6_Pos (6U)
3739 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
3740 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
3741 #define CAN_FFA1R_FFA7_Pos (7U)
3742 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
3743 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
3744 #define CAN_FFA1R_FFA8_Pos (8U)
3745 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
3746 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
3747 #define CAN_FFA1R_FFA9_Pos (9U)
3748 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
3749 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
3750 #define CAN_FFA1R_FFA10_Pos (10U)
3751 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
3752 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
3753 #define CAN_FFA1R_FFA11_Pos (11U)
3754 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
3755 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
3756 #define CAN_FFA1R_FFA12_Pos (12U)
3757 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
3758 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
3759 #define CAN_FFA1R_FFA13_Pos (13U)
3760 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
3761 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
3762
3763 /******************* Bit definition for CAN_FA1R register *******************/
3764 #define CAN_FA1R_FACT_Pos (0U)
3765 #define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
3766 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
3767 #define CAN_FA1R_FACT0_Pos (0U)
3768 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
3769 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
3770 #define CAN_FA1R_FACT1_Pos (1U)
3771 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
3772 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
3773 #define CAN_FA1R_FACT2_Pos (2U)
3774 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
3775 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
3776 #define CAN_FA1R_FACT3_Pos (3U)
3777 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
3778 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
3779 #define CAN_FA1R_FACT4_Pos (4U)
3780 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
3781 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
3782 #define CAN_FA1R_FACT5_Pos (5U)
3783 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
3784 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
3785 #define CAN_FA1R_FACT6_Pos (6U)
3786 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
3787 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
3788 #define CAN_FA1R_FACT7_Pos (7U)
3789 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
3790 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
3791 #define CAN_FA1R_FACT8_Pos (8U)
3792 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
3793 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
3794 #define CAN_FA1R_FACT9_Pos (9U)
3795 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
3796 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
3797 #define CAN_FA1R_FACT10_Pos (10U)
3798 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
3799 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
3800 #define CAN_FA1R_FACT11_Pos (11U)
3801 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
3802 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
3803 #define CAN_FA1R_FACT12_Pos (12U)
3804 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
3805 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
3806 #define CAN_FA1R_FACT13_Pos (13U)
3807 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
3808 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
3809
3810 /******************* Bit definition for CAN_F0R1 register *******************/
3811 #define CAN_F0R1_FB0_Pos (0U)
3812 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
3813 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
3814 #define CAN_F0R1_FB1_Pos (1U)
3815 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
3816 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
3817 #define CAN_F0R1_FB2_Pos (2U)
3818 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
3819 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
3820 #define CAN_F0R1_FB3_Pos (3U)
3821 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
3822 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
3823 #define CAN_F0R1_FB4_Pos (4U)
3824 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
3825 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
3826 #define CAN_F0R1_FB5_Pos (5U)
3827 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
3828 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
3829 #define CAN_F0R1_FB6_Pos (6U)
3830 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
3831 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
3832 #define CAN_F0R1_FB7_Pos (7U)
3833 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
3834 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
3835 #define CAN_F0R1_FB8_Pos (8U)
3836 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
3837 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
3838 #define CAN_F0R1_FB9_Pos (9U)
3839 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
3840 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
3841 #define CAN_F0R1_FB10_Pos (10U)
3842 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
3843 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
3844 #define CAN_F0R1_FB11_Pos (11U)
3845 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
3846 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
3847 #define CAN_F0R1_FB12_Pos (12U)
3848 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
3849 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
3850 #define CAN_F0R1_FB13_Pos (13U)
3851 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
3852 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
3853 #define CAN_F0R1_FB14_Pos (14U)
3854 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
3855 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
3856 #define CAN_F0R1_FB15_Pos (15U)
3857 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
3858 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
3859 #define CAN_F0R1_FB16_Pos (16U)
3860 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
3861 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
3862 #define CAN_F0R1_FB17_Pos (17U)
3863 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
3864 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
3865 #define CAN_F0R1_FB18_Pos (18U)
3866 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
3867 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
3868 #define CAN_F0R1_FB19_Pos (19U)
3869 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
3870 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
3871 #define CAN_F0R1_FB20_Pos (20U)
3872 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
3873 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
3874 #define CAN_F0R1_FB21_Pos (21U)
3875 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
3876 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
3877 #define CAN_F0R1_FB22_Pos (22U)
3878 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
3879 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
3880 #define CAN_F0R1_FB23_Pos (23U)
3881 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
3882 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
3883 #define CAN_F0R1_FB24_Pos (24U)
3884 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
3885 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
3886 #define CAN_F0R1_FB25_Pos (25U)
3887 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
3888 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
3889 #define CAN_F0R1_FB26_Pos (26U)
3890 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
3891 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
3892 #define CAN_F0R1_FB27_Pos (27U)
3893 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
3894 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
3895 #define CAN_F0R1_FB28_Pos (28U)
3896 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
3897 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
3898 #define CAN_F0R1_FB29_Pos (29U)
3899 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
3900 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
3901 #define CAN_F0R1_FB30_Pos (30U)
3902 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
3903 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
3904 #define CAN_F0R1_FB31_Pos (31U)
3905 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
3906 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
3907
3908 /******************* Bit definition for CAN_F1R1 register *******************/
3909 #define CAN_F1R1_FB0_Pos (0U)
3910 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
3911 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
3912 #define CAN_F1R1_FB1_Pos (1U)
3913 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
3914 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
3915 #define CAN_F1R1_FB2_Pos (2U)
3916 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
3917 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
3918 #define CAN_F1R1_FB3_Pos (3U)
3919 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
3920 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
3921 #define CAN_F1R1_FB4_Pos (4U)
3922 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
3923 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
3924 #define CAN_F1R1_FB5_Pos (5U)
3925 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
3926 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
3927 #define CAN_F1R1_FB6_Pos (6U)
3928 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
3929 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
3930 #define CAN_F1R1_FB7_Pos (7U)
3931 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
3932 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
3933 #define CAN_F1R1_FB8_Pos (8U)
3934 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
3935 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
3936 #define CAN_F1R1_FB9_Pos (9U)
3937 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
3938 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
3939 #define CAN_F1R1_FB10_Pos (10U)
3940 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
3941 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
3942 #define CAN_F1R1_FB11_Pos (11U)
3943 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
3944 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
3945 #define CAN_F1R1_FB12_Pos (12U)
3946 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
3947 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
3948 #define CAN_F1R1_FB13_Pos (13U)
3949 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
3950 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
3951 #define CAN_F1R1_FB14_Pos (14U)
3952 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
3953 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
3954 #define CAN_F1R1_FB15_Pos (15U)
3955 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
3956 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
3957 #define CAN_F1R1_FB16_Pos (16U)
3958 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
3959 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
3960 #define CAN_F1R1_FB17_Pos (17U)
3961 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
3962 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
3963 #define CAN_F1R1_FB18_Pos (18U)
3964 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
3965 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
3966 #define CAN_F1R1_FB19_Pos (19U)
3967 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
3968 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
3969 #define CAN_F1R1_FB20_Pos (20U)
3970 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
3971 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
3972 #define CAN_F1R1_FB21_Pos (21U)
3973 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
3974 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
3975 #define CAN_F1R1_FB22_Pos (22U)
3976 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
3977 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
3978 #define CAN_F1R1_FB23_Pos (23U)
3979 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
3980 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
3981 #define CAN_F1R1_FB24_Pos (24U)
3982 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
3983 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
3984 #define CAN_F1R1_FB25_Pos (25U)
3985 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
3986 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
3987 #define CAN_F1R1_FB26_Pos (26U)
3988 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
3989 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
3990 #define CAN_F1R1_FB27_Pos (27U)
3991 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
3992 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
3993 #define CAN_F1R1_FB28_Pos (28U)
3994 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
3995 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
3996 #define CAN_F1R1_FB29_Pos (29U)
3997 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
3998 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
3999 #define CAN_F1R1_FB30_Pos (30U)
4000 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
4001 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
4002 #define CAN_F1R1_FB31_Pos (31U)
4003 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
4004 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
4005
4006 /******************* Bit definition for CAN_F2R1 register *******************/
4007 #define CAN_F2R1_FB0_Pos (0U)
4008 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
4009 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
4010 #define CAN_F2R1_FB1_Pos (1U)
4011 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
4012 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
4013 #define CAN_F2R1_FB2_Pos (2U)
4014 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
4015 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
4016 #define CAN_F2R1_FB3_Pos (3U)
4017 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
4018 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
4019 #define CAN_F2R1_FB4_Pos (4U)
4020 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
4021 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
4022 #define CAN_F2R1_FB5_Pos (5U)
4023 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
4024 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
4025 #define CAN_F2R1_FB6_Pos (6U)
4026 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
4027 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
4028 #define CAN_F2R1_FB7_Pos (7U)
4029 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
4030 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
4031 #define CAN_F2R1_FB8_Pos (8U)
4032 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
4033 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
4034 #define CAN_F2R1_FB9_Pos (9U)
4035 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
4036 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
4037 #define CAN_F2R1_FB10_Pos (10U)
4038 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
4039 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
4040 #define CAN_F2R1_FB11_Pos (11U)
4041 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
4042 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
4043 #define CAN_F2R1_FB12_Pos (12U)
4044 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
4045 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
4046 #define CAN_F2R1_FB13_Pos (13U)
4047 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
4048 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
4049 #define CAN_F2R1_FB14_Pos (14U)
4050 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
4051 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
4052 #define CAN_F2R1_FB15_Pos (15U)
4053 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
4054 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
4055 #define CAN_F2R1_FB16_Pos (16U)
4056 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
4057 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
4058 #define CAN_F2R1_FB17_Pos (17U)
4059 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
4060 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
4061 #define CAN_F2R1_FB18_Pos (18U)
4062 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
4063 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
4064 #define CAN_F2R1_FB19_Pos (19U)
4065 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
4066 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
4067 #define CAN_F2R1_FB20_Pos (20U)
4068 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
4069 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
4070 #define CAN_F2R1_FB21_Pos (21U)
4071 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
4072 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
4073 #define CAN_F2R1_FB22_Pos (22U)
4074 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
4075 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
4076 #define CAN_F2R1_FB23_Pos (23U)
4077 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
4078 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
4079 #define CAN_F2R1_FB24_Pos (24U)
4080 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
4081 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
4082 #define CAN_F2R1_FB25_Pos (25U)
4083 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
4084 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
4085 #define CAN_F2R1_FB26_Pos (26U)
4086 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
4087 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
4088 #define CAN_F2R1_FB27_Pos (27U)
4089 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
4090 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
4091 #define CAN_F2R1_FB28_Pos (28U)
4092 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
4093 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
4094 #define CAN_F2R1_FB29_Pos (29U)
4095 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
4096 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
4097 #define CAN_F2R1_FB30_Pos (30U)
4098 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
4099 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
4100 #define CAN_F2R1_FB31_Pos (31U)
4101 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
4102 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
4103
4104 /******************* Bit definition for CAN_F3R1 register *******************/
4105 #define CAN_F3R1_FB0_Pos (0U)
4106 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
4107 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
4108 #define CAN_F3R1_FB1_Pos (1U)
4109 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
4110 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
4111 #define CAN_F3R1_FB2_Pos (2U)
4112 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
4113 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
4114 #define CAN_F3R1_FB3_Pos (3U)
4115 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
4116 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
4117 #define CAN_F3R1_FB4_Pos (4U)
4118 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
4119 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
4120 #define CAN_F3R1_FB5_Pos (5U)
4121 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
4122 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
4123 #define CAN_F3R1_FB6_Pos (6U)
4124 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
4125 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
4126 #define CAN_F3R1_FB7_Pos (7U)
4127 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
4128 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
4129 #define CAN_F3R1_FB8_Pos (8U)
4130 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
4131 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
4132 #define CAN_F3R1_FB9_Pos (9U)
4133 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
4134 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
4135 #define CAN_F3R1_FB10_Pos (10U)
4136 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
4137 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
4138 #define CAN_F3R1_FB11_Pos (11U)
4139 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
4140 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
4141 #define CAN_F3R1_FB12_Pos (12U)
4142 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
4143 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
4144 #define CAN_F3R1_FB13_Pos (13U)
4145 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
4146 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
4147 #define CAN_F3R1_FB14_Pos (14U)
4148 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
4149 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
4150 #define CAN_F3R1_FB15_Pos (15U)
4151 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
4152 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
4153 #define CAN_F3R1_FB16_Pos (16U)
4154 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
4155 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
4156 #define CAN_F3R1_FB17_Pos (17U)
4157 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
4158 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
4159 #define CAN_F3R1_FB18_Pos (18U)
4160 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
4161 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
4162 #define CAN_F3R1_FB19_Pos (19U)
4163 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
4164 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
4165 #define CAN_F3R1_FB20_Pos (20U)
4166 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
4167 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
4168 #define CAN_F3R1_FB21_Pos (21U)
4169 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
4170 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
4171 #define CAN_F3R1_FB22_Pos (22U)
4172 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
4173 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
4174 #define CAN_F3R1_FB23_Pos (23U)
4175 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
4176 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
4177 #define CAN_F3R1_FB24_Pos (24U)
4178 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
4179 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
4180 #define CAN_F3R1_FB25_Pos (25U)
4181 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
4182 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
4183 #define CAN_F3R1_FB26_Pos (26U)
4184 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
4185 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
4186 #define CAN_F3R1_FB27_Pos (27U)
4187 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
4188 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
4189 #define CAN_F3R1_FB28_Pos (28U)
4190 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
4191 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
4192 #define CAN_F3R1_FB29_Pos (29U)
4193 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
4194 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
4195 #define CAN_F3R1_FB30_Pos (30U)
4196 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
4197 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
4198 #define CAN_F3R1_FB31_Pos (31U)
4199 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
4200 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
4201
4202 /******************* Bit definition for CAN_F4R1 register *******************/
4203 #define CAN_F4R1_FB0_Pos (0U)
4204 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
4205 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
4206 #define CAN_F4R1_FB1_Pos (1U)
4207 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
4208 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
4209 #define CAN_F4R1_FB2_Pos (2U)
4210 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
4211 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
4212 #define CAN_F4R1_FB3_Pos (3U)
4213 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
4214 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
4215 #define CAN_F4R1_FB4_Pos (4U)
4216 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
4217 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
4218 #define CAN_F4R1_FB5_Pos (5U)
4219 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
4220 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
4221 #define CAN_F4R1_FB6_Pos (6U)
4222 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
4223 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
4224 #define CAN_F4R1_FB7_Pos (7U)
4225 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
4226 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
4227 #define CAN_F4R1_FB8_Pos (8U)
4228 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
4229 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
4230 #define CAN_F4R1_FB9_Pos (9U)
4231 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
4232 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
4233 #define CAN_F4R1_FB10_Pos (10U)
4234 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
4235 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
4236 #define CAN_F4R1_FB11_Pos (11U)
4237 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
4238 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
4239 #define CAN_F4R1_FB12_Pos (12U)
4240 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
4241 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
4242 #define CAN_F4R1_FB13_Pos (13U)
4243 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
4244 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
4245 #define CAN_F4R1_FB14_Pos (14U)
4246 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
4247 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
4248 #define CAN_F4R1_FB15_Pos (15U)
4249 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
4250 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
4251 #define CAN_F4R1_FB16_Pos (16U)
4252 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
4253 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
4254 #define CAN_F4R1_FB17_Pos (17U)
4255 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
4256 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
4257 #define CAN_F4R1_FB18_Pos (18U)
4258 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
4259 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
4260 #define CAN_F4R1_FB19_Pos (19U)
4261 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
4262 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
4263 #define CAN_F4R1_FB20_Pos (20U)
4264 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
4265 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
4266 #define CAN_F4R1_FB21_Pos (21U)
4267 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
4268 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
4269 #define CAN_F4R1_FB22_Pos (22U)
4270 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
4271 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
4272 #define CAN_F4R1_FB23_Pos (23U)
4273 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
4274 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
4275 #define CAN_F4R1_FB24_Pos (24U)
4276 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
4277 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
4278 #define CAN_F4R1_FB25_Pos (25U)
4279 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
4280 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
4281 #define CAN_F4R1_FB26_Pos (26U)
4282 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
4283 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
4284 #define CAN_F4R1_FB27_Pos (27U)
4285 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
4286 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
4287 #define CAN_F4R1_FB28_Pos (28U)
4288 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
4289 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
4290 #define CAN_F4R1_FB29_Pos (29U)
4291 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
4292 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
4293 #define CAN_F4R1_FB30_Pos (30U)
4294 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
4295 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
4296 #define CAN_F4R1_FB31_Pos (31U)
4297 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
4298 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
4299
4300 /******************* Bit definition for CAN_F5R1 register *******************/
4301 #define CAN_F5R1_FB0_Pos (0U)
4302 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
4303 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
4304 #define CAN_F5R1_FB1_Pos (1U)
4305 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
4306 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
4307 #define CAN_F5R1_FB2_Pos (2U)
4308 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
4309 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
4310 #define CAN_F5R1_FB3_Pos (3U)
4311 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
4312 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
4313 #define CAN_F5R1_FB4_Pos (4U)
4314 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
4315 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
4316 #define CAN_F5R1_FB5_Pos (5U)
4317 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
4318 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
4319 #define CAN_F5R1_FB6_Pos (6U)
4320 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
4321 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
4322 #define CAN_F5R1_FB7_Pos (7U)
4323 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
4324 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
4325 #define CAN_F5R1_FB8_Pos (8U)
4326 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
4327 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
4328 #define CAN_F5R1_FB9_Pos (9U)
4329 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
4330 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
4331 #define CAN_F5R1_FB10_Pos (10U)
4332 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
4333 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
4334 #define CAN_F5R1_FB11_Pos (11U)
4335 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
4336 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
4337 #define CAN_F5R1_FB12_Pos (12U)
4338 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
4339 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
4340 #define CAN_F5R1_FB13_Pos (13U)
4341 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
4342 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
4343 #define CAN_F5R1_FB14_Pos (14U)
4344 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
4345 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
4346 #define CAN_F5R1_FB15_Pos (15U)
4347 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
4348 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
4349 #define CAN_F5R1_FB16_Pos (16U)
4350 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
4351 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
4352 #define CAN_F5R1_FB17_Pos (17U)
4353 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
4354 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
4355 #define CAN_F5R1_FB18_Pos (18U)
4356 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
4357 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
4358 #define CAN_F5R1_FB19_Pos (19U)
4359 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
4360 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
4361 #define CAN_F5R1_FB20_Pos (20U)
4362 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
4363 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
4364 #define CAN_F5R1_FB21_Pos (21U)
4365 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
4366 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
4367 #define CAN_F5R1_FB22_Pos (22U)
4368 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
4369 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
4370 #define CAN_F5R1_FB23_Pos (23U)
4371 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
4372 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
4373 #define CAN_F5R1_FB24_Pos (24U)
4374 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
4375 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
4376 #define CAN_F5R1_FB25_Pos (25U)
4377 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
4378 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
4379 #define CAN_F5R1_FB26_Pos (26U)
4380 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
4381 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
4382 #define CAN_F5R1_FB27_Pos (27U)
4383 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
4384 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
4385 #define CAN_F5R1_FB28_Pos (28U)
4386 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
4387 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
4388 #define CAN_F5R1_FB29_Pos (29U)
4389 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
4390 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
4391 #define CAN_F5R1_FB30_Pos (30U)
4392 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
4393 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
4394 #define CAN_F5R1_FB31_Pos (31U)
4395 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
4396 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
4397
4398 /******************* Bit definition for CAN_F6R1 register *******************/
4399 #define CAN_F6R1_FB0_Pos (0U)
4400 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
4401 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
4402 #define CAN_F6R1_FB1_Pos (1U)
4403 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
4404 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
4405 #define CAN_F6R1_FB2_Pos (2U)
4406 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
4407 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
4408 #define CAN_F6R1_FB3_Pos (3U)
4409 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
4410 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
4411 #define CAN_F6R1_FB4_Pos (4U)
4412 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
4413 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
4414 #define CAN_F6R1_FB5_Pos (5U)
4415 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
4416 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
4417 #define CAN_F6R1_FB6_Pos (6U)
4418 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
4419 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
4420 #define CAN_F6R1_FB7_Pos (7U)
4421 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
4422 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
4423 #define CAN_F6R1_FB8_Pos (8U)
4424 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
4425 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
4426 #define CAN_F6R1_FB9_Pos (9U)
4427 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
4428 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
4429 #define CAN_F6R1_FB10_Pos (10U)
4430 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
4431 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
4432 #define CAN_F6R1_FB11_Pos (11U)
4433 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
4434 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
4435 #define CAN_F6R1_FB12_Pos (12U)
4436 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
4437 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
4438 #define CAN_F6R1_FB13_Pos (13U)
4439 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
4440 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
4441 #define CAN_F6R1_FB14_Pos (14U)
4442 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
4443 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
4444 #define CAN_F6R1_FB15_Pos (15U)
4445 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
4446 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
4447 #define CAN_F6R1_FB16_Pos (16U)
4448 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
4449 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
4450 #define CAN_F6R1_FB17_Pos (17U)
4451 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
4452 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
4453 #define CAN_F6R1_FB18_Pos (18U)
4454 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
4455 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
4456 #define CAN_F6R1_FB19_Pos (19U)
4457 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
4458 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
4459 #define CAN_F6R1_FB20_Pos (20U)
4460 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
4461 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
4462 #define CAN_F6R1_FB21_Pos (21U)
4463 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
4464 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
4465 #define CAN_F6R1_FB22_Pos (22U)
4466 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
4467 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
4468 #define CAN_F6R1_FB23_Pos (23U)
4469 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
4470 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
4471 #define CAN_F6R1_FB24_Pos (24U)
4472 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
4473 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
4474 #define CAN_F6R1_FB25_Pos (25U)
4475 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
4476 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
4477 #define CAN_F6R1_FB26_Pos (26U)
4478 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
4479 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
4480 #define CAN_F6R1_FB27_Pos (27U)
4481 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
4482 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
4483 #define CAN_F6R1_FB28_Pos (28U)
4484 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
4485 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
4486 #define CAN_F6R1_FB29_Pos (29U)
4487 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
4488 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
4489 #define CAN_F6R1_FB30_Pos (30U)
4490 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
4491 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
4492 #define CAN_F6R1_FB31_Pos (31U)
4493 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
4494 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
4495
4496 /******************* Bit definition for CAN_F7R1 register *******************/
4497 #define CAN_F7R1_FB0_Pos (0U)
4498 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
4499 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
4500 #define CAN_F7R1_FB1_Pos (1U)
4501 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
4502 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
4503 #define CAN_F7R1_FB2_Pos (2U)
4504 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
4505 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
4506 #define CAN_F7R1_FB3_Pos (3U)
4507 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
4508 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
4509 #define CAN_F7R1_FB4_Pos (4U)
4510 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
4511 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
4512 #define CAN_F7R1_FB5_Pos (5U)
4513 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
4514 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
4515 #define CAN_F7R1_FB6_Pos (6U)
4516 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
4517 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
4518 #define CAN_F7R1_FB7_Pos (7U)
4519 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
4520 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
4521 #define CAN_F7R1_FB8_Pos (8U)
4522 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
4523 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
4524 #define CAN_F7R1_FB9_Pos (9U)
4525 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
4526 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
4527 #define CAN_F7R1_FB10_Pos (10U)
4528 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
4529 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
4530 #define CAN_F7R1_FB11_Pos (11U)
4531 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
4532 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
4533 #define CAN_F7R1_FB12_Pos (12U)
4534 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
4535 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
4536 #define CAN_F7R1_FB13_Pos (13U)
4537 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
4538 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
4539 #define CAN_F7R1_FB14_Pos (14U)
4540 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
4541 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
4542 #define CAN_F7R1_FB15_Pos (15U)
4543 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
4544 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
4545 #define CAN_F7R1_FB16_Pos (16U)
4546 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
4547 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
4548 #define CAN_F7R1_FB17_Pos (17U)
4549 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
4550 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
4551 #define CAN_F7R1_FB18_Pos (18U)
4552 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
4553 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
4554 #define CAN_F7R1_FB19_Pos (19U)
4555 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
4556 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
4557 #define CAN_F7R1_FB20_Pos (20U)
4558 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
4559 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
4560 #define CAN_F7R1_FB21_Pos (21U)
4561 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
4562 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
4563 #define CAN_F7R1_FB22_Pos (22U)
4564 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
4565 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
4566 #define CAN_F7R1_FB23_Pos (23U)
4567 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
4568 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
4569 #define CAN_F7R1_FB24_Pos (24U)
4570 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
4571 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
4572 #define CAN_F7R1_FB25_Pos (25U)
4573 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
4574 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
4575 #define CAN_F7R1_FB26_Pos (26U)
4576 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
4577 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
4578 #define CAN_F7R1_FB27_Pos (27U)
4579 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
4580 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
4581 #define CAN_F7R1_FB28_Pos (28U)
4582 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
4583 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
4584 #define CAN_F7R1_FB29_Pos (29U)
4585 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
4586 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
4587 #define CAN_F7R1_FB30_Pos (30U)
4588 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
4589 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
4590 #define CAN_F7R1_FB31_Pos (31U)
4591 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
4592 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
4593
4594 /******************* Bit definition for CAN_F8R1 register *******************/
4595 #define CAN_F8R1_FB0_Pos (0U)
4596 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
4597 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
4598 #define CAN_F8R1_FB1_Pos (1U)
4599 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
4600 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
4601 #define CAN_F8R1_FB2_Pos (2U)
4602 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
4603 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
4604 #define CAN_F8R1_FB3_Pos (3U)
4605 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
4606 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
4607 #define CAN_F8R1_FB4_Pos (4U)
4608 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
4609 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
4610 #define CAN_F8R1_FB5_Pos (5U)
4611 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
4612 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
4613 #define CAN_F8R1_FB6_Pos (6U)
4614 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
4615 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
4616 #define CAN_F8R1_FB7_Pos (7U)
4617 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
4618 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
4619 #define CAN_F8R1_FB8_Pos (8U)
4620 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
4621 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
4622 #define CAN_F8R1_FB9_Pos (9U)
4623 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
4624 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
4625 #define CAN_F8R1_FB10_Pos (10U)
4626 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
4627 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
4628 #define CAN_F8R1_FB11_Pos (11U)
4629 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
4630 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
4631 #define CAN_F8R1_FB12_Pos (12U)
4632 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
4633 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
4634 #define CAN_F8R1_FB13_Pos (13U)
4635 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
4636 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
4637 #define CAN_F8R1_FB14_Pos (14U)
4638 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
4639 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
4640 #define CAN_F8R1_FB15_Pos (15U)
4641 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
4642 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
4643 #define CAN_F8R1_FB16_Pos (16U)
4644 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
4645 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
4646 #define CAN_F8R1_FB17_Pos (17U)
4647 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
4648 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
4649 #define CAN_F8R1_FB18_Pos (18U)
4650 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
4651 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
4652 #define CAN_F8R1_FB19_Pos (19U)
4653 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
4654 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
4655 #define CAN_F8R1_FB20_Pos (20U)
4656 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
4657 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
4658 #define CAN_F8R1_FB21_Pos (21U)
4659 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
4660 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
4661 #define CAN_F8R1_FB22_Pos (22U)
4662 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
4663 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
4664 #define CAN_F8R1_FB23_Pos (23U)
4665 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
4666 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
4667 #define CAN_F8R1_FB24_Pos (24U)
4668 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
4669 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
4670 #define CAN_F8R1_FB25_Pos (25U)
4671 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
4672 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
4673 #define CAN_F8R1_FB26_Pos (26U)
4674 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
4675 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
4676 #define CAN_F8R1_FB27_Pos (27U)
4677 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
4678 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
4679 #define CAN_F8R1_FB28_Pos (28U)
4680 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
4681 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
4682 #define CAN_F8R1_FB29_Pos (29U)
4683 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
4684 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
4685 #define CAN_F8R1_FB30_Pos (30U)
4686 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
4687 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
4688 #define CAN_F8R1_FB31_Pos (31U)
4689 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
4690 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
4691
4692 /******************* Bit definition for CAN_F9R1 register *******************/
4693 #define CAN_F9R1_FB0_Pos (0U)
4694 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
4695 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
4696 #define CAN_F9R1_FB1_Pos (1U)
4697 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
4698 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
4699 #define CAN_F9R1_FB2_Pos (2U)
4700 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
4701 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
4702 #define CAN_F9R1_FB3_Pos (3U)
4703 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
4704 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
4705 #define CAN_F9R1_FB4_Pos (4U)
4706 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
4707 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
4708 #define CAN_F9R1_FB5_Pos (5U)
4709 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
4710 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
4711 #define CAN_F9R1_FB6_Pos (6U)
4712 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
4713 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
4714 #define CAN_F9R1_FB7_Pos (7U)
4715 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
4716 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
4717 #define CAN_F9R1_FB8_Pos (8U)
4718 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
4719 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
4720 #define CAN_F9R1_FB9_Pos (9U)
4721 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
4722 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
4723 #define CAN_F9R1_FB10_Pos (10U)
4724 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
4725 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
4726 #define CAN_F9R1_FB11_Pos (11U)
4727 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
4728 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
4729 #define CAN_F9R1_FB12_Pos (12U)
4730 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
4731 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
4732 #define CAN_F9R1_FB13_Pos (13U)
4733 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
4734 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
4735 #define CAN_F9R1_FB14_Pos (14U)
4736 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
4737 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
4738 #define CAN_F9R1_FB15_Pos (15U)
4739 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
4740 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
4741 #define CAN_F9R1_FB16_Pos (16U)
4742 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
4743 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
4744 #define CAN_F9R1_FB17_Pos (17U)
4745 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
4746 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
4747 #define CAN_F9R1_FB18_Pos (18U)
4748 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
4749 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
4750 #define CAN_F9R1_FB19_Pos (19U)
4751 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
4752 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
4753 #define CAN_F9R1_FB20_Pos (20U)
4754 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
4755 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
4756 #define CAN_F9R1_FB21_Pos (21U)
4757 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
4758 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
4759 #define CAN_F9R1_FB22_Pos (22U)
4760 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
4761 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
4762 #define CAN_F9R1_FB23_Pos (23U)
4763 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
4764 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
4765 #define CAN_F9R1_FB24_Pos (24U)
4766 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
4767 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
4768 #define CAN_F9R1_FB25_Pos (25U)
4769 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
4770 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
4771 #define CAN_F9R1_FB26_Pos (26U)
4772 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
4773 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
4774 #define CAN_F9R1_FB27_Pos (27U)
4775 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
4776 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
4777 #define CAN_F9R1_FB28_Pos (28U)
4778 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
4779 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
4780 #define CAN_F9R1_FB29_Pos (29U)
4781 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
4782 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
4783 #define CAN_F9R1_FB30_Pos (30U)
4784 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
4785 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
4786 #define CAN_F9R1_FB31_Pos (31U)
4787 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
4788 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
4789
4790 /******************* Bit definition for CAN_F10R1 register ******************/
4791 #define CAN_F10R1_FB0_Pos (0U)
4792 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
4793 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
4794 #define CAN_F10R1_FB1_Pos (1U)
4795 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
4796 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
4797 #define CAN_F10R1_FB2_Pos (2U)
4798 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
4799 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
4800 #define CAN_F10R1_FB3_Pos (3U)
4801 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
4802 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
4803 #define CAN_F10R1_FB4_Pos (4U)
4804 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
4805 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
4806 #define CAN_F10R1_FB5_Pos (5U)
4807 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
4808 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
4809 #define CAN_F10R1_FB6_Pos (6U)
4810 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
4811 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
4812 #define CAN_F10R1_FB7_Pos (7U)
4813 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
4814 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
4815 #define CAN_F10R1_FB8_Pos (8U)
4816 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
4817 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
4818 #define CAN_F10R1_FB9_Pos (9U)
4819 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
4820 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
4821 #define CAN_F10R1_FB10_Pos (10U)
4822 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
4823 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
4824 #define CAN_F10R1_FB11_Pos (11U)
4825 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
4826 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
4827 #define CAN_F10R1_FB12_Pos (12U)
4828 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
4829 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
4830 #define CAN_F10R1_FB13_Pos (13U)
4831 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
4832 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
4833 #define CAN_F10R1_FB14_Pos (14U)
4834 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
4835 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
4836 #define CAN_F10R1_FB15_Pos (15U)
4837 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
4838 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
4839 #define CAN_F10R1_FB16_Pos (16U)
4840 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
4841 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
4842 #define CAN_F10R1_FB17_Pos (17U)
4843 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
4844 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
4845 #define CAN_F10R1_FB18_Pos (18U)
4846 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
4847 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
4848 #define CAN_F10R1_FB19_Pos (19U)
4849 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
4850 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
4851 #define CAN_F10R1_FB20_Pos (20U)
4852 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
4853 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
4854 #define CAN_F10R1_FB21_Pos (21U)
4855 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
4856 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
4857 #define CAN_F10R1_FB22_Pos (22U)
4858 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
4859 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
4860 #define CAN_F10R1_FB23_Pos (23U)
4861 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
4862 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
4863 #define CAN_F10R1_FB24_Pos (24U)
4864 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
4865 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
4866 #define CAN_F10R1_FB25_Pos (25U)
4867 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
4868 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
4869 #define CAN_F10R1_FB26_Pos (26U)
4870 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
4871 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
4872 #define CAN_F10R1_FB27_Pos (27U)
4873 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
4874 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
4875 #define CAN_F10R1_FB28_Pos (28U)
4876 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
4877 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
4878 #define CAN_F10R1_FB29_Pos (29U)
4879 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
4880 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
4881 #define CAN_F10R1_FB30_Pos (30U)
4882 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
4883 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
4884 #define CAN_F10R1_FB31_Pos (31U)
4885 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
4886 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
4887
4888 /******************* Bit definition for CAN_F11R1 register ******************/
4889 #define CAN_F11R1_FB0_Pos (0U)
4890 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
4891 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
4892 #define CAN_F11R1_FB1_Pos (1U)
4893 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
4894 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
4895 #define CAN_F11R1_FB2_Pos (2U)
4896 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
4897 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
4898 #define CAN_F11R1_FB3_Pos (3U)
4899 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
4900 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
4901 #define CAN_F11R1_FB4_Pos (4U)
4902 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
4903 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
4904 #define CAN_F11R1_FB5_Pos (5U)
4905 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
4906 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
4907 #define CAN_F11R1_FB6_Pos (6U)
4908 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
4909 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
4910 #define CAN_F11R1_FB7_Pos (7U)
4911 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
4912 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
4913 #define CAN_F11R1_FB8_Pos (8U)
4914 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
4915 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
4916 #define CAN_F11R1_FB9_Pos (9U)
4917 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
4918 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
4919 #define CAN_F11R1_FB10_Pos (10U)
4920 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
4921 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
4922 #define CAN_F11R1_FB11_Pos (11U)
4923 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
4924 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
4925 #define CAN_F11R1_FB12_Pos (12U)
4926 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
4927 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
4928 #define CAN_F11R1_FB13_Pos (13U)
4929 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
4930 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
4931 #define CAN_F11R1_FB14_Pos (14U)
4932 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
4933 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
4934 #define CAN_F11R1_FB15_Pos (15U)
4935 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
4936 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
4937 #define CAN_F11R1_FB16_Pos (16U)
4938 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
4939 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
4940 #define CAN_F11R1_FB17_Pos (17U)
4941 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
4942 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
4943 #define CAN_F11R1_FB18_Pos (18U)
4944 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
4945 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
4946 #define CAN_F11R1_FB19_Pos (19U)
4947 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
4948 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
4949 #define CAN_F11R1_FB20_Pos (20U)
4950 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
4951 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
4952 #define CAN_F11R1_FB21_Pos (21U)
4953 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
4954 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
4955 #define CAN_F11R1_FB22_Pos (22U)
4956 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
4957 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
4958 #define CAN_F11R1_FB23_Pos (23U)
4959 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
4960 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
4961 #define CAN_F11R1_FB24_Pos (24U)
4962 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
4963 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
4964 #define CAN_F11R1_FB25_Pos (25U)
4965 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
4966 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
4967 #define CAN_F11R1_FB26_Pos (26U)
4968 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
4969 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
4970 #define CAN_F11R1_FB27_Pos (27U)
4971 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
4972 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
4973 #define CAN_F11R1_FB28_Pos (28U)
4974 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
4975 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
4976 #define CAN_F11R1_FB29_Pos (29U)
4977 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
4978 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
4979 #define CAN_F11R1_FB30_Pos (30U)
4980 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
4981 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
4982 #define CAN_F11R1_FB31_Pos (31U)
4983 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
4984 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
4985
4986 /******************* Bit definition for CAN_F12R1 register ******************/
4987 #define CAN_F12R1_FB0_Pos (0U)
4988 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
4989 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
4990 #define CAN_F12R1_FB1_Pos (1U)
4991 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
4992 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
4993 #define CAN_F12R1_FB2_Pos (2U)
4994 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
4995 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
4996 #define CAN_F12R1_FB3_Pos (3U)
4997 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
4998 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
4999 #define CAN_F12R1_FB4_Pos (4U)
5000 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
5001 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
5002 #define CAN_F12R1_FB5_Pos (5U)
5003 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
5004 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
5005 #define CAN_F12R1_FB6_Pos (6U)
5006 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
5007 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
5008 #define CAN_F12R1_FB7_Pos (7U)
5009 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
5010 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
5011 #define CAN_F12R1_FB8_Pos (8U)
5012 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
5013 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
5014 #define CAN_F12R1_FB9_Pos (9U)
5015 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
5016 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
5017 #define CAN_F12R1_FB10_Pos (10U)
5018 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
5019 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
5020 #define CAN_F12R1_FB11_Pos (11U)
5021 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
5022 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
5023 #define CAN_F12R1_FB12_Pos (12U)
5024 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
5025 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
5026 #define CAN_F12R1_FB13_Pos (13U)
5027 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
5028 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
5029 #define CAN_F12R1_FB14_Pos (14U)
5030 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
5031 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
5032 #define CAN_F12R1_FB15_Pos (15U)
5033 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
5034 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
5035 #define CAN_F12R1_FB16_Pos (16U)
5036 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
5037 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
5038 #define CAN_F12R1_FB17_Pos (17U)
5039 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
5040 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
5041 #define CAN_F12R1_FB18_Pos (18U)
5042 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
5043 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
5044 #define CAN_F12R1_FB19_Pos (19U)
5045 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
5046 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
5047 #define CAN_F12R1_FB20_Pos (20U)
5048 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
5049 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
5050 #define CAN_F12R1_FB21_Pos (21U)
5051 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
5052 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
5053 #define CAN_F12R1_FB22_Pos (22U)
5054 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
5055 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
5056 #define CAN_F12R1_FB23_Pos (23U)
5057 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
5058 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
5059 #define CAN_F12R1_FB24_Pos (24U)
5060 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
5061 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
5062 #define CAN_F12R1_FB25_Pos (25U)
5063 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
5064 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
5065 #define CAN_F12R1_FB26_Pos (26U)
5066 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
5067 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
5068 #define CAN_F12R1_FB27_Pos (27U)
5069 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
5070 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
5071 #define CAN_F12R1_FB28_Pos (28U)
5072 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
5073 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
5074 #define CAN_F12R1_FB29_Pos (29U)
5075 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
5076 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
5077 #define CAN_F12R1_FB30_Pos (30U)
5078 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
5079 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
5080 #define CAN_F12R1_FB31_Pos (31U)
5081 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
5082 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
5083
5084 /******************* Bit definition for CAN_F13R1 register ******************/
5085 #define CAN_F13R1_FB0_Pos (0U)
5086 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
5087 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
5088 #define CAN_F13R1_FB1_Pos (1U)
5089 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
5090 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
5091 #define CAN_F13R1_FB2_Pos (2U)
5092 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
5093 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
5094 #define CAN_F13R1_FB3_Pos (3U)
5095 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
5096 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
5097 #define CAN_F13R1_FB4_Pos (4U)
5098 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
5099 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
5100 #define CAN_F13R1_FB5_Pos (5U)
5101 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
5102 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
5103 #define CAN_F13R1_FB6_Pos (6U)
5104 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
5105 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
5106 #define CAN_F13R1_FB7_Pos (7U)
5107 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
5108 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
5109 #define CAN_F13R1_FB8_Pos (8U)
5110 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
5111 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
5112 #define CAN_F13R1_FB9_Pos (9U)
5113 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
5114 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
5115 #define CAN_F13R1_FB10_Pos (10U)
5116 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
5117 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
5118 #define CAN_F13R1_FB11_Pos (11U)
5119 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
5120 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
5121 #define CAN_F13R1_FB12_Pos (12U)
5122 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
5123 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
5124 #define CAN_F13R1_FB13_Pos (13U)
5125 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
5126 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
5127 #define CAN_F13R1_FB14_Pos (14U)
5128 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
5129 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
5130 #define CAN_F13R1_FB15_Pos (15U)
5131 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
5132 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
5133 #define CAN_F13R1_FB16_Pos (16U)
5134 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
5135 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
5136 #define CAN_F13R1_FB17_Pos (17U)
5137 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
5138 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
5139 #define CAN_F13R1_FB18_Pos (18U)
5140 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
5141 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
5142 #define CAN_F13R1_FB19_Pos (19U)
5143 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
5144 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
5145 #define CAN_F13R1_FB20_Pos (20U)
5146 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
5147 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
5148 #define CAN_F13R1_FB21_Pos (21U)
5149 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
5150 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
5151 #define CAN_F13R1_FB22_Pos (22U)
5152 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
5153 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
5154 #define CAN_F13R1_FB23_Pos (23U)
5155 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
5156 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
5157 #define CAN_F13R1_FB24_Pos (24U)
5158 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
5159 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
5160 #define CAN_F13R1_FB25_Pos (25U)
5161 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
5162 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
5163 #define CAN_F13R1_FB26_Pos (26U)
5164 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
5165 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
5166 #define CAN_F13R1_FB27_Pos (27U)
5167 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
5168 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
5169 #define CAN_F13R1_FB28_Pos (28U)
5170 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
5171 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
5172 #define CAN_F13R1_FB29_Pos (29U)
5173 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
5174 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
5175 #define CAN_F13R1_FB30_Pos (30U)
5176 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
5177 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
5178 #define CAN_F13R1_FB31_Pos (31U)
5179 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
5180 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
5181
5182 /******************* Bit definition for CAN_F0R2 register *******************/
5183 #define CAN_F0R2_FB0_Pos (0U)
5184 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
5185 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
5186 #define CAN_F0R2_FB1_Pos (1U)
5187 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
5188 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
5189 #define CAN_F0R2_FB2_Pos (2U)
5190 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
5191 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
5192 #define CAN_F0R2_FB3_Pos (3U)
5193 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
5194 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
5195 #define CAN_F0R2_FB4_Pos (4U)
5196 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
5197 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
5198 #define CAN_F0R2_FB5_Pos (5U)
5199 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
5200 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
5201 #define CAN_F0R2_FB6_Pos (6U)
5202 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
5203 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
5204 #define CAN_F0R2_FB7_Pos (7U)
5205 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
5206 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
5207 #define CAN_F0R2_FB8_Pos (8U)
5208 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
5209 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
5210 #define CAN_F0R2_FB9_Pos (9U)
5211 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
5212 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
5213 #define CAN_F0R2_FB10_Pos (10U)
5214 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
5215 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
5216 #define CAN_F0R2_FB11_Pos (11U)
5217 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
5218 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
5219 #define CAN_F0R2_FB12_Pos (12U)
5220 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
5221 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
5222 #define CAN_F0R2_FB13_Pos (13U)
5223 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
5224 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
5225 #define CAN_F0R2_FB14_Pos (14U)
5226 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
5227 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
5228 #define CAN_F0R2_FB15_Pos (15U)
5229 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
5230 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
5231 #define CAN_F0R2_FB16_Pos (16U)
5232 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
5233 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
5234 #define CAN_F0R2_FB17_Pos (17U)
5235 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
5236 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
5237 #define CAN_F0R2_FB18_Pos (18U)
5238 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
5239 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
5240 #define CAN_F0R2_FB19_Pos (19U)
5241 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
5242 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
5243 #define CAN_F0R2_FB20_Pos (20U)
5244 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
5245 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
5246 #define CAN_F0R2_FB21_Pos (21U)
5247 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
5248 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
5249 #define CAN_F0R2_FB22_Pos (22U)
5250 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
5251 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
5252 #define CAN_F0R2_FB23_Pos (23U)
5253 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
5254 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
5255 #define CAN_F0R2_FB24_Pos (24U)
5256 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
5257 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
5258 #define CAN_F0R2_FB25_Pos (25U)
5259 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
5260 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
5261 #define CAN_F0R2_FB26_Pos (26U)
5262 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
5263 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
5264 #define CAN_F0R2_FB27_Pos (27U)
5265 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
5266 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
5267 #define CAN_F0R2_FB28_Pos (28U)
5268 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
5269 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
5270 #define CAN_F0R2_FB29_Pos (29U)
5271 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
5272 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
5273 #define CAN_F0R2_FB30_Pos (30U)
5274 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
5275 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
5276 #define CAN_F0R2_FB31_Pos (31U)
5277 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
5278 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
5279
5280 /******************* Bit definition for CAN_F1R2 register *******************/
5281 #define CAN_F1R2_FB0_Pos (0U)
5282 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
5283 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
5284 #define CAN_F1R2_FB1_Pos (1U)
5285 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
5286 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
5287 #define CAN_F1R2_FB2_Pos (2U)
5288 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
5289 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
5290 #define CAN_F1R2_FB3_Pos (3U)
5291 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
5292 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
5293 #define CAN_F1R2_FB4_Pos (4U)
5294 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
5295 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
5296 #define CAN_F1R2_FB5_Pos (5U)
5297 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
5298 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
5299 #define CAN_F1R2_FB6_Pos (6U)
5300 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
5301 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
5302 #define CAN_F1R2_FB7_Pos (7U)
5303 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
5304 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
5305 #define CAN_F1R2_FB8_Pos (8U)
5306 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
5307 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
5308 #define CAN_F1R2_FB9_Pos (9U)
5309 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
5310 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
5311 #define CAN_F1R2_FB10_Pos (10U)
5312 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
5313 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
5314 #define CAN_F1R2_FB11_Pos (11U)
5315 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
5316 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
5317 #define CAN_F1R2_FB12_Pos (12U)
5318 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
5319 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
5320 #define CAN_F1R2_FB13_Pos (13U)
5321 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
5322 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
5323 #define CAN_F1R2_FB14_Pos (14U)
5324 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
5325 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
5326 #define CAN_F1R2_FB15_Pos (15U)
5327 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
5328 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
5329 #define CAN_F1R2_FB16_Pos (16U)
5330 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
5331 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
5332 #define CAN_F1R2_FB17_Pos (17U)
5333 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
5334 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
5335 #define CAN_F1R2_FB18_Pos (18U)
5336 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
5337 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
5338 #define CAN_F1R2_FB19_Pos (19U)
5339 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
5340 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
5341 #define CAN_F1R2_FB20_Pos (20U)
5342 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
5343 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
5344 #define CAN_F1R2_FB21_Pos (21U)
5345 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
5346 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
5347 #define CAN_F1R2_FB22_Pos (22U)
5348 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
5349 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
5350 #define CAN_F1R2_FB23_Pos (23U)
5351 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
5352 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
5353 #define CAN_F1R2_FB24_Pos (24U)
5354 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
5355 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
5356 #define CAN_F1R2_FB25_Pos (25U)
5357 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
5358 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
5359 #define CAN_F1R2_FB26_Pos (26U)
5360 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
5361 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
5362 #define CAN_F1R2_FB27_Pos (27U)
5363 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
5364 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
5365 #define CAN_F1R2_FB28_Pos (28U)
5366 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
5367 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
5368 #define CAN_F1R2_FB29_Pos (29U)
5369 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
5370 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
5371 #define CAN_F1R2_FB30_Pos (30U)
5372 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
5373 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
5374 #define CAN_F1R2_FB31_Pos (31U)
5375 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
5376 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
5377
5378 /******************* Bit definition for CAN_F2R2 register *******************/
5379 #define CAN_F2R2_FB0_Pos (0U)
5380 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
5381 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
5382 #define CAN_F2R2_FB1_Pos (1U)
5383 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
5384 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
5385 #define CAN_F2R2_FB2_Pos (2U)
5386 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
5387 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
5388 #define CAN_F2R2_FB3_Pos (3U)
5389 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
5390 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
5391 #define CAN_F2R2_FB4_Pos (4U)
5392 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
5393 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
5394 #define CAN_F2R2_FB5_Pos (5U)
5395 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
5396 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
5397 #define CAN_F2R2_FB6_Pos (6U)
5398 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
5399 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
5400 #define CAN_F2R2_FB7_Pos (7U)
5401 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
5402 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
5403 #define CAN_F2R2_FB8_Pos (8U)
5404 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
5405 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
5406 #define CAN_F2R2_FB9_Pos (9U)
5407 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
5408 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
5409 #define CAN_F2R2_FB10_Pos (10U)
5410 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
5411 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
5412 #define CAN_F2R2_FB11_Pos (11U)
5413 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
5414 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
5415 #define CAN_F2R2_FB12_Pos (12U)
5416 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
5417 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
5418 #define CAN_F2R2_FB13_Pos (13U)
5419 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
5420 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
5421 #define CAN_F2R2_FB14_Pos (14U)
5422 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
5423 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
5424 #define CAN_F2R2_FB15_Pos (15U)
5425 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
5426 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
5427 #define CAN_F2R2_FB16_Pos (16U)
5428 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
5429 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
5430 #define CAN_F2R2_FB17_Pos (17U)
5431 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
5432 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
5433 #define CAN_F2R2_FB18_Pos (18U)
5434 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
5435 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
5436 #define CAN_F2R2_FB19_Pos (19U)
5437 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
5438 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
5439 #define CAN_F2R2_FB20_Pos (20U)
5440 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
5441 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
5442 #define CAN_F2R2_FB21_Pos (21U)
5443 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
5444 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
5445 #define CAN_F2R2_FB22_Pos (22U)
5446 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
5447 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
5448 #define CAN_F2R2_FB23_Pos (23U)
5449 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
5450 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
5451 #define CAN_F2R2_FB24_Pos (24U)
5452 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
5453 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
5454 #define CAN_F2R2_FB25_Pos (25U)
5455 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
5456 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
5457 #define CAN_F2R2_FB26_Pos (26U)
5458 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
5459 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
5460 #define CAN_F2R2_FB27_Pos (27U)
5461 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
5462 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
5463 #define CAN_F2R2_FB28_Pos (28U)
5464 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
5465 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
5466 #define CAN_F2R2_FB29_Pos (29U)
5467 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
5468 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
5469 #define CAN_F2R2_FB30_Pos (30U)
5470 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
5471 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
5472 #define CAN_F2R2_FB31_Pos (31U)
5473 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
5474 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
5475
5476 /******************* Bit definition for CAN_F3R2 register *******************/
5477 #define CAN_F3R2_FB0_Pos (0U)
5478 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
5479 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
5480 #define CAN_F3R2_FB1_Pos (1U)
5481 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
5482 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
5483 #define CAN_F3R2_FB2_Pos (2U)
5484 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
5485 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
5486 #define CAN_F3R2_FB3_Pos (3U)
5487 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
5488 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
5489 #define CAN_F3R2_FB4_Pos (4U)
5490 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
5491 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
5492 #define CAN_F3R2_FB5_Pos (5U)
5493 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
5494 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
5495 #define CAN_F3R2_FB6_Pos (6U)
5496 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
5497 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
5498 #define CAN_F3R2_FB7_Pos (7U)
5499 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
5500 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
5501 #define CAN_F3R2_FB8_Pos (8U)
5502 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
5503 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
5504 #define CAN_F3R2_FB9_Pos (9U)
5505 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
5506 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
5507 #define CAN_F3R2_FB10_Pos (10U)
5508 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
5509 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
5510 #define CAN_F3R2_FB11_Pos (11U)
5511 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
5512 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
5513 #define CAN_F3R2_FB12_Pos (12U)
5514 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
5515 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
5516 #define CAN_F3R2_FB13_Pos (13U)
5517 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
5518 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
5519 #define CAN_F3R2_FB14_Pos (14U)
5520 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
5521 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
5522 #define CAN_F3R2_FB15_Pos (15U)
5523 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
5524 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
5525 #define CAN_F3R2_FB16_Pos (16U)
5526 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
5527 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
5528 #define CAN_F3R2_FB17_Pos (17U)
5529 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
5530 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
5531 #define CAN_F3R2_FB18_Pos (18U)
5532 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
5533 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
5534 #define CAN_F3R2_FB19_Pos (19U)
5535 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
5536 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
5537 #define CAN_F3R2_FB20_Pos (20U)
5538 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
5539 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
5540 #define CAN_F3R2_FB21_Pos (21U)
5541 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
5542 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
5543 #define CAN_F3R2_FB22_Pos (22U)
5544 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
5545 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
5546 #define CAN_F3R2_FB23_Pos (23U)
5547 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
5548 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
5549 #define CAN_F3R2_FB24_Pos (24U)
5550 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
5551 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
5552 #define CAN_F3R2_FB25_Pos (25U)
5553 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
5554 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
5555 #define CAN_F3R2_FB26_Pos (26U)
5556 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
5557 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
5558 #define CAN_F3R2_FB27_Pos (27U)
5559 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
5560 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
5561 #define CAN_F3R2_FB28_Pos (28U)
5562 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
5563 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
5564 #define CAN_F3R2_FB29_Pos (29U)
5565 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
5566 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
5567 #define CAN_F3R2_FB30_Pos (30U)
5568 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
5569 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
5570 #define CAN_F3R2_FB31_Pos (31U)
5571 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
5572 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
5573
5574 /******************* Bit definition for CAN_F4R2 register *******************/
5575 #define CAN_F4R2_FB0_Pos (0U)
5576 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
5577 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
5578 #define CAN_F4R2_FB1_Pos (1U)
5579 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
5580 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
5581 #define CAN_F4R2_FB2_Pos (2U)
5582 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
5583 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
5584 #define CAN_F4R2_FB3_Pos (3U)
5585 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
5586 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
5587 #define CAN_F4R2_FB4_Pos (4U)
5588 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
5589 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
5590 #define CAN_F4R2_FB5_Pos (5U)
5591 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
5592 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
5593 #define CAN_F4R2_FB6_Pos (6U)
5594 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
5595 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
5596 #define CAN_F4R2_FB7_Pos (7U)
5597 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
5598 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
5599 #define CAN_F4R2_FB8_Pos (8U)
5600 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
5601 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
5602 #define CAN_F4R2_FB9_Pos (9U)
5603 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
5604 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
5605 #define CAN_F4R2_FB10_Pos (10U)
5606 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
5607 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
5608 #define CAN_F4R2_FB11_Pos (11U)
5609 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
5610 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
5611 #define CAN_F4R2_FB12_Pos (12U)
5612 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
5613 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
5614 #define CAN_F4R2_FB13_Pos (13U)
5615 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
5616 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
5617 #define CAN_F4R2_FB14_Pos (14U)
5618 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
5619 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
5620 #define CAN_F4R2_FB15_Pos (15U)
5621 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
5622 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
5623 #define CAN_F4R2_FB16_Pos (16U)
5624 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
5625 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
5626 #define CAN_F4R2_FB17_Pos (17U)
5627 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
5628 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
5629 #define CAN_F4R2_FB18_Pos (18U)
5630 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
5631 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
5632 #define CAN_F4R2_FB19_Pos (19U)
5633 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
5634 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
5635 #define CAN_F4R2_FB20_Pos (20U)
5636 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
5637 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
5638 #define CAN_F4R2_FB21_Pos (21U)
5639 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
5640 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
5641 #define CAN_F4R2_FB22_Pos (22U)
5642 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
5643 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
5644 #define CAN_F4R2_FB23_Pos (23U)
5645 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
5646 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
5647 #define CAN_F4R2_FB24_Pos (24U)
5648 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
5649 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
5650 #define CAN_F4R2_FB25_Pos (25U)
5651 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
5652 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
5653 #define CAN_F4R2_FB26_Pos (26U)
5654 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
5655 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
5656 #define CAN_F4R2_FB27_Pos (27U)
5657 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
5658 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
5659 #define CAN_F4R2_FB28_Pos (28U)
5660 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
5661 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
5662 #define CAN_F4R2_FB29_Pos (29U)
5663 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
5664 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
5665 #define CAN_F4R2_FB30_Pos (30U)
5666 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
5667 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
5668 #define CAN_F4R2_FB31_Pos (31U)
5669 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
5670 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
5671
5672 /******************* Bit definition for CAN_F5R2 register *******************/
5673 #define CAN_F5R2_FB0_Pos (0U)
5674 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
5675 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
5676 #define CAN_F5R2_FB1_Pos (1U)
5677 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
5678 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
5679 #define CAN_F5R2_FB2_Pos (2U)
5680 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
5681 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
5682 #define CAN_F5R2_FB3_Pos (3U)
5683 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
5684 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
5685 #define CAN_F5R2_FB4_Pos (4U)
5686 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
5687 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
5688 #define CAN_F5R2_FB5_Pos (5U)
5689 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
5690 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
5691 #define CAN_F5R2_FB6_Pos (6U)
5692 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
5693 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
5694 #define CAN_F5R2_FB7_Pos (7U)
5695 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
5696 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
5697 #define CAN_F5R2_FB8_Pos (8U)
5698 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
5699 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
5700 #define CAN_F5R2_FB9_Pos (9U)
5701 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
5702 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
5703 #define CAN_F5R2_FB10_Pos (10U)
5704 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
5705 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
5706 #define CAN_F5R2_FB11_Pos (11U)
5707 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
5708 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
5709 #define CAN_F5R2_FB12_Pos (12U)
5710 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
5711 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
5712 #define CAN_F5R2_FB13_Pos (13U)
5713 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
5714 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
5715 #define CAN_F5R2_FB14_Pos (14U)
5716 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
5717 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
5718 #define CAN_F5R2_FB15_Pos (15U)
5719 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
5720 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
5721 #define CAN_F5R2_FB16_Pos (16U)
5722 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
5723 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
5724 #define CAN_F5R2_FB17_Pos (17U)
5725 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
5726 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
5727 #define CAN_F5R2_FB18_Pos (18U)
5728 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
5729 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
5730 #define CAN_F5R2_FB19_Pos (19U)
5731 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
5732 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
5733 #define CAN_F5R2_FB20_Pos (20U)
5734 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
5735 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
5736 #define CAN_F5R2_FB21_Pos (21U)
5737 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
5738 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
5739 #define CAN_F5R2_FB22_Pos (22U)
5740 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
5741 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
5742 #define CAN_F5R2_FB23_Pos (23U)
5743 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
5744 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
5745 #define CAN_F5R2_FB24_Pos (24U)
5746 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
5747 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
5748 #define CAN_F5R2_FB25_Pos (25U)
5749 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
5750 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
5751 #define CAN_F5R2_FB26_Pos (26U)
5752 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
5753 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
5754 #define CAN_F5R2_FB27_Pos (27U)
5755 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
5756 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
5757 #define CAN_F5R2_FB28_Pos (28U)
5758 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
5759 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
5760 #define CAN_F5R2_FB29_Pos (29U)
5761 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
5762 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
5763 #define CAN_F5R2_FB30_Pos (30U)
5764 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
5765 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
5766 #define CAN_F5R2_FB31_Pos (31U)
5767 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
5768 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
5769
5770 /******************* Bit definition for CAN_F6R2 register *******************/
5771 #define CAN_F6R2_FB0_Pos (0U)
5772 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
5773 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
5774 #define CAN_F6R2_FB1_Pos (1U)
5775 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
5776 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
5777 #define CAN_F6R2_FB2_Pos (2U)
5778 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
5779 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
5780 #define CAN_F6R2_FB3_Pos (3U)
5781 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
5782 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
5783 #define CAN_F6R2_FB4_Pos (4U)
5784 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
5785 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
5786 #define CAN_F6R2_FB5_Pos (5U)
5787 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
5788 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
5789 #define CAN_F6R2_FB6_Pos (6U)
5790 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
5791 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
5792 #define CAN_F6R2_FB7_Pos (7U)
5793 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
5794 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
5795 #define CAN_F6R2_FB8_Pos (8U)
5796 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
5797 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
5798 #define CAN_F6R2_FB9_Pos (9U)
5799 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
5800 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
5801 #define CAN_F6R2_FB10_Pos (10U)
5802 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
5803 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
5804 #define CAN_F6R2_FB11_Pos (11U)
5805 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
5806 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
5807 #define CAN_F6R2_FB12_Pos (12U)
5808 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
5809 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
5810 #define CAN_F6R2_FB13_Pos (13U)
5811 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
5812 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
5813 #define CAN_F6R2_FB14_Pos (14U)
5814 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
5815 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
5816 #define CAN_F6R2_FB15_Pos (15U)
5817 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
5818 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
5819 #define CAN_F6R2_FB16_Pos (16U)
5820 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
5821 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
5822 #define CAN_F6R2_FB17_Pos (17U)
5823 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
5824 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
5825 #define CAN_F6R2_FB18_Pos (18U)
5826 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
5827 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
5828 #define CAN_F6R2_FB19_Pos (19U)
5829 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
5830 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
5831 #define CAN_F6R2_FB20_Pos (20U)
5832 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
5833 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
5834 #define CAN_F6R2_FB21_Pos (21U)
5835 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
5836 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
5837 #define CAN_F6R2_FB22_Pos (22U)
5838 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
5839 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
5840 #define CAN_F6R2_FB23_Pos (23U)
5841 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
5842 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
5843 #define CAN_F6R2_FB24_Pos (24U)
5844 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
5845 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
5846 #define CAN_F6R2_FB25_Pos (25U)
5847 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
5848 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
5849 #define CAN_F6R2_FB26_Pos (26U)
5850 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
5851 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
5852 #define CAN_F6R2_FB27_Pos (27U)
5853 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
5854 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
5855 #define CAN_F6R2_FB28_Pos (28U)
5856 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
5857 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
5858 #define CAN_F6R2_FB29_Pos (29U)
5859 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
5860 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
5861 #define CAN_F6R2_FB30_Pos (30U)
5862 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
5863 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
5864 #define CAN_F6R2_FB31_Pos (31U)
5865 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
5866 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
5867
5868 /******************* Bit definition for CAN_F7R2 register *******************/
5869 #define CAN_F7R2_FB0_Pos (0U)
5870 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
5871 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
5872 #define CAN_F7R2_FB1_Pos (1U)
5873 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
5874 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
5875 #define CAN_F7R2_FB2_Pos (2U)
5876 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
5877 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
5878 #define CAN_F7R2_FB3_Pos (3U)
5879 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
5880 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
5881 #define CAN_F7R2_FB4_Pos (4U)
5882 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
5883 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
5884 #define CAN_F7R2_FB5_Pos (5U)
5885 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
5886 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
5887 #define CAN_F7R2_FB6_Pos (6U)
5888 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
5889 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
5890 #define CAN_F7R2_FB7_Pos (7U)
5891 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
5892 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
5893 #define CAN_F7R2_FB8_Pos (8U)
5894 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
5895 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
5896 #define CAN_F7R2_FB9_Pos (9U)
5897 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
5898 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
5899 #define CAN_F7R2_FB10_Pos (10U)
5900 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
5901 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
5902 #define CAN_F7R2_FB11_Pos (11U)
5903 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
5904 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
5905 #define CAN_F7R2_FB12_Pos (12U)
5906 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
5907 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
5908 #define CAN_F7R2_FB13_Pos (13U)
5909 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
5910 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
5911 #define CAN_F7R2_FB14_Pos (14U)
5912 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
5913 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
5914 #define CAN_F7R2_FB15_Pos (15U)
5915 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
5916 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
5917 #define CAN_F7R2_FB16_Pos (16U)
5918 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
5919 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
5920 #define CAN_F7R2_FB17_Pos (17U)
5921 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
5922 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
5923 #define CAN_F7R2_FB18_Pos (18U)
5924 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
5925 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
5926 #define CAN_F7R2_FB19_Pos (19U)
5927 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
5928 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
5929 #define CAN_F7R2_FB20_Pos (20U)
5930 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
5931 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
5932 #define CAN_F7R2_FB21_Pos (21U)
5933 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
5934 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
5935 #define CAN_F7R2_FB22_Pos (22U)
5936 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
5937 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
5938 #define CAN_F7R2_FB23_Pos (23U)
5939 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
5940 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
5941 #define CAN_F7R2_FB24_Pos (24U)
5942 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
5943 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
5944 #define CAN_F7R2_FB25_Pos (25U)
5945 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
5946 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
5947 #define CAN_F7R2_FB26_Pos (26U)
5948 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
5949 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
5950 #define CAN_F7R2_FB27_Pos (27U)
5951 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
5952 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
5953 #define CAN_F7R2_FB28_Pos (28U)
5954 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
5955 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
5956 #define CAN_F7R2_FB29_Pos (29U)
5957 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
5958 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
5959 #define CAN_F7R2_FB30_Pos (30U)
5960 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
5961 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
5962 #define CAN_F7R2_FB31_Pos (31U)
5963 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
5964 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
5965
5966 /******************* Bit definition for CAN_F8R2 register *******************/
5967 #define CAN_F8R2_FB0_Pos (0U)
5968 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
5969 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
5970 #define CAN_F8R2_FB1_Pos (1U)
5971 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
5972 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
5973 #define CAN_F8R2_FB2_Pos (2U)
5974 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
5975 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
5976 #define CAN_F8R2_FB3_Pos (3U)
5977 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
5978 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
5979 #define CAN_F8R2_FB4_Pos (4U)
5980 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
5981 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
5982 #define CAN_F8R2_FB5_Pos (5U)
5983 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
5984 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
5985 #define CAN_F8R2_FB6_Pos (6U)
5986 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
5987 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
5988 #define CAN_F8R2_FB7_Pos (7U)
5989 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
5990 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
5991 #define CAN_F8R2_FB8_Pos (8U)
5992 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
5993 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
5994 #define CAN_F8R2_FB9_Pos (9U)
5995 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
5996 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
5997 #define CAN_F8R2_FB10_Pos (10U)
5998 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
5999 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
6000 #define CAN_F8R2_FB11_Pos (11U)
6001 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
6002 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
6003 #define CAN_F8R2_FB12_Pos (12U)
6004 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
6005 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
6006 #define CAN_F8R2_FB13_Pos (13U)
6007 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
6008 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
6009 #define CAN_F8R2_FB14_Pos (14U)
6010 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
6011 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
6012 #define CAN_F8R2_FB15_Pos (15U)
6013 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
6014 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
6015 #define CAN_F8R2_FB16_Pos (16U)
6016 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
6017 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
6018 #define CAN_F8R2_FB17_Pos (17U)
6019 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
6020 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
6021 #define CAN_F8R2_FB18_Pos (18U)
6022 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
6023 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
6024 #define CAN_F8R2_FB19_Pos (19U)
6025 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
6026 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
6027 #define CAN_F8R2_FB20_Pos (20U)
6028 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
6029 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
6030 #define CAN_F8R2_FB21_Pos (21U)
6031 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
6032 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
6033 #define CAN_F8R2_FB22_Pos (22U)
6034 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
6035 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
6036 #define CAN_F8R2_FB23_Pos (23U)
6037 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
6038 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
6039 #define CAN_F8R2_FB24_Pos (24U)
6040 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
6041 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
6042 #define CAN_F8R2_FB25_Pos (25U)
6043 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
6044 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
6045 #define CAN_F8R2_FB26_Pos (26U)
6046 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
6047 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
6048 #define CAN_F8R2_FB27_Pos (27U)
6049 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
6050 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
6051 #define CAN_F8R2_FB28_Pos (28U)
6052 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
6053 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
6054 #define CAN_F8R2_FB29_Pos (29U)
6055 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
6056 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
6057 #define CAN_F8R2_FB30_Pos (30U)
6058 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
6059 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
6060 #define CAN_F8R2_FB31_Pos (31U)
6061 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
6062 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
6063
6064 /******************* Bit definition for CAN_F9R2 register *******************/
6065 #define CAN_F9R2_FB0_Pos (0U)
6066 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
6067 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
6068 #define CAN_F9R2_FB1_Pos (1U)
6069 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
6070 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
6071 #define CAN_F9R2_FB2_Pos (2U)
6072 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
6073 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
6074 #define CAN_F9R2_FB3_Pos (3U)
6075 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
6076 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
6077 #define CAN_F9R2_FB4_Pos (4U)
6078 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
6079 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
6080 #define CAN_F9R2_FB5_Pos (5U)
6081 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
6082 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
6083 #define CAN_F9R2_FB6_Pos (6U)
6084 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
6085 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
6086 #define CAN_F9R2_FB7_Pos (7U)
6087 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
6088 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
6089 #define CAN_F9R2_FB8_Pos (8U)
6090 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
6091 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
6092 #define CAN_F9R2_FB9_Pos (9U)
6093 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
6094 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
6095 #define CAN_F9R2_FB10_Pos (10U)
6096 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
6097 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
6098 #define CAN_F9R2_FB11_Pos (11U)
6099 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
6100 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
6101 #define CAN_F9R2_FB12_Pos (12U)
6102 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
6103 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
6104 #define CAN_F9R2_FB13_Pos (13U)
6105 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
6106 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
6107 #define CAN_F9R2_FB14_Pos (14U)
6108 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
6109 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
6110 #define CAN_F9R2_FB15_Pos (15U)
6111 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
6112 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
6113 #define CAN_F9R2_FB16_Pos (16U)
6114 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
6115 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
6116 #define CAN_F9R2_FB17_Pos (17U)
6117 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
6118 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
6119 #define CAN_F9R2_FB18_Pos (18U)
6120 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
6121 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
6122 #define CAN_F9R2_FB19_Pos (19U)
6123 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
6124 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
6125 #define CAN_F9R2_FB20_Pos (20U)
6126 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
6127 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
6128 #define CAN_F9R2_FB21_Pos (21U)
6129 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
6130 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
6131 #define CAN_F9R2_FB22_Pos (22U)
6132 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
6133 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
6134 #define CAN_F9R2_FB23_Pos (23U)
6135 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
6136 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
6137 #define CAN_F9R2_FB24_Pos (24U)
6138 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
6139 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
6140 #define CAN_F9R2_FB25_Pos (25U)
6141 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
6142 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
6143 #define CAN_F9R2_FB26_Pos (26U)
6144 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
6145 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
6146 #define CAN_F9R2_FB27_Pos (27U)
6147 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
6148 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
6149 #define CAN_F9R2_FB28_Pos (28U)
6150 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
6151 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
6152 #define CAN_F9R2_FB29_Pos (29U)
6153 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
6154 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
6155 #define CAN_F9R2_FB30_Pos (30U)
6156 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
6157 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
6158 #define CAN_F9R2_FB31_Pos (31U)
6159 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
6160 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
6161
6162 /******************* Bit definition for CAN_F10R2 register ******************/
6163 #define CAN_F10R2_FB0_Pos (0U)
6164 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
6165 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
6166 #define CAN_F10R2_FB1_Pos (1U)
6167 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
6168 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
6169 #define CAN_F10R2_FB2_Pos (2U)
6170 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
6171 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
6172 #define CAN_F10R2_FB3_Pos (3U)
6173 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
6174 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
6175 #define CAN_F10R2_FB4_Pos (4U)
6176 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
6177 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
6178 #define CAN_F10R2_FB5_Pos (5U)
6179 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
6180 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
6181 #define CAN_F10R2_FB6_Pos (6U)
6182 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
6183 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
6184 #define CAN_F10R2_FB7_Pos (7U)
6185 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
6186 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
6187 #define CAN_F10R2_FB8_Pos (8U)
6188 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
6189 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
6190 #define CAN_F10R2_FB9_Pos (9U)
6191 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
6192 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
6193 #define CAN_F10R2_FB10_Pos (10U)
6194 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
6195 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
6196 #define CAN_F10R2_FB11_Pos (11U)
6197 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
6198 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
6199 #define CAN_F10R2_FB12_Pos (12U)
6200 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
6201 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
6202 #define CAN_F10R2_FB13_Pos (13U)
6203 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
6204 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
6205 #define CAN_F10R2_FB14_Pos (14U)
6206 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
6207 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
6208 #define CAN_F10R2_FB15_Pos (15U)
6209 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
6210 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
6211 #define CAN_F10R2_FB16_Pos (16U)
6212 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
6213 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
6214 #define CAN_F10R2_FB17_Pos (17U)
6215 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
6216 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
6217 #define CAN_F10R2_FB18_Pos (18U)
6218 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
6219 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
6220 #define CAN_F10R2_FB19_Pos (19U)
6221 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
6222 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
6223 #define CAN_F10R2_FB20_Pos (20U)
6224 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
6225 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
6226 #define CAN_F10R2_FB21_Pos (21U)
6227 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
6228 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
6229 #define CAN_F10R2_FB22_Pos (22U)
6230 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
6231 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
6232 #define CAN_F10R2_FB23_Pos (23U)
6233 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
6234 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
6235 #define CAN_F10R2_FB24_Pos (24U)
6236 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
6237 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
6238 #define CAN_F10R2_FB25_Pos (25U)
6239 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
6240 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
6241 #define CAN_F10R2_FB26_Pos (26U)
6242 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
6243 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
6244 #define CAN_F10R2_FB27_Pos (27U)
6245 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
6246 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
6247 #define CAN_F10R2_FB28_Pos (28U)
6248 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
6249 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
6250 #define CAN_F10R2_FB29_Pos (29U)
6251 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
6252 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
6253 #define CAN_F10R2_FB30_Pos (30U)
6254 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
6255 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
6256 #define CAN_F10R2_FB31_Pos (31U)
6257 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
6258 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
6259
6260 /******************* Bit definition for CAN_F11R2 register ******************/
6261 #define CAN_F11R2_FB0_Pos (0U)
6262 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
6263 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
6264 #define CAN_F11R2_FB1_Pos (1U)
6265 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
6266 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
6267 #define CAN_F11R2_FB2_Pos (2U)
6268 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
6269 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
6270 #define CAN_F11R2_FB3_Pos (3U)
6271 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
6272 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
6273 #define CAN_F11R2_FB4_Pos (4U)
6274 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
6275 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
6276 #define CAN_F11R2_FB5_Pos (5U)
6277 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
6278 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
6279 #define CAN_F11R2_FB6_Pos (6U)
6280 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
6281 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
6282 #define CAN_F11R2_FB7_Pos (7U)
6283 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
6284 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
6285 #define CAN_F11R2_FB8_Pos (8U)
6286 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
6287 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
6288 #define CAN_F11R2_FB9_Pos (9U)
6289 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
6290 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
6291 #define CAN_F11R2_FB10_Pos (10U)
6292 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
6293 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
6294 #define CAN_F11R2_FB11_Pos (11U)
6295 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
6296 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
6297 #define CAN_F11R2_FB12_Pos (12U)
6298 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
6299 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
6300 #define CAN_F11R2_FB13_Pos (13U)
6301 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
6302 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
6303 #define CAN_F11R2_FB14_Pos (14U)
6304 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
6305 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
6306 #define CAN_F11R2_FB15_Pos (15U)
6307 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
6308 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
6309 #define CAN_F11R2_FB16_Pos (16U)
6310 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
6311 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
6312 #define CAN_F11R2_FB17_Pos (17U)
6313 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
6314 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
6315 #define CAN_F11R2_FB18_Pos (18U)
6316 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
6317 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
6318 #define CAN_F11R2_FB19_Pos (19U)
6319 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
6320 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
6321 #define CAN_F11R2_FB20_Pos (20U)
6322 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
6323 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
6324 #define CAN_F11R2_FB21_Pos (21U)
6325 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
6326 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
6327 #define CAN_F11R2_FB22_Pos (22U)
6328 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
6329 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
6330 #define CAN_F11R2_FB23_Pos (23U)
6331 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
6332 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
6333 #define CAN_F11R2_FB24_Pos (24U)
6334 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
6335 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
6336 #define CAN_F11R2_FB25_Pos (25U)
6337 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
6338 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
6339 #define CAN_F11R2_FB26_Pos (26U)
6340 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
6341 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
6342 #define CAN_F11R2_FB27_Pos (27U)
6343 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
6344 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
6345 #define CAN_F11R2_FB28_Pos (28U)
6346 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
6347 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
6348 #define CAN_F11R2_FB29_Pos (29U)
6349 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
6350 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
6351 #define CAN_F11R2_FB30_Pos (30U)
6352 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
6353 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
6354 #define CAN_F11R2_FB31_Pos (31U)
6355 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
6356 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
6357
6358 /******************* Bit definition for CAN_F12R2 register ******************/
6359 #define CAN_F12R2_FB0_Pos (0U)
6360 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
6361 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
6362 #define CAN_F12R2_FB1_Pos (1U)
6363 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
6364 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
6365 #define CAN_F12R2_FB2_Pos (2U)
6366 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
6367 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
6368 #define CAN_F12R2_FB3_Pos (3U)
6369 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
6370 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
6371 #define CAN_F12R2_FB4_Pos (4U)
6372 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
6373 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
6374 #define CAN_F12R2_FB5_Pos (5U)
6375 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
6376 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
6377 #define CAN_F12R2_FB6_Pos (6U)
6378 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
6379 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
6380 #define CAN_F12R2_FB7_Pos (7U)
6381 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
6382 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
6383 #define CAN_F12R2_FB8_Pos (8U)
6384 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
6385 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
6386 #define CAN_F12R2_FB9_Pos (9U)
6387 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
6388 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
6389 #define CAN_F12R2_FB10_Pos (10U)
6390 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
6391 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
6392 #define CAN_F12R2_FB11_Pos (11U)
6393 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
6394 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
6395 #define CAN_F12R2_FB12_Pos (12U)
6396 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
6397 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
6398 #define CAN_F12R2_FB13_Pos (13U)
6399 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
6400 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
6401 #define CAN_F12R2_FB14_Pos (14U)
6402 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
6403 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
6404 #define CAN_F12R2_FB15_Pos (15U)
6405 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
6406 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
6407 #define CAN_F12R2_FB16_Pos (16U)
6408 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
6409 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
6410 #define CAN_F12R2_FB17_Pos (17U)
6411 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
6412 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
6413 #define CAN_F12R2_FB18_Pos (18U)
6414 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
6415 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
6416 #define CAN_F12R2_FB19_Pos (19U)
6417 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
6418 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
6419 #define CAN_F12R2_FB20_Pos (20U)
6420 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
6421 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
6422 #define CAN_F12R2_FB21_Pos (21U)
6423 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
6424 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
6425 #define CAN_F12R2_FB22_Pos (22U)
6426 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
6427 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
6428 #define CAN_F12R2_FB23_Pos (23U)
6429 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
6430 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
6431 #define CAN_F12R2_FB24_Pos (24U)
6432 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
6433 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
6434 #define CAN_F12R2_FB25_Pos (25U)
6435 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
6436 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
6437 #define CAN_F12R2_FB26_Pos (26U)
6438 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
6439 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
6440 #define CAN_F12R2_FB27_Pos (27U)
6441 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
6442 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
6443 #define CAN_F12R2_FB28_Pos (28U)
6444 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
6445 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
6446 #define CAN_F12R2_FB29_Pos (29U)
6447 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
6448 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
6449 #define CAN_F12R2_FB30_Pos (30U)
6450 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
6451 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
6452 #define CAN_F12R2_FB31_Pos (31U)
6453 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
6454 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
6455
6456 /******************* Bit definition for CAN_F13R2 register ******************/
6457 #define CAN_F13R2_FB0_Pos (0U)
6458 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
6459 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
6460 #define CAN_F13R2_FB1_Pos (1U)
6461 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
6462 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
6463 #define CAN_F13R2_FB2_Pos (2U)
6464 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
6465 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
6466 #define CAN_F13R2_FB3_Pos (3U)
6467 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
6468 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
6469 #define CAN_F13R2_FB4_Pos (4U)
6470 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
6471 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
6472 #define CAN_F13R2_FB5_Pos (5U)
6473 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
6474 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
6475 #define CAN_F13R2_FB6_Pos (6U)
6476 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
6477 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
6478 #define CAN_F13R2_FB7_Pos (7U)
6479 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
6480 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
6481 #define CAN_F13R2_FB8_Pos (8U)
6482 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
6483 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
6484 #define CAN_F13R2_FB9_Pos (9U)
6485 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
6486 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
6487 #define CAN_F13R2_FB10_Pos (10U)
6488 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
6489 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
6490 #define CAN_F13R2_FB11_Pos (11U)
6491 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
6492 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
6493 #define CAN_F13R2_FB12_Pos (12U)
6494 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
6495 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
6496 #define CAN_F13R2_FB13_Pos (13U)
6497 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
6498 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
6499 #define CAN_F13R2_FB14_Pos (14U)
6500 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
6501 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
6502 #define CAN_F13R2_FB15_Pos (15U)
6503 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
6504 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
6505 #define CAN_F13R2_FB16_Pos (16U)
6506 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
6507 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
6508 #define CAN_F13R2_FB17_Pos (17U)
6509 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
6510 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
6511 #define CAN_F13R2_FB18_Pos (18U)
6512 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
6513 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
6514 #define CAN_F13R2_FB19_Pos (19U)
6515 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
6516 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
6517 #define CAN_F13R2_FB20_Pos (20U)
6518 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
6519 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
6520 #define CAN_F13R2_FB21_Pos (21U)
6521 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
6522 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
6523 #define CAN_F13R2_FB22_Pos (22U)
6524 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
6525 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
6526 #define CAN_F13R2_FB23_Pos (23U)
6527 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
6528 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
6529 #define CAN_F13R2_FB24_Pos (24U)
6530 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
6531 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
6532 #define CAN_F13R2_FB25_Pos (25U)
6533 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
6534 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
6535 #define CAN_F13R2_FB26_Pos (26U)
6536 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
6537 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
6538 #define CAN_F13R2_FB27_Pos (27U)
6539 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
6540 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
6541 #define CAN_F13R2_FB28_Pos (28U)
6542 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
6543 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
6544 #define CAN_F13R2_FB29_Pos (29U)
6545 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
6546 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
6547 #define CAN_F13R2_FB30_Pos (30U)
6548 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
6549 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
6550 #define CAN_F13R2_FB31_Pos (31U)
6551 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
6552 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
6553
6554 /******************************************************************************/
6555 /* */
6556 /* CRC calculation unit (CRC) */
6557 /* */
6558 /******************************************************************************/
6559 /******************* Bit definition for CRC_DR register *********************/
6560 #define CRC_DR_DR_Pos (0U)
6561 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
6562 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
6563
6564 /******************* Bit definition for CRC_IDR register ********************/
6565 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
6566
6567 /******************** Bit definition for CRC_CR register ********************/
6568 #define CRC_CR_RESET_Pos (0U)
6569 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
6570 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
6571 #define CRC_CR_POLYSIZE_Pos (3U)
6572 #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
6573 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
6574 #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
6575 #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
6576 #define CRC_CR_REV_IN_Pos (5U)
6577 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
6578 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
6579 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
6580 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
6581 #define CRC_CR_REV_OUT_Pos (7U)
6582 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
6583 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
6584
6585 /******************* Bit definition for CRC_INIT register *******************/
6586 #define CRC_INIT_INIT_Pos (0U)
6587 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
6588 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
6589
6590 /******************* Bit definition for CRC_POL register ********************/
6591 #define CRC_POL_POL_Pos (0U)
6592 #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
6593 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
6594
6595 /******************************************************************************/
6596 /* */
6597 /* Digital to Analog Converter (DAC) */
6598 /* */
6599 /******************************************************************************/
6600
6601 /*
6602 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
6603 */
6604 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available (may not be available on all DAC instances DACx) */
6605
6606
6607 /******************** Bit definition for DAC_CR register ********************/
6608 #define DAC_CR_EN1_Pos (0U)
6609 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
6610 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
6611 #define DAC_CR_BOFF1_Pos (1U)
6612 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
6613 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
6614 #define DAC_CR_TEN1_Pos (2U)
6615 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
6616 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
6617
6618 #define DAC_CR_TSEL1_Pos (3U)
6619 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
6620 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
6621 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
6622 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
6623 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
6624
6625 #define DAC_CR_WAVE1_Pos (6U)
6626 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
6627 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
6628 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
6629 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
6630
6631 #define DAC_CR_MAMP1_Pos (8U)
6632 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
6633 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
6634 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
6635 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
6636 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
6637 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
6638
6639 #define DAC_CR_DMAEN1_Pos (12U)
6640 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
6641 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
6642 #define DAC_CR_DMAUDRIE1_Pos (13U)
6643 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
6644 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA underrun IT enable */
6645 #define DAC_CR_EN2_Pos (16U)
6646 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
6647 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */
6648 #define DAC_CR_BOFF2_Pos (17U)
6649 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
6650 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */
6651 #define DAC_CR_TEN2_Pos (18U)
6652 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
6653 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */
6654
6655 #define DAC_CR_TSEL2_Pos (19U)
6656 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
6657 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
6658 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
6659 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
6660 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
6661
6662 #define DAC_CR_WAVE2_Pos (22U)
6663 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
6664 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
6665 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
6666 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
6667
6668 #define DAC_CR_MAMP2_Pos (24U)
6669 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
6670 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
6671 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
6672 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
6673 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
6674 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
6675
6676 #define DAC_CR_DMAEN2_Pos (28U)
6677 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
6678 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */
6679 #define DAC_CR_DMAUDRIE2_Pos (29U)
6680 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
6681 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel2 DMA underrun IT enable */
6682
6683 /***************** Bit definition for DAC_SWTRIGR register ******************/
6684 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
6685 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
6686 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
6687 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
6688 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
6689 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */
6690
6691 /***************** Bit definition for DAC_DHR12R1 register ******************/
6692 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
6693 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
6694 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
6695
6696 /***************** Bit definition for DAC_DHR12L1 register ******************/
6697 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
6698 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
6699 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
6700
6701 /****************** Bit definition for DAC_DHR8R1 register ******************/
6702 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
6703 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
6704 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
6705
6706 /***************** Bit definition for DAC_DHR12R2 register ******************/
6707 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
6708 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
6709 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
6710
6711 /***************** Bit definition for DAC_DHR12L2 register ******************/
6712 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
6713 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
6714 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
6715
6716 /****************** Bit definition for DAC_DHR8R2 register ******************/
6717 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
6718 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
6719 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
6720
6721 /***************** Bit definition for DAC_DHR12RD register ******************/
6722 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
6723 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
6724 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
6725 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
6726 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
6727 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
6728
6729 /***************** Bit definition for DAC_DHR12LD register ******************/
6730 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
6731 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
6732 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
6733 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
6734 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
6735 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
6736
6737 /****************** Bit definition for DAC_DHR8RD register ******************/
6738 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
6739 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
6740 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
6741 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
6742 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
6743 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
6744
6745 /******************* Bit definition for DAC_DOR1 register *******************/
6746 #define DAC_DOR1_DACC1DOR_Pos (0U)
6747 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
6748 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */
6749
6750 /******************* Bit definition for DAC_DOR2 register *******************/
6751 #define DAC_DOR2_DACC2DOR_Pos (0U)
6752 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
6753 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */
6754
6755 /******************** Bit definition for DAC_SR register ********************/
6756 #define DAC_SR_DMAUDR1_Pos (13U)
6757 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
6758 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */
6759 #define DAC_SR_DMAUDR2_Pos (29U)
6760 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
6761 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */
6762
6763 /******************************************************************************/
6764 /* */
6765 /* Debug MCU (DBGMCU) */
6766 /* */
6767 /******************************************************************************/
6768 /******************** Bit definition for DBGMCU_IDCODE register *************/
6769 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
6770 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
6771 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
6772 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
6773 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
6774 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
6775
6776 /******************** Bit definition for DBGMCU_CR register *****************/
6777 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
6778 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
6779 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
6780 #define DBGMCU_CR_DBG_STOP_Pos (1U)
6781 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
6782 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
6783 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
6784 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
6785 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
6786 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
6787 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
6788 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
6789
6790 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
6791 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
6792 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
6793 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
6794 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
6795
6796 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
6797 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
6798 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
6799 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
6800 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
6801 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
6802 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
6803 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
6804 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
6805 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
6806 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
6807 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
6808 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
6809 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
6810 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
6811 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
6812 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
6813 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
6814 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
6815 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
6816 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
6817 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
6818 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
6819 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
6820 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
6821 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
6822 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
6823 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
6824 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
6825 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
6826 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
6827 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (30U)
6828 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x40000000 */
6829 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
6830 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos (25U)
6831 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
6832 #define DBGMCU_APB1_FZ_DBG_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk
6833
6834 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
6835 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
6836 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
6837 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
6838 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
6839 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
6840 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
6841 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (2U)
6842 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00000004 */
6843 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk
6844 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (3U)
6845 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00000008 */
6846 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk
6847 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (4U)
6848 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00000010 */
6849 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk
6850 #define DBGMCU_APB2_FZ_DBG_TIM20_STOP_Pos (5U)
6851 #define DBGMCU_APB2_FZ_DBG_TIM20_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM20_STOP_Pos) /*!< 0x00000020 */
6852 #define DBGMCU_APB2_FZ_DBG_TIM20_STOP DBGMCU_APB2_FZ_DBG_TIM20_STOP_Msk
6853
6854 /******************************************************************************/
6855 /* */
6856 /* DMA Controller (DMA) */
6857 /* */
6858 /******************************************************************************/
6859 /******************* Bit definition for DMA_ISR register ********************/
6860 #define DMA_ISR_GIF1_Pos (0U)
6861 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
6862 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
6863 #define DMA_ISR_TCIF1_Pos (1U)
6864 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
6865 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
6866 #define DMA_ISR_HTIF1_Pos (2U)
6867 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
6868 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
6869 #define DMA_ISR_TEIF1_Pos (3U)
6870 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
6871 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
6872 #define DMA_ISR_GIF2_Pos (4U)
6873 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
6874 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
6875 #define DMA_ISR_TCIF2_Pos (5U)
6876 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
6877 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
6878 #define DMA_ISR_HTIF2_Pos (6U)
6879 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
6880 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
6881 #define DMA_ISR_TEIF2_Pos (7U)
6882 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
6883 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
6884 #define DMA_ISR_GIF3_Pos (8U)
6885 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
6886 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
6887 #define DMA_ISR_TCIF3_Pos (9U)
6888 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
6889 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
6890 #define DMA_ISR_HTIF3_Pos (10U)
6891 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
6892 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
6893 #define DMA_ISR_TEIF3_Pos (11U)
6894 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
6895 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
6896 #define DMA_ISR_GIF4_Pos (12U)
6897 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
6898 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
6899 #define DMA_ISR_TCIF4_Pos (13U)
6900 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
6901 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
6902 #define DMA_ISR_HTIF4_Pos (14U)
6903 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
6904 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
6905 #define DMA_ISR_TEIF4_Pos (15U)
6906 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
6907 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
6908 #define DMA_ISR_GIF5_Pos (16U)
6909 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
6910 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
6911 #define DMA_ISR_TCIF5_Pos (17U)
6912 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
6913 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
6914 #define DMA_ISR_HTIF5_Pos (18U)
6915 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
6916 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
6917 #define DMA_ISR_TEIF5_Pos (19U)
6918 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
6919 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
6920 #define DMA_ISR_GIF6_Pos (20U)
6921 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
6922 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
6923 #define DMA_ISR_TCIF6_Pos (21U)
6924 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
6925 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
6926 #define DMA_ISR_HTIF6_Pos (22U)
6927 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
6928 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
6929 #define DMA_ISR_TEIF6_Pos (23U)
6930 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
6931 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
6932 #define DMA_ISR_GIF7_Pos (24U)
6933 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
6934 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
6935 #define DMA_ISR_TCIF7_Pos (25U)
6936 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
6937 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
6938 #define DMA_ISR_HTIF7_Pos (26U)
6939 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
6940 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
6941 #define DMA_ISR_TEIF7_Pos (27U)
6942 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
6943 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
6944
6945 /******************* Bit definition for DMA_IFCR register *******************/
6946 #define DMA_IFCR_CGIF1_Pos (0U)
6947 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
6948 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
6949 #define DMA_IFCR_CTCIF1_Pos (1U)
6950 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
6951 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
6952 #define DMA_IFCR_CHTIF1_Pos (2U)
6953 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
6954 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
6955 #define DMA_IFCR_CTEIF1_Pos (3U)
6956 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
6957 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
6958 #define DMA_IFCR_CGIF2_Pos (4U)
6959 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
6960 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
6961 #define DMA_IFCR_CTCIF2_Pos (5U)
6962 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
6963 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
6964 #define DMA_IFCR_CHTIF2_Pos (6U)
6965 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
6966 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
6967 #define DMA_IFCR_CTEIF2_Pos (7U)
6968 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
6969 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
6970 #define DMA_IFCR_CGIF3_Pos (8U)
6971 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
6972 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
6973 #define DMA_IFCR_CTCIF3_Pos (9U)
6974 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
6975 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
6976 #define DMA_IFCR_CHTIF3_Pos (10U)
6977 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
6978 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
6979 #define DMA_IFCR_CTEIF3_Pos (11U)
6980 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
6981 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
6982 #define DMA_IFCR_CGIF4_Pos (12U)
6983 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
6984 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
6985 #define DMA_IFCR_CTCIF4_Pos (13U)
6986 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
6987 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
6988 #define DMA_IFCR_CHTIF4_Pos (14U)
6989 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
6990 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
6991 #define DMA_IFCR_CTEIF4_Pos (15U)
6992 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
6993 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
6994 #define DMA_IFCR_CGIF5_Pos (16U)
6995 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
6996 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
6997 #define DMA_IFCR_CTCIF5_Pos (17U)
6998 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
6999 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
7000 #define DMA_IFCR_CHTIF5_Pos (18U)
7001 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
7002 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
7003 #define DMA_IFCR_CTEIF5_Pos (19U)
7004 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
7005 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
7006 #define DMA_IFCR_CGIF6_Pos (20U)
7007 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
7008 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
7009 #define DMA_IFCR_CTCIF6_Pos (21U)
7010 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
7011 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
7012 #define DMA_IFCR_CHTIF6_Pos (22U)
7013 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
7014 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
7015 #define DMA_IFCR_CTEIF6_Pos (23U)
7016 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
7017 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
7018 #define DMA_IFCR_CGIF7_Pos (24U)
7019 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
7020 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
7021 #define DMA_IFCR_CTCIF7_Pos (25U)
7022 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
7023 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
7024 #define DMA_IFCR_CHTIF7_Pos (26U)
7025 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
7026 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
7027 #define DMA_IFCR_CTEIF7_Pos (27U)
7028 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
7029 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
7030
7031 /******************* Bit definition for DMA_CCR register ********************/
7032 #define DMA_CCR_EN_Pos (0U)
7033 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
7034 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
7035 #define DMA_CCR_TCIE_Pos (1U)
7036 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
7037 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
7038 #define DMA_CCR_HTIE_Pos (2U)
7039 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
7040 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
7041 #define DMA_CCR_TEIE_Pos (3U)
7042 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
7043 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
7044 #define DMA_CCR_DIR_Pos (4U)
7045 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
7046 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
7047 #define DMA_CCR_CIRC_Pos (5U)
7048 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
7049 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
7050 #define DMA_CCR_PINC_Pos (6U)
7051 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
7052 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
7053 #define DMA_CCR_MINC_Pos (7U)
7054 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
7055 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
7056
7057 #define DMA_CCR_PSIZE_Pos (8U)
7058 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
7059 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
7060 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
7061 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
7062
7063 #define DMA_CCR_MSIZE_Pos (10U)
7064 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
7065 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
7066 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
7067 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
7068
7069 #define DMA_CCR_PL_Pos (12U)
7070 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
7071 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
7072 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
7073 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
7074
7075 #define DMA_CCR_MEM2MEM_Pos (14U)
7076 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
7077 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
7078
7079 /****************** Bit definition for DMA_CNDTR register *******************/
7080 #define DMA_CNDTR_NDT_Pos (0U)
7081 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
7082 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
7083
7084 /****************** Bit definition for DMA_CPAR register ********************/
7085 #define DMA_CPAR_PA_Pos (0U)
7086 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
7087 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
7088
7089 /****************** Bit definition for DMA_CMAR register ********************/
7090 #define DMA_CMAR_MA_Pos (0U)
7091 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
7092 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
7093
7094 /******************************************************************************/
7095 /* */
7096 /* External Interrupt/Event Controller (EXTI) */
7097 /* */
7098 /******************************************************************************/
7099 /******************* Bit definition for EXTI_IMR register *******************/
7100 #define EXTI_IMR_MR0_Pos (0U)
7101 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
7102 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
7103 #define EXTI_IMR_MR1_Pos (1U)
7104 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
7105 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
7106 #define EXTI_IMR_MR2_Pos (2U)
7107 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
7108 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
7109 #define EXTI_IMR_MR3_Pos (3U)
7110 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
7111 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
7112 #define EXTI_IMR_MR4_Pos (4U)
7113 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
7114 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
7115 #define EXTI_IMR_MR5_Pos (5U)
7116 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
7117 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
7118 #define EXTI_IMR_MR6_Pos (6U)
7119 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
7120 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
7121 #define EXTI_IMR_MR7_Pos (7U)
7122 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
7123 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
7124 #define EXTI_IMR_MR8_Pos (8U)
7125 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
7126 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
7127 #define EXTI_IMR_MR9_Pos (9U)
7128 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
7129 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
7130 #define EXTI_IMR_MR10_Pos (10U)
7131 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
7132 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
7133 #define EXTI_IMR_MR11_Pos (11U)
7134 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
7135 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
7136 #define EXTI_IMR_MR12_Pos (12U)
7137 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
7138 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
7139 #define EXTI_IMR_MR13_Pos (13U)
7140 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
7141 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
7142 #define EXTI_IMR_MR14_Pos (14U)
7143 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
7144 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
7145 #define EXTI_IMR_MR15_Pos (15U)
7146 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
7147 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
7148 #define EXTI_IMR_MR16_Pos (16U)
7149 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
7150 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
7151 #define EXTI_IMR_MR17_Pos (17U)
7152 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
7153 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
7154 #define EXTI_IMR_MR18_Pos (18U)
7155 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
7156 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
7157 #define EXTI_IMR_MR19_Pos (19U)
7158 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
7159 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
7160 #define EXTI_IMR_MR20_Pos (20U)
7161 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
7162 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
7163 #define EXTI_IMR_MR21_Pos (21U)
7164 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
7165 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
7166 #define EXTI_IMR_MR22_Pos (22U)
7167 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
7168 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
7169 #define EXTI_IMR_MR23_Pos (23U)
7170 #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
7171 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
7172 #define EXTI_IMR_MR24_Pos (24U)
7173 #define EXTI_IMR_MR24_Msk (0x1U << EXTI_IMR_MR24_Pos) /*!< 0x01000000 */
7174 #define EXTI_IMR_MR24 EXTI_IMR_MR24_Msk /*!< Interrupt Mask on line 24 */
7175 #define EXTI_IMR_MR25_Pos (25U)
7176 #define EXTI_IMR_MR25_Msk (0x1U << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */
7177 #define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */
7178 #define EXTI_IMR_MR26_Pos (26U)
7179 #define EXTI_IMR_MR26_Msk (0x1U << EXTI_IMR_MR26_Pos) /*!< 0x04000000 */
7180 #define EXTI_IMR_MR26 EXTI_IMR_MR26_Msk /*!< Interrupt Mask on line 26 */
7181 #define EXTI_IMR_MR27_Pos (27U)
7182 #define EXTI_IMR_MR27_Msk (0x1U << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */
7183 #define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */
7184 #define EXTI_IMR_MR28_Pos (28U)
7185 #define EXTI_IMR_MR28_Msk (0x1U << EXTI_IMR_MR28_Pos) /*!< 0x10000000 */
7186 #define EXTI_IMR_MR28 EXTI_IMR_MR28_Msk /*!< Interrupt Mask on line 28 */
7187 #define EXTI_IMR_MR29_Pos (29U)
7188 #define EXTI_IMR_MR29_Msk (0x1U << EXTI_IMR_MR29_Pos) /*!< 0x20000000 */
7189 #define EXTI_IMR_MR29 EXTI_IMR_MR29_Msk /*!< Interrupt Mask on line 29 */
7190 #define EXTI_IMR_MR30_Pos (30U)
7191 #define EXTI_IMR_MR30_Msk (0x1U << EXTI_IMR_MR30_Pos) /*!< 0x40000000 */
7192 #define EXTI_IMR_MR30 EXTI_IMR_MR30_Msk /*!< Interrupt Mask on line 30 */
7193 #define EXTI_IMR_MR31_Pos (31U)
7194 #define EXTI_IMR_MR31_Msk (0x1U << EXTI_IMR_MR31_Pos) /*!< 0x80000000 */
7195 #define EXTI_IMR_MR31 EXTI_IMR_MR31_Msk /*!< Interrupt Mask on line 31 */
7196
7197 /* References Defines */
7198 #define EXTI_IMR_IM0 EXTI_IMR_MR0
7199 #define EXTI_IMR_IM1 EXTI_IMR_MR1
7200 #define EXTI_IMR_IM2 EXTI_IMR_MR2
7201 #define EXTI_IMR_IM3 EXTI_IMR_MR3
7202 #define EXTI_IMR_IM4 EXTI_IMR_MR4
7203 #define EXTI_IMR_IM5 EXTI_IMR_MR5
7204 #define EXTI_IMR_IM6 EXTI_IMR_MR6
7205 #define EXTI_IMR_IM7 EXTI_IMR_MR7
7206 #define EXTI_IMR_IM8 EXTI_IMR_MR8
7207 #define EXTI_IMR_IM9 EXTI_IMR_MR9
7208 #define EXTI_IMR_IM10 EXTI_IMR_MR10
7209 #define EXTI_IMR_IM11 EXTI_IMR_MR11
7210 #define EXTI_IMR_IM12 EXTI_IMR_MR12
7211 #define EXTI_IMR_IM13 EXTI_IMR_MR13
7212 #define EXTI_IMR_IM14 EXTI_IMR_MR14
7213 #define EXTI_IMR_IM15 EXTI_IMR_MR15
7214 #define EXTI_IMR_IM16 EXTI_IMR_MR16
7215 #define EXTI_IMR_IM17 EXTI_IMR_MR17
7216 #define EXTI_IMR_IM18 EXTI_IMR_MR18
7217 #define EXTI_IMR_IM19 EXTI_IMR_MR19
7218 #define EXTI_IMR_IM20 EXTI_IMR_MR20
7219 #define EXTI_IMR_IM21 EXTI_IMR_MR21
7220 #define EXTI_IMR_IM22 EXTI_IMR_MR22
7221 #define EXTI_IMR_IM23 EXTI_IMR_MR23
7222 #define EXTI_IMR_IM24 EXTI_IMR_MR24
7223 #define EXTI_IMR_IM25 EXTI_IMR_MR25
7224 #define EXTI_IMR_IM26 EXTI_IMR_MR26
7225 #define EXTI_IMR_IM27 EXTI_IMR_MR27
7226 #define EXTI_IMR_IM28 EXTI_IMR_MR28
7227 #define EXTI_IMR_IM29 EXTI_IMR_MR29
7228 #define EXTI_IMR_IM30 EXTI_IMR_MR30
7229 #define EXTI_IMR_IM31 EXTI_IMR_MR31
7230
7231 #define EXTI_IMR_IM_Pos (0U)
7232 #define EXTI_IMR_IM_Msk (0xFFFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0xFFFFFFFF */
7233 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
7234
7235 /******************* Bit definition for EXTI_EMR register *******************/
7236 #define EXTI_EMR_MR0_Pos (0U)
7237 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
7238 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
7239 #define EXTI_EMR_MR1_Pos (1U)
7240 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
7241 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
7242 #define EXTI_EMR_MR2_Pos (2U)
7243 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
7244 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
7245 #define EXTI_EMR_MR3_Pos (3U)
7246 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
7247 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
7248 #define EXTI_EMR_MR4_Pos (4U)
7249 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
7250 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
7251 #define EXTI_EMR_MR5_Pos (5U)
7252 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
7253 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
7254 #define EXTI_EMR_MR6_Pos (6U)
7255 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
7256 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
7257 #define EXTI_EMR_MR7_Pos (7U)
7258 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
7259 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
7260 #define EXTI_EMR_MR8_Pos (8U)
7261 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
7262 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
7263 #define EXTI_EMR_MR9_Pos (9U)
7264 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
7265 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
7266 #define EXTI_EMR_MR10_Pos (10U)
7267 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
7268 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
7269 #define EXTI_EMR_MR11_Pos (11U)
7270 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
7271 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
7272 #define EXTI_EMR_MR12_Pos (12U)
7273 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
7274 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
7275 #define EXTI_EMR_MR13_Pos (13U)
7276 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
7277 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
7278 #define EXTI_EMR_MR14_Pos (14U)
7279 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
7280 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
7281 #define EXTI_EMR_MR15_Pos (15U)
7282 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
7283 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
7284 #define EXTI_EMR_MR16_Pos (16U)
7285 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
7286 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
7287 #define EXTI_EMR_MR17_Pos (17U)
7288 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
7289 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
7290 #define EXTI_EMR_MR18_Pos (18U)
7291 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
7292 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
7293 #define EXTI_EMR_MR19_Pos (19U)
7294 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
7295 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
7296 #define EXTI_EMR_MR20_Pos (20U)
7297 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
7298 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
7299 #define EXTI_EMR_MR21_Pos (21U)
7300 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
7301 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
7302 #define EXTI_EMR_MR22_Pos (22U)
7303 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
7304 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
7305 #define EXTI_EMR_MR23_Pos (23U)
7306 #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
7307 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
7308 #define EXTI_EMR_MR24_Pos (24U)
7309 #define EXTI_EMR_MR24_Msk (0x1U << EXTI_EMR_MR24_Pos) /*!< 0x01000000 */
7310 #define EXTI_EMR_MR24 EXTI_EMR_MR24_Msk /*!< Event Mask on line 24 */
7311 #define EXTI_EMR_MR25_Pos (25U)
7312 #define EXTI_EMR_MR25_Msk (0x1U << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */
7313 #define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */
7314 #define EXTI_EMR_MR26_Pos (26U)
7315 #define EXTI_EMR_MR26_Msk (0x1U << EXTI_EMR_MR26_Pos) /*!< 0x04000000 */
7316 #define EXTI_EMR_MR26 EXTI_EMR_MR26_Msk /*!< Event Mask on line 26 */
7317 #define EXTI_EMR_MR27_Pos (27U)
7318 #define EXTI_EMR_MR27_Msk (0x1U << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */
7319 #define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */
7320 #define EXTI_EMR_MR28_Pos (28U)
7321 #define EXTI_EMR_MR28_Msk (0x1U << EXTI_EMR_MR28_Pos) /*!< 0x10000000 */
7322 #define EXTI_EMR_MR28 EXTI_EMR_MR28_Msk /*!< Event Mask on line 28 */
7323 #define EXTI_EMR_MR29_Pos (29U)
7324 #define EXTI_EMR_MR29_Msk (0x1U << EXTI_EMR_MR29_Pos) /*!< 0x20000000 */
7325 #define EXTI_EMR_MR29 EXTI_EMR_MR29_Msk /*!< Event Mask on line 29 */
7326 #define EXTI_EMR_MR30_Pos (30U)
7327 #define EXTI_EMR_MR30_Msk (0x1U << EXTI_EMR_MR30_Pos) /*!< 0x40000000 */
7328 #define EXTI_EMR_MR30 EXTI_EMR_MR30_Msk /*!< Event Mask on line 30 */
7329 #define EXTI_EMR_MR31_Pos (31U)
7330 #define EXTI_EMR_MR31_Msk (0x1U << EXTI_EMR_MR31_Pos) /*!< 0x80000000 */
7331 #define EXTI_EMR_MR31 EXTI_EMR_MR31_Msk /*!< Event Mask on line 31 */
7332
7333 /* References Defines */
7334 #define EXTI_EMR_EM0 EXTI_EMR_MR0
7335 #define EXTI_EMR_EM1 EXTI_EMR_MR1
7336 #define EXTI_EMR_EM2 EXTI_EMR_MR2
7337 #define EXTI_EMR_EM3 EXTI_EMR_MR3
7338 #define EXTI_EMR_EM4 EXTI_EMR_MR4
7339 #define EXTI_EMR_EM5 EXTI_EMR_MR5
7340 #define EXTI_EMR_EM6 EXTI_EMR_MR6
7341 #define EXTI_EMR_EM7 EXTI_EMR_MR7
7342 #define EXTI_EMR_EM8 EXTI_EMR_MR8
7343 #define EXTI_EMR_EM9 EXTI_EMR_MR9
7344 #define EXTI_EMR_EM10 EXTI_EMR_MR10
7345 #define EXTI_EMR_EM11 EXTI_EMR_MR11
7346 #define EXTI_EMR_EM12 EXTI_EMR_MR12
7347 #define EXTI_EMR_EM13 EXTI_EMR_MR13
7348 #define EXTI_EMR_EM14 EXTI_EMR_MR14
7349 #define EXTI_EMR_EM15 EXTI_EMR_MR15
7350 #define EXTI_EMR_EM16 EXTI_EMR_MR16
7351 #define EXTI_EMR_EM17 EXTI_EMR_MR17
7352 #define EXTI_EMR_EM18 EXTI_EMR_MR18
7353 #define EXTI_EMR_EM19 EXTI_EMR_MR19
7354 #define EXTI_EMR_EM20 EXTI_EMR_MR20
7355 #define EXTI_EMR_EM21 EXTI_EMR_MR21
7356 #define EXTI_EMR_EM22 EXTI_EMR_MR22
7357 #define EXTI_EMR_EM23 EXTI_EMR_MR23
7358 #define EXTI_EMR_EM24 EXTI_EMR_MR24
7359 #define EXTI_EMR_EM25 EXTI_EMR_MR25
7360 #define EXTI_EMR_EM26 EXTI_EMR_MR26
7361 #define EXTI_EMR_EM27 EXTI_EMR_MR27
7362 #define EXTI_EMR_EM28 EXTI_EMR_MR28
7363 #define EXTI_EMR_EM29 EXTI_EMR_MR29
7364 #define EXTI_EMR_EM30 EXTI_EMR_MR30
7365 #define EXTI_EMR_EM31 EXTI_EMR_MR31
7366
7367 /****************** Bit definition for EXTI_RTSR register *******************/
7368 #define EXTI_RTSR_TR0_Pos (0U)
7369 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
7370 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
7371 #define EXTI_RTSR_TR1_Pos (1U)
7372 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
7373 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
7374 #define EXTI_RTSR_TR2_Pos (2U)
7375 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
7376 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
7377 #define EXTI_RTSR_TR3_Pos (3U)
7378 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
7379 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
7380 #define EXTI_RTSR_TR4_Pos (4U)
7381 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
7382 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
7383 #define EXTI_RTSR_TR5_Pos (5U)
7384 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
7385 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
7386 #define EXTI_RTSR_TR6_Pos (6U)
7387 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
7388 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
7389 #define EXTI_RTSR_TR7_Pos (7U)
7390 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
7391 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
7392 #define EXTI_RTSR_TR8_Pos (8U)
7393 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
7394 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
7395 #define EXTI_RTSR_TR9_Pos (9U)
7396 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
7397 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
7398 #define EXTI_RTSR_TR10_Pos (10U)
7399 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
7400 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
7401 #define EXTI_RTSR_TR11_Pos (11U)
7402 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
7403 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
7404 #define EXTI_RTSR_TR12_Pos (12U)
7405 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
7406 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
7407 #define EXTI_RTSR_TR13_Pos (13U)
7408 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
7409 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
7410 #define EXTI_RTSR_TR14_Pos (14U)
7411 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
7412 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
7413 #define EXTI_RTSR_TR15_Pos (15U)
7414 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
7415 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
7416 #define EXTI_RTSR_TR16_Pos (16U)
7417 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
7418 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
7419 #define EXTI_RTSR_TR17_Pos (17U)
7420 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
7421 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
7422 #define EXTI_RTSR_TR18_Pos (18U)
7423 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
7424 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
7425 #define EXTI_RTSR_TR19_Pos (19U)
7426 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
7427 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
7428 #define EXTI_RTSR_TR20_Pos (20U)
7429 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
7430 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
7431 #define EXTI_RTSR_TR21_Pos (21U)
7432 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
7433 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
7434 #define EXTI_RTSR_TR22_Pos (22U)
7435 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
7436 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
7437 #define EXTI_RTSR_TR29_Pos (29U)
7438 #define EXTI_RTSR_TR29_Msk (0x1U << EXTI_RTSR_TR29_Pos) /*!< 0x20000000 */
7439 #define EXTI_RTSR_TR29 EXTI_RTSR_TR29_Msk /*!< Rising trigger event configuration bit of line 29 */
7440 #define EXTI_RTSR_TR30_Pos (30U)
7441 #define EXTI_RTSR_TR30_Msk (0x1U << EXTI_RTSR_TR30_Pos) /*!< 0x40000000 */
7442 #define EXTI_RTSR_TR30 EXTI_RTSR_TR30_Msk /*!< Rising trigger event configuration bit of line 30 */
7443 #define EXTI_RTSR_TR31_Pos (31U)
7444 #define EXTI_RTSR_TR31_Msk (0x1U << EXTI_RTSR_TR31_Pos) /*!< 0x80000000 */
7445 #define EXTI_RTSR_TR31 EXTI_RTSR_TR31_Msk /*!< Rising trigger event configuration bit of line 31 */
7446
7447 /* References Defines */
7448 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
7449 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
7450 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
7451 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
7452 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
7453 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
7454 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
7455 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
7456 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
7457 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
7458 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
7459 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
7460 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
7461 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
7462 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
7463 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
7464 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
7465 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
7466 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18
7467 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19
7468 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20
7469 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21
7470 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22
7471 #if defined(EXTI_RTSR_TR23)
7472 #define EXTI_RTSR_RT23 EXTI_RTSR_TR23
7473 #endif
7474 #if defined(EXTI_RTSR_TR24)
7475 #define EXTI_RTSR_RT24 EXTI_RTSR_TR24
7476 #endif
7477 #if defined(EXTI_RTSR_TR25)
7478 #define EXTI_RTSR_RT25 EXTI_RTSR_TR25
7479 #endif
7480 #if defined(EXTI_RTSR_TR26)
7481 #define EXTI_RTSR_RT26 EXTI_RTSR_TR26
7482 #endif
7483 #if defined(EXTI_RTSR_TR27)
7484 #define EXTI_RTSR_RT27 EXTI_RTSR_TR27
7485 #endif
7486 #if defined(EXTI_RTSR_TR28)
7487 #define EXTI_RTSR_RT28 EXTI_RTSR_TR28
7488 #endif
7489 #define EXTI_RTSR_RT29 EXTI_RTSR_TR29
7490 #define EXTI_RTSR_RT30 EXTI_RTSR_TR30
7491 #define EXTI_RTSR_RT31 EXTI_RTSR_TR31
7492
7493 /****************** Bit definition for EXTI_FTSR register *******************/
7494 #define EXTI_FTSR_TR0_Pos (0U)
7495 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
7496 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
7497 #define EXTI_FTSR_TR1_Pos (1U)
7498 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
7499 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
7500 #define EXTI_FTSR_TR2_Pos (2U)
7501 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
7502 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
7503 #define EXTI_FTSR_TR3_Pos (3U)
7504 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
7505 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
7506 #define EXTI_FTSR_TR4_Pos (4U)
7507 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
7508 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
7509 #define EXTI_FTSR_TR5_Pos (5U)
7510 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
7511 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
7512 #define EXTI_FTSR_TR6_Pos (6U)
7513 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
7514 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
7515 #define EXTI_FTSR_TR7_Pos (7U)
7516 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
7517 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
7518 #define EXTI_FTSR_TR8_Pos (8U)
7519 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
7520 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
7521 #define EXTI_FTSR_TR9_Pos (9U)
7522 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
7523 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
7524 #define EXTI_FTSR_TR10_Pos (10U)
7525 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
7526 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
7527 #define EXTI_FTSR_TR11_Pos (11U)
7528 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
7529 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
7530 #define EXTI_FTSR_TR12_Pos (12U)
7531 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
7532 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
7533 #define EXTI_FTSR_TR13_Pos (13U)
7534 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
7535 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
7536 #define EXTI_FTSR_TR14_Pos (14U)
7537 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
7538 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
7539 #define EXTI_FTSR_TR15_Pos (15U)
7540 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
7541 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
7542 #define EXTI_FTSR_TR16_Pos (16U)
7543 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
7544 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
7545 #define EXTI_FTSR_TR17_Pos (17U)
7546 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
7547 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
7548 #define EXTI_FTSR_TR18_Pos (18U)
7549 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
7550 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
7551 #define EXTI_FTSR_TR19_Pos (19U)
7552 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
7553 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
7554 #define EXTI_FTSR_TR20_Pos (20U)
7555 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
7556 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
7557 #define EXTI_FTSR_TR21_Pos (21U)
7558 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
7559 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
7560 #define EXTI_FTSR_TR22_Pos (22U)
7561 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
7562 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
7563 #define EXTI_FTSR_TR29_Pos (29U)
7564 #define EXTI_FTSR_TR29_Msk (0x1U << EXTI_FTSR_TR29_Pos) /*!< 0x20000000 */
7565 #define EXTI_FTSR_TR29 EXTI_FTSR_TR29_Msk /*!< Falling trigger event configuration bit of line 29 */
7566 #define EXTI_FTSR_TR30_Pos (30U)
7567 #define EXTI_FTSR_TR30_Msk (0x1U << EXTI_FTSR_TR30_Pos) /*!< 0x40000000 */
7568 #define EXTI_FTSR_TR30 EXTI_FTSR_TR30_Msk /*!< Falling trigger event configuration bit of line 30 */
7569 #define EXTI_FTSR_TR31_Pos (31U)
7570 #define EXTI_FTSR_TR31_Msk (0x1U << EXTI_FTSR_TR31_Pos) /*!< 0x80000000 */
7571 #define EXTI_FTSR_TR31 EXTI_FTSR_TR31_Msk /*!< Falling trigger event configuration bit of line 31 */
7572
7573 /* References Defines */
7574 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
7575 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
7576 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
7577 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
7578 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
7579 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
7580 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
7581 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
7582 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
7583 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
7584 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
7585 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
7586 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
7587 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
7588 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
7589 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
7590 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
7591 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
7592 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18
7593 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19
7594 #define EXTI_FTSR_FT20 EXTI_FTSR_TR20
7595 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21
7596 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22
7597 #if defined(EXTI_FTSR_TR23)
7598 #define EXTI_FTSR_FT23 EXTI_FTSR_TR23
7599 #endif
7600 #if defined(EXTI_FTSR_TR24)
7601 #define EXTI_FTSR_FT24 EXTI_FTSR_TR24
7602 #endif
7603 #if defined(EXTI_FTSR_TR25)
7604 #define EXTI_FTSR_FT25 EXTI_FTSR_TR25
7605 #endif
7606 #if defined(EXTI_FTSR_TR26)
7607 #define EXTI_FTSR_FT26 EXTI_FTSR_TR26
7608 #endif
7609 #if defined(EXTI_FTSR_TR27)
7610 #define EXTI_FTSR_FT27 EXTI_FTSR_TR27
7611 #endif
7612 #if defined(EXTI_FTSR_TR28)
7613 #define EXTI_FTSR_FT28 EXTI_FTSR_TR28
7614 #endif
7615 #define EXTI_FTSR_FT29 EXTI_FTSR_TR29
7616 #define EXTI_FTSR_FT30 EXTI_FTSR_TR30
7617 #define EXTI_FTSR_FT31 EXTI_FTSR_TR31
7618
7619 /****************** Bit definition for EXTI_SWIER register ******************/
7620 #define EXTI_SWIER_SWIER0_Pos (0U)
7621 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
7622 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
7623 #define EXTI_SWIER_SWIER1_Pos (1U)
7624 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
7625 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
7626 #define EXTI_SWIER_SWIER2_Pos (2U)
7627 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
7628 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
7629 #define EXTI_SWIER_SWIER3_Pos (3U)
7630 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
7631 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
7632 #define EXTI_SWIER_SWIER4_Pos (4U)
7633 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
7634 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
7635 #define EXTI_SWIER_SWIER5_Pos (5U)
7636 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
7637 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
7638 #define EXTI_SWIER_SWIER6_Pos (6U)
7639 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
7640 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
7641 #define EXTI_SWIER_SWIER7_Pos (7U)
7642 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
7643 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
7644 #define EXTI_SWIER_SWIER8_Pos (8U)
7645 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
7646 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
7647 #define EXTI_SWIER_SWIER9_Pos (9U)
7648 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
7649 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
7650 #define EXTI_SWIER_SWIER10_Pos (10U)
7651 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
7652 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
7653 #define EXTI_SWIER_SWIER11_Pos (11U)
7654 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
7655 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
7656 #define EXTI_SWIER_SWIER12_Pos (12U)
7657 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
7658 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
7659 #define EXTI_SWIER_SWIER13_Pos (13U)
7660 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
7661 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
7662 #define EXTI_SWIER_SWIER14_Pos (14U)
7663 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
7664 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
7665 #define EXTI_SWIER_SWIER15_Pos (15U)
7666 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
7667 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
7668 #define EXTI_SWIER_SWIER16_Pos (16U)
7669 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
7670 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
7671 #define EXTI_SWIER_SWIER17_Pos (17U)
7672 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
7673 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
7674 #define EXTI_SWIER_SWIER18_Pos (18U)
7675 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
7676 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
7677 #define EXTI_SWIER_SWIER19_Pos (19U)
7678 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
7679 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
7680 #define EXTI_SWIER_SWIER20_Pos (20U)
7681 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
7682 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
7683 #define EXTI_SWIER_SWIER21_Pos (21U)
7684 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
7685 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
7686 #define EXTI_SWIER_SWIER22_Pos (22U)
7687 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
7688 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
7689 #define EXTI_SWIER_SWIER29_Pos (29U)
7690 #define EXTI_SWIER_SWIER29_Msk (0x1U << EXTI_SWIER_SWIER29_Pos) /*!< 0x20000000 */
7691 #define EXTI_SWIER_SWIER29 EXTI_SWIER_SWIER29_Msk /*!< Software Interrupt on line 29 */
7692 #define EXTI_SWIER_SWIER30_Pos (30U)
7693 #define EXTI_SWIER_SWIER30_Msk (0x1U << EXTI_SWIER_SWIER30_Pos) /*!< 0x40000000 */
7694 #define EXTI_SWIER_SWIER30 EXTI_SWIER_SWIER30_Msk /*!< Software Interrupt on line 30 */
7695 #define EXTI_SWIER_SWIER31_Pos (31U)
7696 #define EXTI_SWIER_SWIER31_Msk (0x1U << EXTI_SWIER_SWIER31_Pos) /*!< 0x80000000 */
7697 #define EXTI_SWIER_SWIER31 EXTI_SWIER_SWIER31_Msk /*!< Software Interrupt on line 31 */
7698
7699 /* References Defines */
7700 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
7701 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
7702 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
7703 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
7704 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
7705 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
7706 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
7707 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
7708 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
7709 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
7710 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
7711 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
7712 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
7713 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
7714 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
7715 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
7716 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
7717 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
7718 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
7719 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
7720 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
7721 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
7722 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
7723 #if defined(EXTI_SWIER_SWIER23)
7724 #define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
7725 #endif
7726 #if defined(EXTI_SWIER_SWIER24)
7727 #define EXTI_SWIER_SWI24 EXTI_SWIER_SWIER24
7728 #endif
7729 #if defined(EXTI_SWIER_SWIER25)
7730 #define EXTI_SWIER_SWI25 EXTI_SWIER_SWIER25
7731 #endif
7732 #if defined(EXTI_SWIER_SWIER26)
7733 #define EXTI_SWIER_SWI26 EXTI_SWIER_SWIER26
7734 #endif
7735 #if defined(EXTI_SWIER_SWIER27)
7736 #define EXTI_SWIER_SWI27 EXTI_SWIER_SWIER27
7737 #endif
7738 #if defined(EXTI_SWIER_SWIER28)
7739 #define EXTI_SWIER_SWI28 EXTI_SWIER_SWIER28
7740 #endif
7741 #define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
7742 #define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
7743 #define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
7744
7745 /******************* Bit definition for EXTI_PR register ********************/
7746 #define EXTI_PR_PR0_Pos (0U)
7747 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
7748 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
7749 #define EXTI_PR_PR1_Pos (1U)
7750 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
7751 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
7752 #define EXTI_PR_PR2_Pos (2U)
7753 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
7754 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
7755 #define EXTI_PR_PR3_Pos (3U)
7756 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
7757 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
7758 #define EXTI_PR_PR4_Pos (4U)
7759 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
7760 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
7761 #define EXTI_PR_PR5_Pos (5U)
7762 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
7763 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
7764 #define EXTI_PR_PR6_Pos (6U)
7765 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
7766 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
7767 #define EXTI_PR_PR7_Pos (7U)
7768 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
7769 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
7770 #define EXTI_PR_PR8_Pos (8U)
7771 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
7772 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
7773 #define EXTI_PR_PR9_Pos (9U)
7774 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
7775 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
7776 #define EXTI_PR_PR10_Pos (10U)
7777 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
7778 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
7779 #define EXTI_PR_PR11_Pos (11U)
7780 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
7781 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
7782 #define EXTI_PR_PR12_Pos (12U)
7783 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
7784 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
7785 #define EXTI_PR_PR13_Pos (13U)
7786 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
7787 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
7788 #define EXTI_PR_PR14_Pos (14U)
7789 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
7790 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
7791 #define EXTI_PR_PR15_Pos (15U)
7792 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
7793 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
7794 #define EXTI_PR_PR16_Pos (16U)
7795 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
7796 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
7797 #define EXTI_PR_PR17_Pos (17U)
7798 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
7799 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
7800 #define EXTI_PR_PR18_Pos (18U)
7801 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
7802 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
7803 #define EXTI_PR_PR19_Pos (19U)
7804 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
7805 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
7806 #define EXTI_PR_PR20_Pos (20U)
7807 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
7808 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
7809 #define EXTI_PR_PR21_Pos (21U)
7810 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
7811 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
7812 #define EXTI_PR_PR22_Pos (22U)
7813 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
7814 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
7815 #define EXTI_PR_PR29_Pos (29U)
7816 #define EXTI_PR_PR29_Msk (0x1U << EXTI_PR_PR29_Pos) /*!< 0x20000000 */
7817 #define EXTI_PR_PR29 EXTI_PR_PR29_Msk /*!< Pending bit for line 29 */
7818 #define EXTI_PR_PR30_Pos (30U)
7819 #define EXTI_PR_PR30_Msk (0x1U << EXTI_PR_PR30_Pos) /*!< 0x40000000 */
7820 #define EXTI_PR_PR30 EXTI_PR_PR30_Msk /*!< Pending bit for line 30 */
7821 #define EXTI_PR_PR31_Pos (31U)
7822 #define EXTI_PR_PR31_Msk (0x1U << EXTI_PR_PR31_Pos) /*!< 0x80000000 */
7823 #define EXTI_PR_PR31 EXTI_PR_PR31_Msk /*!< Pending bit for line 31 */
7824
7825 /* References Defines */
7826 #define EXTI_PR_PIF0 EXTI_PR_PR0
7827 #define EXTI_PR_PIF1 EXTI_PR_PR1
7828 #define EXTI_PR_PIF2 EXTI_PR_PR2
7829 #define EXTI_PR_PIF3 EXTI_PR_PR3
7830 #define EXTI_PR_PIF4 EXTI_PR_PR4
7831 #define EXTI_PR_PIF5 EXTI_PR_PR5
7832 #define EXTI_PR_PIF6 EXTI_PR_PR6
7833 #define EXTI_PR_PIF6 EXTI_PR_PR6
7834 #define EXTI_PR_PIF7 EXTI_PR_PR7
7835 #define EXTI_PR_PIF8 EXTI_PR_PR8
7836 #define EXTI_PR_PIF9 EXTI_PR_PR9
7837 #define EXTI_PR_PIF10 EXTI_PR_PR10
7838 #define EXTI_PR_PIF11 EXTI_PR_PR11
7839 #define EXTI_PR_PIF12 EXTI_PR_PR12
7840 #define EXTI_PR_PIF13 EXTI_PR_PR13
7841 #define EXTI_PR_PIF14 EXTI_PR_PR14
7842 #define EXTI_PR_PIF15 EXTI_PR_PR15
7843 #define EXTI_PR_PIF16 EXTI_PR_PR16
7844 #define EXTI_PR_PIF17 EXTI_PR_PR17
7845 #define EXTI_PR_PIF18 EXTI_PR_PR18
7846 #define EXTI_PR_PIF19 EXTI_PR_PR19
7847 #define EXTI_PR_PIF20 EXTI_PR_PR20
7848 #define EXTI_PR_PIF21 EXTI_PR_PR21
7849 #define EXTI_PR_PIF22 EXTI_PR_PR22
7850 #if defined(EXTI_PR_PR23)
7851 #define EXTI_PR_PIF23 EXTI_PR_PR23
7852 #endif
7853 #if defined(EXTI_PR_PR24)
7854 #define EXTI_PR_PIF24 EXTI_PR_PR24
7855 #endif
7856 #if defined(EXTI_PR_PR25)
7857 #define EXTI_PR_PIF25 EXTI_PR_PR25
7858 #endif
7859 #if defined(EXTI_PR_PR26)
7860 #define EXTI_PR_PIF26 EXTI_PR_PR26
7861 #endif
7862 #if defined(EXTI_PR_PR27)
7863 #define EXTI_PR_PIF27 EXTI_PR_PR27
7864 #endif
7865 #if defined(EXTI_PR_PR28)
7866 #define EXTI_PR_PIF28 EXTI_PR_PR28
7867 #endif
7868 #define EXTI_PR_PIF29 EXTI_PR_PR29
7869 #define EXTI_PR_PIF30 EXTI_PR_PR30
7870 #define EXTI_PR_PIF31 EXTI_PR_PR31
7871
7872 #define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */
7873
7874 /******************* Bit definition for EXTI_IMR2 register ******************/
7875 #define EXTI_IMR2_MR32_Pos (0U)
7876 #define EXTI_IMR2_MR32_Msk (0x1U << EXTI_IMR2_MR32_Pos) /*!< 0x00000001 */
7877 #define EXTI_IMR2_MR32 EXTI_IMR2_MR32_Msk /*!< Interrupt Mask on line 32 */
7878 #define EXTI_IMR2_MR33_Pos (1U)
7879 #define EXTI_IMR2_MR33_Msk (0x1U << EXTI_IMR2_MR33_Pos) /*!< 0x00000002 */
7880 #define EXTI_IMR2_MR33 EXTI_IMR2_MR33_Msk /*!< Interrupt Mask on line 33 */
7881 #define EXTI_IMR2_MR34_Pos (2U)
7882 #define EXTI_IMR2_MR34_Msk (0x1U << EXTI_IMR2_MR34_Pos) /*!< 0x00000004 */
7883 #define EXTI_IMR2_MR34 EXTI_IMR2_MR34_Msk /*!< Interrupt Mask on line 34 */
7884 #define EXTI_IMR2_MR35_Pos (3U)
7885 #define EXTI_IMR2_MR35_Msk (0x1U << EXTI_IMR2_MR35_Pos) /*!< 0x00000008 */
7886 #define EXTI_IMR2_MR35 EXTI_IMR2_MR35_Msk /*!< Interrupt Mask on line 35 */
7887
7888 /* References Defines */
7889
7890 #define EXTI_IMR2_IM32 EXTI_IMR2_MR32
7891 #define EXTI_IMR2_IM33 EXTI_IMR2_MR33
7892 #define EXTI_IMR2_IM34 EXTI_IMR2_MR34
7893 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35
7894
7895 #define EXTI_IMR2_IM_Pos (0U)
7896 #define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
7897 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
7898
7899 /******************* Bit definition for EXTI_EMR2 ****************************/
7900 #define EXTI_EMR2_MR32_Pos (0U)
7901 #define EXTI_EMR2_MR32_Msk (0x1U << EXTI_EMR2_MR32_Pos) /*!< 0x00000001 */
7902 #define EXTI_EMR2_MR32 EXTI_EMR2_MR32_Msk /*!< Event Mask on line 32 */
7903 #define EXTI_EMR2_MR33_Pos (1U)
7904 #define EXTI_EMR2_MR33_Msk (0x1U << EXTI_EMR2_MR33_Pos) /*!< 0x00000002 */
7905 #define EXTI_EMR2_MR33 EXTI_EMR2_MR33_Msk /*!< Event Mask on line 33 */
7906 #define EXTI_EMR2_MR34_Pos (2U)
7907 #define EXTI_EMR2_MR34_Msk (0x1U << EXTI_EMR2_MR34_Pos) /*!< 0x00000004 */
7908 #define EXTI_EMR2_MR34 EXTI_EMR2_MR34_Msk /*!< Event Mask on line 34 */
7909 #define EXTI_EMR2_MR35_Pos (3U)
7910 #define EXTI_EMR2_MR35_Msk (0x1U << EXTI_EMR2_MR35_Pos) /*!< 0x00000008 */
7911 #define EXTI_EMR2_MR35 EXTI_EMR2_MR35_Msk /*!< Event Mask on line 34 */
7912
7913 /* References Defines */
7914 #define EXTI_EMR2_EM32 EXTI_EMR2_MR32
7915 #define EXTI_EMR2_EM33 EXTI_EMR2_MR33
7916 #define EXTI_EMR2_EM34 EXTI_EMR2_MR34
7917 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
7918
7919 #define EXTI_EMR2_EM_Pos (0U)
7920 #define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
7921 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
7922
7923 /****************** Bit definition for EXTI_RTSR2 register ********************/
7924 #define EXTI_RTSR2_TR32_Pos (0U)
7925 #define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
7926 #define EXTI_RTSR2_TR32 EXTI_RTSR2_TR32_Msk /*!< Rising trigger event configuration bit of line 32 */
7927 #define EXTI_RTSR2_TR33_Pos (1U)
7928 #define EXTI_RTSR2_TR33_Msk (0x1U << EXTI_RTSR2_TR33_Pos) /*!< 0x00000002 */
7929 #define EXTI_RTSR2_TR33 EXTI_RTSR2_TR33_Msk /*!< Rising trigger event configuration bit of line 33 */
7930
7931 /* References Defines */
7932 #define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
7933 #define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
7934 #if defined(EXTI_RTSR2_TR34)
7935 #define EXTI_RTSR2_RT34 EXTI_RTSR2_TR34
7936 #endif
7937 #if defined(EXTI_RTSR2_TR35)
7938 #define EXTI_RTSR2_RT35 EXTI_RTSR2_TR35
7939 #endif
7940
7941 /****************** Bit definition for EXTI_FTSR2 register ******************/
7942 #define EXTI_FTSR2_TR32_Pos (0U)
7943 #define EXTI_FTSR2_TR32_Msk (0x1U << EXTI_FTSR2_TR32_Pos) /*!< 0x00000001 */
7944 #define EXTI_FTSR2_TR32 EXTI_FTSR2_TR32_Msk /*!< Falling trigger event configuration bit of line 32 */
7945 #define EXTI_FTSR2_TR33_Pos (1U)
7946 #define EXTI_FTSR2_TR33_Msk (0x1U << EXTI_FTSR2_TR33_Pos) /*!< 0x00000002 */
7947 #define EXTI_FTSR2_TR33 EXTI_FTSR2_TR33_Msk /*!< Falling trigger event configuration bit of line 33 */
7948
7949 /* References Defines */
7950 #define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
7951 #define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
7952 #if defined(EXTI_FTSR2_TR34)
7953 #define EXTI_FTSR2_FT34 EXTI_FTSR2_TR34
7954 #endif
7955 #if defined(EXTI_FTSR2_TR35)
7956 #define EXTI_FTSR2_FT35 EXTI_FTSR2_TR35
7957 #endif
7958
7959 /****************** Bit definition for EXTI_SWIER2 register *****************/
7960 #define EXTI_SWIER2_SWIER32_Pos (0U)
7961 #define EXTI_SWIER2_SWIER32_Msk (0x1U << EXTI_SWIER2_SWIER32_Pos) /*!< 0x00000001 */
7962 #define EXTI_SWIER2_SWIER32 EXTI_SWIER2_SWIER32_Msk /*!< Software Interrupt on line 32 */
7963 #define EXTI_SWIER2_SWIER33_Pos (1U)
7964 #define EXTI_SWIER2_SWIER33_Msk (0x1U << EXTI_SWIER2_SWIER33_Pos) /*!< 0x00000002 */
7965 #define EXTI_SWIER2_SWIER33 EXTI_SWIER2_SWIER33_Msk /*!< Software Interrupt on line 33 */
7966
7967 /* References Defines */
7968 #define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
7969 #define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
7970 #if defined(EXTI_SWIER2_SWIER34)
7971 #define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWIER34
7972 #endif
7973 #if defined(EXTI_SWIER2_SWIER35)
7974 #define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWIER35
7975 #endif
7976
7977 /******************* Bit definition for EXTI_PR2 register *******************/
7978 #define EXTI_PR2_PR32_Pos (0U)
7979 #define EXTI_PR2_PR32_Msk (0x1U << EXTI_PR2_PR32_Pos) /*!< 0x00000001 */
7980 #define EXTI_PR2_PR32 EXTI_PR2_PR32_Msk /*!< Pending bit for line 32 */
7981 #define EXTI_PR2_PR33_Pos (1U)
7982 #define EXTI_PR2_PR33_Msk (0x1U << EXTI_PR2_PR33_Pos) /*!< 0x00000002 */
7983 #define EXTI_PR2_PR33 EXTI_PR2_PR33_Msk /*!< Pending bit for line 33 */
7984
7985 /* References Defines */
7986 #define EXTI_PR2_PIF32 EXTI_PR2_PR32
7987 #define EXTI_PR2_PIF33 EXTI_PR2_PR33
7988 #if defined(EXTI_PR2_PR34)
7989 #define EXTI_PR2_PIF34 EXTI_PR2_PR34
7990 #endif
7991 #if defined(EXTI_PR2_PR35)
7992 #define EXTI_PR2_PIF35 EXTI_PR2_PR35
7993 #endif
7994
7995
7996 /******************************************************************************/
7997 /* */
7998 /* FLASH */
7999 /* */
8000 /******************************************************************************/
8001 /******************* Bit definition for FLASH_ACR register ******************/
8002 #define FLASH_ACR_LATENCY_Pos (0U)
8003 #define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
8004 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
8005 #define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
8006 #define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
8007 #define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
8008
8009 #define FLASH_ACR_HLFCYA_Pos (3U)
8010 #define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
8011 #define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
8012 #define FLASH_ACR_PRFTBE_Pos (4U)
8013 #define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
8014 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
8015 #define FLASH_ACR_PRFTBS_Pos (5U)
8016 #define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
8017 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
8018
8019 /****************** Bit definition for FLASH_KEYR register ******************/
8020 #define FLASH_KEYR_FKEYR_Pos (0U)
8021 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
8022 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
8023
8024 #define RDP_KEY_Pos (0U)
8025 #define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
8026 #define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
8027 #define FLASH_KEY1_Pos (0U)
8028 #define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
8029 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
8030 #define FLASH_KEY2_Pos (0U)
8031 #define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
8032 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
8033
8034 /***************** Bit definition for FLASH_OPTKEYR register ****************/
8035 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
8036 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
8037 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
8038
8039 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
8040 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
8041
8042 /****************** Bit definition for FLASH_SR register *******************/
8043 #define FLASH_SR_BSY_Pos (0U)
8044 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
8045 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
8046 #define FLASH_SR_PGERR_Pos (2U)
8047 #define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
8048 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
8049 #define FLASH_SR_WRPERR_Pos (4U)
8050 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
8051 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write Protection Error */
8052 #define FLASH_SR_EOP_Pos (5U)
8053 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
8054 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
8055
8056 /******************* Bit definition for FLASH_CR register *******************/
8057 #define FLASH_CR_PG_Pos (0U)
8058 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
8059 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
8060 #define FLASH_CR_PER_Pos (1U)
8061 #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
8062 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
8063 #define FLASH_CR_MER_Pos (2U)
8064 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
8065 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
8066 #define FLASH_CR_OPTPG_Pos (4U)
8067 #define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
8068 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
8069 #define FLASH_CR_OPTER_Pos (5U)
8070 #define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
8071 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
8072 #define FLASH_CR_STRT_Pos (6U)
8073 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
8074 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
8075 #define FLASH_CR_LOCK_Pos (7U)
8076 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
8077 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
8078 #define FLASH_CR_OPTWRE_Pos (9U)
8079 #define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
8080 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
8081 #define FLASH_CR_ERRIE_Pos (10U)
8082 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
8083 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
8084 #define FLASH_CR_EOPIE_Pos (12U)
8085 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
8086 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
8087 #define FLASH_CR_OBL_LAUNCH_Pos (13U)
8088 #define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */
8089 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< OptionBytes Loader Launch */
8090
8091 /******************* Bit definition for FLASH_AR register *******************/
8092 #define FLASH_AR_FAR_Pos (0U)
8093 #define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
8094 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
8095
8096 /****************** Bit definition for FLASH_OBR register *******************/
8097 #define FLASH_OBR_OPTERR_Pos (0U)
8098 #define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
8099 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
8100 #define FLASH_OBR_RDPRT_Pos (1U)
8101 #define FLASH_OBR_RDPRT_Msk (0x3U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000006 */
8102 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
8103 #define FLASH_OBR_RDPRT_1 (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
8104 #define FLASH_OBR_RDPRT_2 (0x3U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000006 */
8105
8106 #define FLASH_OBR_USER_Pos (8U)
8107 #define FLASH_OBR_USER_Msk (0x77U << FLASH_OBR_USER_Pos) /*!< 0x00007700 */
8108 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
8109 #define FLASH_OBR_IWDG_SW_Pos (8U)
8110 #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000100 */
8111 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
8112 #define FLASH_OBR_nRST_STOP_Pos (9U)
8113 #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */
8114 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
8115 #define FLASH_OBR_nRST_STDBY_Pos (10U)
8116 #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */
8117 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
8118 #define FLASH_OBR_nBOOT1_Pos (12U)
8119 #define FLASH_OBR_nBOOT1_Msk (0x1U << FLASH_OBR_nBOOT1_Pos) /*!< 0x00001000 */
8120 #define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /*!< nBOOT1 */
8121 #define FLASH_OBR_VDDA_MONITOR_Pos (13U)
8122 #define FLASH_OBR_VDDA_MONITOR_Msk (0x1U << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */
8123 #define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /*!< VDDA_MONITOR */
8124 #define FLASH_OBR_SRAM_PE_Pos (14U)
8125 #define FLASH_OBR_SRAM_PE_Msk (0x1U << FLASH_OBR_SRAM_PE_Pos) /*!< 0x00004000 */
8126 #define FLASH_OBR_SRAM_PE FLASH_OBR_SRAM_PE_Msk /*!< SRAM_PE */
8127 #define FLASH_OBR_DATA0_Pos (16U)
8128 #define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x00FF0000 */
8129 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
8130 #define FLASH_OBR_DATA1_Pos (24U)
8131 #define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0xFF000000 */
8132 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
8133
8134 /* Legacy defines */
8135 #define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
8136
8137 /****************** Bit definition for FLASH_WRPR register ******************/
8138 #define FLASH_WRPR_WRP_Pos (0U)
8139 #define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
8140 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
8141
8142 /*----------------------------------------------------------------------------*/
8143
8144 /****************** Bit definition for OB_RDP register **********************/
8145 #define OB_RDP_RDP_Pos (0U)
8146 #define OB_RDP_RDP_Msk (0xFFU << OB_RDP_RDP_Pos) /*!< 0x000000FF */
8147 #define OB_RDP_RDP OB_RDP_RDP_Msk /*!< Read protection option byte */
8148 #define OB_RDP_nRDP_Pos (8U)
8149 #define OB_RDP_nRDP_Msk (0xFFU << OB_RDP_nRDP_Pos) /*!< 0x0000FF00 */
8150 #define OB_RDP_nRDP OB_RDP_nRDP_Msk /*!< Read protection complemented option byte */
8151
8152 /****************** Bit definition for OB_USER register *********************/
8153 #define OB_USER_USER_Pos (16U)
8154 #define OB_USER_USER_Msk (0xFFU << OB_USER_USER_Pos) /*!< 0x00FF0000 */
8155 #define OB_USER_USER OB_USER_USER_Msk /*!< User option byte */
8156 #define OB_USER_nUSER_Pos (24U)
8157 #define OB_USER_nUSER_Msk (0xFFU << OB_USER_nUSER_Pos) /*!< 0xFF000000 */
8158 #define OB_USER_nUSER OB_USER_nUSER_Msk /*!< User complemented option byte */
8159
8160 /****************** Bit definition for FLASH_WRP0 register ******************/
8161 #define OB_WRP0_WRP0_Pos (0U)
8162 #define OB_WRP0_WRP0_Msk (0xFFU << OB_WRP0_WRP0_Pos) /*!< 0x000000FF */
8163 #define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
8164 #define OB_WRP0_nWRP0_Pos (8U)
8165 #define OB_WRP0_nWRP0_Msk (0xFFU << OB_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
8166 #define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
8167
8168 /****************** Bit definition for FLASH_WRP1 register ******************/
8169 #define OB_WRP1_WRP1_Pos (16U)
8170 #define OB_WRP1_WRP1_Msk (0xFFU << OB_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
8171 #define OB_WRP1_WRP1 OB_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
8172 #define OB_WRP1_nWRP1_Pos (24U)
8173 #define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
8174 #define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
8175
8176 /****************** Bit definition for FLASH_WRP2 register ******************/
8177 #define OB_WRP2_WRP2_Pos (0U)
8178 #define OB_WRP2_WRP2_Msk (0xFFU << OB_WRP2_WRP2_Pos) /*!< 0x000000FF */
8179 #define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
8180 #define OB_WRP2_nWRP2_Pos (8U)
8181 #define OB_WRP2_nWRP2_Msk (0xFFU << OB_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
8182 #define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
8183
8184 /****************** Bit definition for FLASH_WRP3 register ******************/
8185 #define OB_WRP3_WRP3_Pos (16U)
8186 #define OB_WRP3_WRP3_Msk (0xFFU << OB_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
8187 #define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
8188 #define OB_WRP3_nWRP3_Pos (24U)
8189 #define OB_WRP3_nWRP3_Msk (0xFFU << OB_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
8190 #define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
8191
8192 /******************************************************************************/
8193 /* */
8194 /* Flexible Memory Controller */
8195 /* */
8196 /******************************************************************************/
8197 /****************** Bit definition for FMC_BCRx register *******************/
8198 #define FMC_BCRx_MBKEN_Pos (0U)
8199 #define FMC_BCRx_MBKEN_Msk (0x1U << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
8200 #define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */
8201 #define FMC_BCRx_MUXEN_Pos (1U)
8202 #define FMC_BCRx_MUXEN_Msk (0x1U << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
8203 #define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */
8204
8205 #define FMC_BCRx_MTYP_Pos (2U)
8206 #define FMC_BCRx_MTYP_Msk (0x3U << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
8207 #define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
8208 #define FMC_BCRx_MTYP_0 (0x1U << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
8209 #define FMC_BCRx_MTYP_1 (0x2U << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
8210
8211 #define FMC_BCRx_MWID_Pos (4U)
8212 #define FMC_BCRx_MWID_Msk (0x3U << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
8213 #define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
8214 #define FMC_BCRx_MWID_0 (0x1U << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
8215 #define FMC_BCRx_MWID_1 (0x2U << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
8216
8217 #define FMC_BCRx_FACCEN_Pos (6U)
8218 #define FMC_BCRx_FACCEN_Msk (0x1U << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
8219 #define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */
8220 #define FMC_BCRx_BURSTEN_Pos (8U)
8221 #define FMC_BCRx_BURSTEN_Msk (0x1U << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
8222 #define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */
8223 #define FMC_BCRx_WAITPOL_Pos (9U)
8224 #define FMC_BCRx_WAITPOL_Msk (0x1U << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
8225 #define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */
8226 #define FMC_BCRx_WRAPMOD_Pos (10U)
8227 #define FMC_BCRx_WRAPMOD_Msk (0x1U << FMC_BCRx_WRAPMOD_Pos) /*!< 0x00000400 */
8228 #define FMC_BCRx_WRAPMOD FMC_BCRx_WRAPMOD_Msk /*!<Wrapped burst mode support */
8229 #define FMC_BCRx_WAITCFG_Pos (11U)
8230 #define FMC_BCRx_WAITCFG_Msk (0x1U << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
8231 #define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */
8232 #define FMC_BCRx_WREN_Pos (12U)
8233 #define FMC_BCRx_WREN_Msk (0x1U << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
8234 #define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */
8235 #define FMC_BCRx_WAITEN_Pos (13U)
8236 #define FMC_BCRx_WAITEN_Msk (0x1U << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
8237 #define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */
8238 #define FMC_BCRx_EXTMOD_Pos (14U)
8239 #define FMC_BCRx_EXTMOD_Msk (0x1U << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
8240 #define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */
8241 #define FMC_BCRx_ASYNCWAIT_Pos (15U)
8242 #define FMC_BCRx_ASYNCWAIT_Msk (0x1U << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
8243 #define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */
8244 #define FMC_BCRx_CBURSTRW_Pos (19U)
8245 #define FMC_BCRx_CBURSTRW_Msk (0x1U << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
8246 #define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */
8247
8248 /****************** Bit definition for FMC_BCR1 register *******************/
8249 #define FMC_BCR1_MBKEN_Pos (0U)
8250 #define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
8251 #define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
8252 #define FMC_BCR1_MUXEN_Pos (1U)
8253 #define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
8254 #define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
8255
8256 #define FMC_BCR1_MTYP_Pos (2U)
8257 #define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
8258 #define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
8259 #define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
8260 #define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
8261
8262 #define FMC_BCR1_MWID_Pos (4U)
8263 #define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
8264 #define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
8265 #define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
8266 #define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
8267
8268 #define FMC_BCR1_FACCEN_Pos (6U)
8269 #define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
8270 #define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
8271 #define FMC_BCR1_BURSTEN_Pos (8U)
8272 #define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
8273 #define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
8274 #define FMC_BCR1_WAITPOL_Pos (9U)
8275 #define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
8276 #define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
8277 #define FMC_BCR1_WRAPMOD_Pos (10U)
8278 #define FMC_BCR1_WRAPMOD_Msk (0x1U << FMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
8279 #define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
8280 #define FMC_BCR1_WAITCFG_Pos (11U)
8281 #define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
8282 #define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
8283 #define FMC_BCR1_WREN_Pos (12U)
8284 #define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
8285 #define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
8286 #define FMC_BCR1_WAITEN_Pos (13U)
8287 #define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
8288 #define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
8289 #define FMC_BCR1_EXTMOD_Pos (14U)
8290 #define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
8291 #define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
8292 #define FMC_BCR1_ASYNCWAIT_Pos (15U)
8293 #define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
8294 #define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
8295 #define FMC_BCR1_CBURSTRW_Pos (19U)
8296 #define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
8297 #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
8298 #define FMC_BCR1_CCLKEN_Pos (20U)
8299 #define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
8300 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
8301
8302 /****************** Bit definition for FMC_BCR2 register *******************/
8303 #define FMC_BCR2_MBKEN_Pos (0U)
8304 #define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
8305 #define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
8306 #define FMC_BCR2_MUXEN_Pos (1U)
8307 #define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
8308 #define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
8309
8310 #define FMC_BCR2_MTYP_Pos (2U)
8311 #define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
8312 #define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
8313 #define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
8314 #define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
8315
8316 #define FMC_BCR2_MWID_Pos (4U)
8317 #define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
8318 #define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
8319 #define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
8320 #define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
8321
8322 #define FMC_BCR2_FACCEN_Pos (6U)
8323 #define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
8324 #define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
8325 #define FMC_BCR2_BURSTEN_Pos (8U)
8326 #define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
8327 #define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
8328 #define FMC_BCR2_WAITPOL_Pos (9U)
8329 #define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
8330 #define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
8331 #define FMC_BCR2_WRAPMOD_Pos (10U)
8332 #define FMC_BCR2_WRAPMOD_Msk (0x1U << FMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
8333 #define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
8334 #define FMC_BCR2_WAITCFG_Pos (11U)
8335 #define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
8336 #define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
8337 #define FMC_BCR2_WREN_Pos (12U)
8338 #define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
8339 #define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
8340 #define FMC_BCR2_WAITEN_Pos (13U)
8341 #define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
8342 #define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
8343 #define FMC_BCR2_EXTMOD_Pos (14U)
8344 #define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
8345 #define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
8346 #define FMC_BCR2_ASYNCWAIT_Pos (15U)
8347 #define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
8348 #define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
8349 #define FMC_BCR2_CBURSTRW_Pos (19U)
8350 #define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
8351 #define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
8352
8353 /****************** Bit definition for FMC_BCR3 register *******************/
8354 #define FMC_BCR3_MBKEN_Pos (0U)
8355 #define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
8356 #define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
8357 #define FMC_BCR3_MUXEN_Pos (1U)
8358 #define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
8359 #define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
8360
8361 #define FMC_BCR3_MTYP_Pos (2U)
8362 #define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
8363 #define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
8364 #define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
8365 #define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
8366
8367 #define FMC_BCR3_MWID_Pos (4U)
8368 #define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
8369 #define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
8370 #define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
8371 #define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
8372
8373 #define FMC_BCR3_FACCEN_Pos (6U)
8374 #define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
8375 #define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
8376 #define FMC_BCR3_BURSTEN_Pos (8U)
8377 #define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
8378 #define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
8379 #define FMC_BCR3_WAITPOL_Pos (9U)
8380 #define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
8381 #define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
8382 #define FMC_BCR3_WRAPMOD_Pos (10U)
8383 #define FMC_BCR3_WRAPMOD_Msk (0x1U << FMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
8384 #define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
8385 #define FMC_BCR3_WAITCFG_Pos (11U)
8386 #define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
8387 #define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
8388 #define FMC_BCR3_WREN_Pos (12U)
8389 #define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
8390 #define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
8391 #define FMC_BCR3_WAITEN_Pos (13U)
8392 #define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
8393 #define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
8394 #define FMC_BCR3_EXTMOD_Pos (14U)
8395 #define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
8396 #define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
8397 #define FMC_BCR3_ASYNCWAIT_Pos (15U)
8398 #define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
8399 #define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
8400 #define FMC_BCR3_CBURSTRW_Pos (19U)
8401 #define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
8402 #define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
8403
8404 /****************** Bit definition for FMC_BCR4 register *******************/
8405 #define FMC_BCR4_MBKEN_Pos (0U)
8406 #define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
8407 #define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
8408 #define FMC_BCR4_MUXEN_Pos (1U)
8409 #define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
8410 #define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
8411
8412 #define FMC_BCR4_MTYP_Pos (2U)
8413 #define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
8414 #define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
8415 #define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
8416 #define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
8417
8418 #define FMC_BCR4_MWID_Pos (4U)
8419 #define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
8420 #define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
8421 #define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
8422 #define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
8423
8424 #define FMC_BCR4_FACCEN_Pos (6U)
8425 #define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
8426 #define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
8427 #define FMC_BCR4_BURSTEN_Pos (8U)
8428 #define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
8429 #define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
8430 #define FMC_BCR4_WAITPOL_Pos (9U)
8431 #define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
8432 #define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
8433 #define FMC_BCR4_WRAPMOD_Pos (10U)
8434 #define FMC_BCR4_WRAPMOD_Msk (0x1U << FMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
8435 #define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
8436 #define FMC_BCR4_WAITCFG_Pos (11U)
8437 #define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
8438 #define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
8439 #define FMC_BCR4_WREN_Pos (12U)
8440 #define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
8441 #define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
8442 #define FMC_BCR4_WAITEN_Pos (13U)
8443 #define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
8444 #define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
8445 #define FMC_BCR4_EXTMOD_Pos (14U)
8446 #define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
8447 #define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
8448 #define FMC_BCR4_ASYNCWAIT_Pos (15U)
8449 #define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
8450 #define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
8451 #define FMC_BCR4_CBURSTRW_Pos (19U)
8452 #define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
8453 #define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
8454
8455 /****************** Bit definition for FMC_BTRx register ******************/
8456 #define FMC_BTRx_ADDSET_Pos (0U)
8457 #define FMC_BTRx_ADDSET_Msk (0xFU << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
8458 #define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8459 #define FMC_BTRx_ADDSET_0 (0x1U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
8460 #define FMC_BTRx_ADDSET_1 (0x2U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
8461 #define FMC_BTRx_ADDSET_2 (0x4U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
8462 #define FMC_BTR_ADDSET_3 (0x00000008U) /*!<Bit 3 */
8463
8464 #define FMC_BTRx_ADDHLD_Pos (4U)
8465 #define FMC_BTRx_ADDHLD_Msk (0xFU << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
8466 #define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8467 #define FMC_BTRx_ADDHLD_0 (0x1U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
8468 #define FMC_BTRx_ADDHLD_1 (0x2U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
8469 #define FMC_BTRx_ADDHLD_2 (0x4U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
8470 #define FMC_BTRx_ADDHLD_3 (0x8U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
8471
8472 #define FMC_BTRx_DATAST_Pos (8U)
8473 #define FMC_BTRx_DATAST_Msk (0xFFU << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
8474 #define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8475 #define FMC_BTR_DATAST_0 (0x00000100U) /*!<Bit 0 */
8476 #define FMC_BTRx_DATAST_1 (0x00000200U) /*!<Bit 1 */
8477 #define FMC_BTRx_DATAST_2 (0x00000400U) /*!<Bit 2 */
8478 #define FMC_BTRx_DATAST_3 (0x00000800U) /*!<Bit 3 */
8479 #define FMC_BTRx_DATAST_4 (0x00001000U) /*!<Bit 4 */
8480 #define FMC_BTRx_DATAST_5 (0x00002000U) /*!<Bit 5 */
8481 #define FMC_BTRx_DATAST_6 (0x00004000U) /*!<Bit 6 */
8482 #define FMC_BTRx_DATAST_7 (0x00008000U) /*!<Bit 7 */
8483
8484 #define FMC_BTRx_BUSTURN_Pos (16U)
8485 #define FMC_BTRx_BUSTURN_Msk (0xFU << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
8486 #define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
8487 #define FMC_BTRx_BUSTURN_0 (0x1U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
8488 #define FMC_BTRx_BUSTURN_1 (0x2U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
8489 #define FMC_BTRx_BUSTURN_2 (0x4U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
8490 #define FMC_BTRx_BUSTURN_3 (0x8U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
8491
8492 #define FMC_BTRx_CLKDIV_Pos (20U)
8493 #define FMC_BTRx_CLKDIV_Msk (0xFU << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
8494 #define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
8495 #define FMC_BTRx_CLKDIV_0 (0x1U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
8496 #define FMC_BTRx_CLKDIV_1 (0x2U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
8497 #define FMC_BTRx_CLKDIV_2 (0x4U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
8498 #define FMC_BTRx_CLKDIV_3 (0x8U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
8499
8500 #define FMC_BTRx_DATLAT_Pos (24U)
8501 #define FMC_BTRx_DATLAT_Msk (0xFU << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
8502 #define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
8503 #define FMC_BTRx_DATLAT_0 (0x1U << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
8504 #define FMC_BTRx_DATLAT_1 (0x2U << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
8505 #define FMC_BTRx_DATLAT_2 (0x4U << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
8506 #define FMC_BTRx_DATLAT_3 (0x8U << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
8507
8508 #define FMC_BTRx_ACCMOD_Pos (28U)
8509 #define FMC_BTRx_ACCMOD_Msk (0x3U << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
8510 #define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8511 #define FMC_BTRx_ACCMOD_0 (0x1U << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
8512 #define FMC_BTRx_ACCMOD_1 (0x2U << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
8513
8514 /****************** Bit definition for FMC_BTR1 register ******************/
8515 #define FMC_BTR1_ADDSET_Pos (0U)
8516 #define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
8517 #define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8518 #define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
8519 #define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
8520 #define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
8521 #define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
8522
8523 #define FMC_BTR1_ADDHLD_Pos (4U)
8524 #define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
8525 #define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8526 #define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
8527 #define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
8528 #define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
8529 #define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
8530
8531 #define FMC_BTR1_DATAST_Pos (8U)
8532 #define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
8533 #define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8534 #define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
8535 #define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
8536 #define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
8537 #define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
8538 #define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
8539 #define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
8540 #define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
8541 #define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
8542
8543 #define FMC_BTR1_BUSTURN_Pos (16U)
8544 #define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
8545 #define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
8546 #define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
8547 #define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
8548 #define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
8549 #define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
8550
8551 #define FMC_BTR1_CLKDIV_Pos (20U)
8552 #define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
8553 #define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
8554 #define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
8555 #define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
8556 #define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
8557 #define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
8558
8559 #define FMC_BTR1_DATLAT_Pos (24U)
8560 #define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
8561 #define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
8562 #define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
8563 #define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
8564 #define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
8565 #define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
8566
8567 #define FMC_BTR1_ACCMOD_Pos (28U)
8568 #define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
8569 #define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8570 #define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
8571 #define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
8572
8573 /****************** Bit definition for FMC_BTR2 register *******************/
8574 #define FMC_BTR2_ADDSET_Pos (0U)
8575 #define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
8576 #define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8577 #define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
8578 #define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
8579 #define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
8580 #define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
8581
8582 #define FMC_BTR2_ADDHLD_Pos (4U)
8583 #define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
8584 #define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8585 #define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
8586 #define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
8587 #define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
8588 #define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
8589
8590 #define FMC_BTR2_DATAST_Pos (8U)
8591 #define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
8592 #define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8593 #define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
8594 #define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
8595 #define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
8596 #define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
8597 #define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
8598 #define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
8599 #define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
8600 #define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
8601
8602 #define FMC_BTR2_BUSTURN_Pos (16U)
8603 #define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
8604 #define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
8605 #define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
8606 #define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
8607 #define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
8608 #define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
8609
8610 #define FMC_BTR2_CLKDIV_Pos (20U)
8611 #define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
8612 #define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
8613 #define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
8614 #define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
8615 #define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
8616 #define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
8617
8618 #define FMC_BTR2_DATLAT_Pos (24U)
8619 #define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
8620 #define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
8621 #define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
8622 #define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
8623 #define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
8624 #define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
8625
8626 #define FMC_BTR2_ACCMOD_Pos (28U)
8627 #define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
8628 #define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8629 #define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
8630 #define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
8631
8632 /******************* Bit definition for FMC_BTR3 register *******************/
8633 #define FMC_BTR3_ADDSET_Pos (0U)
8634 #define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
8635 #define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8636 #define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
8637 #define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
8638 #define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
8639 #define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
8640
8641 #define FMC_BTR3_ADDHLD_Pos (4U)
8642 #define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
8643 #define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8644 #define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
8645 #define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
8646 #define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
8647 #define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
8648
8649 #define FMC_BTR3_DATAST_Pos (8U)
8650 #define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
8651 #define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8652 #define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
8653 #define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
8654 #define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
8655 #define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
8656 #define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
8657 #define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
8658 #define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
8659 #define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
8660
8661 #define FMC_BTR3_BUSTURN_Pos (16U)
8662 #define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
8663 #define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
8664 #define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
8665 #define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
8666 #define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
8667 #define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
8668
8669 #define FMC_BTR3_CLKDIV_Pos (20U)
8670 #define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
8671 #define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
8672 #define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
8673 #define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
8674 #define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
8675 #define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
8676
8677 #define FMC_BTR3_DATLAT_Pos (24U)
8678 #define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
8679 #define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
8680 #define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
8681 #define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
8682 #define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
8683 #define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
8684
8685 #define FMC_BTR3_ACCMOD_Pos (28U)
8686 #define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
8687 #define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8688 #define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
8689 #define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
8690
8691 /****************** Bit definition for FMC_BTR4 register *******************/
8692 #define FMC_BTR4_ADDSET_Pos (0U)
8693 #define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
8694 #define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8695 #define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
8696 #define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
8697 #define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
8698 #define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
8699
8700 #define FMC_BTR4_ADDHLD_Pos (4U)
8701 #define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
8702 #define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8703 #define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
8704 #define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
8705 #define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
8706 #define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
8707
8708 #define FMC_BTR4_DATAST_Pos (8U)
8709 #define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
8710 #define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8711 #define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
8712 #define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
8713 #define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
8714 #define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
8715 #define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
8716 #define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
8717 #define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
8718 #define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
8719
8720 #define FMC_BTR4_BUSTURN_Pos (16U)
8721 #define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
8722 #define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
8723 #define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
8724 #define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
8725 #define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
8726 #define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
8727
8728 #define FMC_BTR4_CLKDIV_Pos (20U)
8729 #define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
8730 #define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
8731 #define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
8732 #define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
8733 #define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
8734 #define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
8735
8736 #define FMC_BTR4_DATLAT_Pos (24U)
8737 #define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
8738 #define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
8739 #define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
8740 #define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
8741 #define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
8742 #define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
8743
8744 #define FMC_BTR4_ACCMOD_Pos (28U)
8745 #define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
8746 #define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8747 #define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
8748 #define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
8749
8750 /****************** Bit definition for FMC_BWTRx register ******************/
8751 #define FMC_BWTRx_ADDSET_Pos (0U)
8752 #define FMC_BWTRx_ADDSET_Msk (0xFU << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
8753 #define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8754 #define FMC_BWTRx_ADDSET_0 (0x1U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
8755 #define FMC_BWTRx_ADDSET_1 (0x2U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
8756 #define FMC_BWTRx_ADDSET_2 (0x4U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
8757 #define FMC_BWTRx_ADDSET_3 (0x8U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
8758
8759 #define FMC_BWTRx_ADDHLD_Pos (4U)
8760 #define FMC_BWTRx_ADDHLD_Msk (0xFU << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
8761 #define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8762 #define FMC_BWTRx_ADDHLD_0 (0x1U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
8763 #define FMC_BWTRx_ADDHLD_1 (0x2U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
8764 #define FMC_BWTRx_ADDHLD_2 (0x4U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
8765 #define FMC_BWTRx_ADDHLD_3 (0x8U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
8766
8767 #define FMC_BWTRx_DATAST_Pos (8U)
8768 #define FMC_BWTRx_DATAST_Msk (0xFFU << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
8769 #define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8770 #define FMC_BWTRx_DATAST_0 (0x01U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
8771 #define FMC_BWTRx_DATAST_1 (0x02U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
8772 #define FMC_BWTRx_DATAST_2 (0x04U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
8773 #define FMC_BWTRx_DATAST_3 (0x08U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
8774 #define FMC_BWTRx_DATAST_4 (0x10U << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
8775 #define FMC_BWTRx_DATAST_5 (0x20U << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
8776 #define FMC_BWTRx_DATAST_6 (0x40U << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
8777 #define FMC_BWTRx_DATAST_7 (0x80U << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
8778
8779 #define FMC_BWTRx_ACCMOD_Pos (28U)
8780 #define FMC_BWTRx_ACCMOD_Msk (0x3U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
8781 #define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8782 #define FMC_BWTRx_ACCMOD_0 (0x1U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
8783 #define FMC_BWTRx_ACCMOD_1 (0x2U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
8784
8785 /* Old Bit definition for FMC_BWTRx register maintained for legacy purpose */
8786 #define FMC_BWTRx_ADDSETx FMC_BWTRx_ADDSET
8787 #define FMC_BWTRx_ADDSETx_0 FMC_BWTRx_ADDSET_0
8788 #define FMC_BWTRx_ADDSETx_1 FMC_BWTRx_ADDSET_1
8789 #define FMC_BWTRx_ADDSETx_2 FMC_BWTRx_ADDSET_2
8790 #define FMC_BWTRx_ADDSETx_3 FMC_BWTRx_ADDSET_3
8791
8792 #define FMC_BWTRx_ADDHLDx FMC_BWTRx_ADDHLD
8793 #define FMC_BWTRx_ADDHLDx_0 FMC_BWTRx_ADDHLD_0
8794 #define FMC_BWTRx_ADDHLDx_1 FMC_BWTRx_ADDHLD_1
8795 #define FMC_BWTRx_ADDHLDx_2 FMC_BWTRx_ADDHLD_2
8796 #define FMC_BWTRx_ADDHLDx_3 FMC_BWTRx_ADDHLD_3
8797
8798 #define FMC_BWTRx_DATASTx FMC_BWTRx_DATAST
8799 #define FMC_BWTRx_DATASTx_0 FMC_BWTRx_DATAST_0
8800 #define FMC_BWTRx_DATASTx_1 FMC_BWTRx_DATAST_1
8801 #define FMC_BWTRx_DATASTx_2 FMC_BWTRx_DATAST_2
8802 #define FMC_BWTRx_DATASTx_3 FMC_BWTRx_DATAST_3
8803 #define FMC_BWTRx_DATASTx_4 FMC_BWTRx_DATAST_4
8804 #define FMC_BWTRx_DATASTx_5 FMC_BWTRx_DATAST_5
8805 #define FMC_BWTRx_DATASTx_6 FMC_BWTRx_DATAST_6
8806 #define FMC_BWTRx_DATASTx_7 FMC_BWTRx_DATAST_7
8807
8808 #define FMC_BWTRx_ACCMODx FMC_BWTRx_ACCMOD
8809 #define FMC_BWTRx_ACCMODx_0 FMC_BWTRx_ACCMOD_0
8810 #define FMC_BWTRx_ACCMODx_1 FMC_BWTRx_ACCMOD_1
8811
8812 /****************** Bit definition for FMC_BWTR1 register ******************/
8813 #define FMC_BWTR1_ADDSET_Pos (0U)
8814 #define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
8815 #define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8816 #define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
8817 #define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
8818 #define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
8819 #define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
8820
8821 #define FMC_BWTR1_ADDHLD_Pos (4U)
8822 #define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
8823 #define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8824 #define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
8825 #define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
8826 #define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
8827 #define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
8828
8829 #define FMC_BWTR1_DATAST_Pos (8U)
8830 #define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
8831 #define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8832 #define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
8833 #define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
8834 #define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
8835 #define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
8836 #define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
8837 #define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
8838 #define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
8839 #define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
8840
8841 #define FMC_BWTR1_CLKDIV_Pos (20U)
8842 #define FMC_BWTR1_CLKDIV_Msk (0xFU << FMC_BWTR1_CLKDIV_Pos) /*!< 0x00F00000 */
8843 #define FMC_BWTR1_CLKDIV FMC_BWTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
8844 #define FMC_BWTR1_CLKDIV_0 (0x1U << FMC_BWTR1_CLKDIV_Pos) /*!< 0x00100000 */
8845 #define FMC_BWTR1_CLKDIV_1 (0x2U << FMC_BWTR1_CLKDIV_Pos) /*!< 0x00200000 */
8846 #define FMC_BWTR1_CLKDIV_2 (0x4U << FMC_BWTR1_CLKDIV_Pos) /*!< 0x00400000 */
8847 #define FMC_BWTR1_CLKDIV_3 (0x8U << FMC_BWTR1_CLKDIV_Pos) /*!< 0x00800000 */
8848
8849 #define FMC_BWTR1_DATLAT_Pos (24U)
8850 #define FMC_BWTR1_DATLAT_Msk (0xFU << FMC_BWTR1_DATLAT_Pos) /*!< 0x0F000000 */
8851 #define FMC_BWTR1_DATLAT FMC_BWTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
8852 #define FMC_BWTR1_DATLAT_0 (0x1U << FMC_BWTR1_DATLAT_Pos) /*!< 0x01000000 */
8853 #define FMC_BWTR1_DATLAT_1 (0x2U << FMC_BWTR1_DATLAT_Pos) /*!< 0x02000000 */
8854 #define FMC_BWTR1_DATLAT_2 (0x4U << FMC_BWTR1_DATLAT_Pos) /*!< 0x04000000 */
8855 #define FMC_BWTR1_DATLAT_3 (0x8U << FMC_BWTR1_DATLAT_Pos) /*!< 0x08000000 */
8856
8857 #define FMC_BWTR1_ACCMOD_Pos (28U)
8858 #define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
8859 #define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8860 #define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
8861 #define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
8862
8863 /****************** Bit definition for FMC_BWTR2 register ******************/
8864 #define FMC_BWTR2_ADDSET_Pos (0U)
8865 #define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
8866 #define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8867 #define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
8868 #define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
8869 #define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
8870 #define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
8871
8872 #define FMC_BWTR2_ADDHLD_Pos (4U)
8873 #define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
8874 #define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8875 #define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
8876 #define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
8877 #define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
8878 #define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
8879
8880 #define FMC_BWTR2_DATAST_Pos (8U)
8881 #define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
8882 #define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8883 #define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
8884 #define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
8885 #define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
8886 #define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
8887 #define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
8888 #define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
8889 #define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
8890 #define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
8891
8892 #define FMC_BWTR2_CLKDIV_Pos (20U)
8893 #define FMC_BWTR2_CLKDIV_Msk (0xFU << FMC_BWTR2_CLKDIV_Pos) /*!< 0x00F00000 */
8894 #define FMC_BWTR2_CLKDIV FMC_BWTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
8895 #define FMC_BWTR2_CLKDIV_0 (0x1U << FMC_BWTR2_CLKDIV_Pos) /*!< 0x00100000 */
8896 #define FMC_BWTR2_CLKDIV_1 (0x2U << FMC_BWTR2_CLKDIV_Pos) /*!< 0x00200000 */
8897 #define FMC_BWTR2_CLKDIV_2 (0x4U << FMC_BWTR2_CLKDIV_Pos) /*!< 0x00400000 */
8898 #define FMC_BWTR2_CLKDIV_3 (0x8U << FMC_BWTR2_CLKDIV_Pos) /*!< 0x00800000 */
8899
8900 #define FMC_BWTR2_DATLAT_Pos (24U)
8901 #define FMC_BWTR2_DATLAT_Msk (0xFU << FMC_BWTR2_DATLAT_Pos) /*!< 0x0F000000 */
8902 #define FMC_BWTR2_DATLAT FMC_BWTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
8903 #define FMC_BWTR2_DATLAT_0 (0x1U << FMC_BWTR2_DATLAT_Pos) /*!< 0x01000000 */
8904 #define FMC_BWTR2_DATLAT_1 (0x2U << FMC_BWTR2_DATLAT_Pos) /*!< 0x02000000 */
8905 #define FMC_BWTR2_DATLAT_2 (0x4U << FMC_BWTR2_DATLAT_Pos) /*!< 0x04000000 */
8906 #define FMC_BWTR2_DATLAT_3 (0x8U << FMC_BWTR2_DATLAT_Pos) /*!< 0x08000000 */
8907
8908 #define FMC_BWTR2_ACCMOD_Pos (28U)
8909 #define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
8910 #define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8911 #define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
8912 #define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
8913
8914 /****************** Bit definition for FMC_BWTR3 register ******************/
8915 #define FMC_BWTR3_ADDSET_Pos (0U)
8916 #define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
8917 #define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8918 #define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
8919 #define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
8920 #define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
8921 #define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
8922
8923 #define FMC_BWTR3_ADDHLD_Pos (4U)
8924 #define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
8925 #define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8926 #define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
8927 #define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
8928 #define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
8929 #define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
8930
8931 #define FMC_BWTR3_DATAST_Pos (8U)
8932 #define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
8933 #define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8934 #define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
8935 #define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
8936 #define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
8937 #define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
8938 #define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
8939 #define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
8940 #define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
8941 #define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
8942
8943 #define FMC_BWTR3_CLKDIV_Pos (20U)
8944 #define FMC_BWTR3_CLKDIV_Msk (0xFU << FMC_BWTR3_CLKDIV_Pos) /*!< 0x00F00000 */
8945 #define FMC_BWTR3_CLKDIV FMC_BWTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
8946 #define FMC_BWTR3_CLKDIV_0 (0x1U << FMC_BWTR3_CLKDIV_Pos) /*!< 0x00100000 */
8947 #define FMC_BWTR3_CLKDIV_1 (0x2U << FMC_BWTR3_CLKDIV_Pos) /*!< 0x00200000 */
8948 #define FMC_BWTR3_CLKDIV_2 (0x4U << FMC_BWTR3_CLKDIV_Pos) /*!< 0x00400000 */
8949 #define FMC_BWTR3_CLKDIV_3 (0x8U << FMC_BWTR3_CLKDIV_Pos) /*!< 0x00800000 */
8950
8951 #define FMC_BWTR3_DATLAT_Pos (24U)
8952 #define FMC_BWTR3_DATLAT_Msk (0xFU << FMC_BWTR3_DATLAT_Pos) /*!< 0x0F000000 */
8953 #define FMC_BWTR3_DATLAT FMC_BWTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
8954 #define FMC_BWTR3_DATLAT_0 (0x1U << FMC_BWTR3_DATLAT_Pos) /*!< 0x01000000 */
8955 #define FMC_BWTR3_DATLAT_1 (0x2U << FMC_BWTR3_DATLAT_Pos) /*!< 0x02000000 */
8956 #define FMC_BWTR3_DATLAT_2 (0x4U << FMC_BWTR3_DATLAT_Pos) /*!< 0x04000000 */
8957 #define FMC_BWTR3_DATLAT_3 (0x8U << FMC_BWTR3_DATLAT_Pos) /*!< 0x08000000 */
8958
8959 #define FMC_BWTR3_ACCMOD_Pos (28U)
8960 #define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
8961 #define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8962 #define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
8963 #define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
8964
8965 /****************** Bit definition for FMC_BWTR4 register ******************/
8966 #define FMC_BWTR4_ADDSET_Pos (0U)
8967 #define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
8968 #define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8969 #define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
8970 #define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
8971 #define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
8972 #define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
8973
8974 #define FMC_BWTR4_ADDHLD_Pos (4U)
8975 #define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
8976 #define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8977 #define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
8978 #define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
8979 #define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
8980 #define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
8981
8982 #define FMC_BWTR4_DATAST_Pos (8U)
8983 #define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
8984 #define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8985 #define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
8986 #define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
8987 #define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
8988 #define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
8989 #define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
8990 #define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
8991 #define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
8992 #define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
8993
8994 #define FMC_BWTR4_CLKDIV_Pos (20U)
8995 #define FMC_BWTR4_CLKDIV_Msk (0xFU << FMC_BWTR4_CLKDIV_Pos) /*!< 0x00F00000 */
8996 #define FMC_BWTR4_CLKDIV FMC_BWTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
8997 #define FMC_BWTR4_CLKDIV_0 (0x1U << FMC_BWTR4_CLKDIV_Pos) /*!< 0x00100000 */
8998 #define FMC_BWTR4_CLKDIV_1 (0x2U << FMC_BWTR4_CLKDIV_Pos) /*!< 0x00200000 */
8999 #define FMC_BWTR4_CLKDIV_2 (0x4U << FMC_BWTR4_CLKDIV_Pos) /*!< 0x00400000 */
9000 #define FMC_BWTR4_CLKDIV_3 (0x8U << FMC_BWTR4_CLKDIV_Pos) /*!< 0x00800000 */
9001
9002 #define FMC_BWTR4_DATLAT_Pos (24U)
9003 #define FMC_BWTR4_DATLAT_Msk (0xFU << FMC_BWTR4_DATLAT_Pos) /*!< 0x0F000000 */
9004 #define FMC_BWTR4_DATLAT FMC_BWTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
9005 #define FMC_BWTR4_DATLAT_0 (0x1U << FMC_BWTR4_DATLAT_Pos) /*!< 0x01000000 */
9006 #define FMC_BWTR4_DATLAT_1 (0x2U << FMC_BWTR4_DATLAT_Pos) /*!< 0x02000000 */
9007 #define FMC_BWTR4_DATLAT_2 (0x4U << FMC_BWTR4_DATLAT_Pos) /*!< 0x04000000 */
9008 #define FMC_BWTR4_DATLAT_3 (0x8U << FMC_BWTR4_DATLAT_Pos) /*!< 0x08000000 */
9009
9010 #define FMC_BWTR4_ACCMOD_Pos (28U)
9011 #define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
9012 #define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
9013 #define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
9014 #define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
9015
9016 /****************** Bit definition for FMC_PCRx register *******************/
9017 #define FMC_PCRx_PWAITEN_Pos (1U)
9018 #define FMC_PCRx_PWAITEN_Msk (0x1U << FMC_PCRx_PWAITEN_Pos) /*!< 0x00000002 */
9019 #define FMC_PCRx_PWAITEN FMC_PCRx_PWAITEN_Msk /*!<Wait feature enable bit */
9020 #define FMC_PCRx_PBKEN_Pos (2U)
9021 #define FMC_PCRx_PBKEN_Msk (0x1U << FMC_PCRx_PBKEN_Pos) /*!< 0x00000004 */
9022 #define FMC_PCRx_PBKEN FMC_PCRx_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
9023 #define FMC_PCRx_PTYP_Pos (3U)
9024 #define FMC_PCRx_PTYP_Msk (0x1U << FMC_PCRx_PTYP_Pos) /*!< 0x00000008 */
9025 #define FMC_PCRx_PTYP FMC_PCRx_PTYP_Msk /*!<Memory type */
9026
9027 #define FMC_PCRx_PWID_Pos (4U)
9028 #define FMC_PCRx_PWID_Msk (0x3U << FMC_PCRx_PWID_Pos) /*!< 0x00000030 */
9029 #define FMC_PCRx_PWID FMC_PCRx_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
9030 #define FMC_PCRx_PWID_0 (0x1U << FMC_PCRx_PWID_Pos) /*!< 0x00000010 */
9031 #define FMC_PCRx_PWID_1 (0x2U << FMC_PCRx_PWID_Pos) /*!< 0x00000020 */
9032
9033 #define FMC_PCRx_ECCEN_Pos (6U)
9034 #define FMC_PCRx_ECCEN_Msk (0x1U << FMC_PCRx_ECCEN_Pos) /*!< 0x00000040 */
9035 #define FMC_PCRx_ECCEN FMC_PCRx_ECCEN_Msk /*!<ECC computation logic enable bit */
9036
9037 #define FMC_PCRx_TCLR_Pos (9U)
9038 #define FMC_PCRx_TCLR_Msk (0xFU << FMC_PCRx_TCLR_Pos) /*!< 0x00001E00 */
9039 #define FMC_PCRx_TCLR FMC_PCRx_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
9040 #define FMC_PCRx_TCLR_0 (0x1U << FMC_PCRx_TCLR_Pos) /*!< 0x00000200 */
9041 #define FMC_PCRx_TCLR_1 (0x2U << FMC_PCRx_TCLR_Pos) /*!< 0x00000400 */
9042 #define FMC_PCRx_TCLR_2 (0x4U << FMC_PCRx_TCLR_Pos) /*!< 0x00000800 */
9043 #define FMC_PCRx_TCLR_3 (0x8U << FMC_PCRx_TCLR_Pos) /*!< 0x00001000 */
9044
9045 #define FMC_PCRx_TAR_Pos (13U)
9046 #define FMC_PCRx_TAR_Msk (0xFU << FMC_PCRx_TAR_Pos) /*!< 0x0001E000 */
9047 #define FMC_PCRx_TAR FMC_PCRx_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
9048 #define FMC_PCRx_TAR_0 (0x1U << FMC_PCRx_TAR_Pos) /*!< 0x00002000 */
9049 #define FMC_PCRx_TAR_1 (0x2U << FMC_PCRx_TAR_Pos) /*!< 0x00004000 */
9050 #define FMC_PCRx_TAR_2 (0x4U << FMC_PCRx_TAR_Pos) /*!< 0x00008000 */
9051 #define FMC_PCRx_TAR_3 (0x8U << FMC_PCRx_TAR_Pos) /*!< 0x00010000 */
9052
9053 #define FMC_PCRx_ECCPS_Pos (17U)
9054 #define FMC_PCRx_ECCPS_Msk (0x7U << FMC_PCRx_ECCPS_Pos) /*!< 0x000E0000 */
9055 #define FMC_PCRx_ECCPS FMC_PCRx_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
9056 #define FMC_PCRx_ECCPS_0 (0x1U << FMC_PCRx_ECCPS_Pos) /*!< 0x00020000 */
9057 #define FMC_PCRx_ECCPS_1 (0x2U << FMC_PCRx_ECCPS_Pos) /*!< 0x00040000 */
9058 #define FMC_PCRx_ECCPS_2 (0x4U << FMC_PCRx_ECCPS_Pos) /*!< 0x00080000 */
9059
9060 /****************** Bit definition for FMC_PCR2 register *******************/
9061 #define FMC_PCR2_PWAITEN_Pos (1U)
9062 #define FMC_PCR2_PWAITEN_Msk (0x1U << FMC_PCR2_PWAITEN_Pos) /*!< 0x00000002 */
9063 #define FMC_PCR2_PWAITEN FMC_PCR2_PWAITEN_Msk /*!<Wait feature enable bit */
9064 #define FMC_PCR2_PBKEN_Pos (2U)
9065 #define FMC_PCR2_PBKEN_Msk (0x1U << FMC_PCR2_PBKEN_Pos) /*!< 0x00000004 */
9066 #define FMC_PCR2_PBKEN FMC_PCR2_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
9067 #define FMC_PCR2_PTYP_Pos (3U)
9068 #define FMC_PCR2_PTYP_Msk (0x1U << FMC_PCR2_PTYP_Pos) /*!< 0x00000008 */
9069 #define FMC_PCR2_PTYP FMC_PCR2_PTYP_Msk /*!<Memory type */
9070
9071 #define FMC_PCR2_PWID_Pos (4U)
9072 #define FMC_PCR2_PWID_Msk (0x3U << FMC_PCR2_PWID_Pos) /*!< 0x00000030 */
9073 #define FMC_PCR2_PWID FMC_PCR2_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
9074 #define FMC_PCR2_PWID_0 (0x1U << FMC_PCR2_PWID_Pos) /*!< 0x00000010 */
9075 #define FMC_PCR2_PWID_1 (0x2U << FMC_PCR2_PWID_Pos) /*!< 0x00000020 */
9076
9077 #define FMC_PCR2_ECCEN_Pos (6U)
9078 #define FMC_PCR2_ECCEN_Msk (0x1U << FMC_PCR2_ECCEN_Pos) /*!< 0x00000040 */
9079 #define FMC_PCR2_ECCEN FMC_PCR2_ECCEN_Msk /*!<ECC computation logic enable bit */
9080
9081 #define FMC_PCR2_TCLR_Pos (9U)
9082 #define FMC_PCR2_TCLR_Msk (0xFU << FMC_PCR2_TCLR_Pos) /*!< 0x00001E00 */
9083 #define FMC_PCR2_TCLR FMC_PCR2_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
9084 #define FMC_PCR2_TCLR_0 (0x1U << FMC_PCR2_TCLR_Pos) /*!< 0x00000200 */
9085 #define FMC_PCR2_TCLR_1 (0x2U << FMC_PCR2_TCLR_Pos) /*!< 0x00000400 */
9086 #define FMC_PCR2_TCLR_2 (0x4U << FMC_PCR2_TCLR_Pos) /*!< 0x00000800 */
9087 #define FMC_PCR2_TCLR_3 (0x8U << FMC_PCR2_TCLR_Pos) /*!< 0x00001000 */
9088
9089 #define FMC_PCR2_TAR_Pos (13U)
9090 #define FMC_PCR2_TAR_Msk (0xFU << FMC_PCR2_TAR_Pos) /*!< 0x0001E000 */
9091 #define FMC_PCR2_TAR FMC_PCR2_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
9092 #define FMC_PCR2_TAR_0 (0x1U << FMC_PCR2_TAR_Pos) /*!< 0x00002000 */
9093 #define FMC_PCR2_TAR_1 (0x2U << FMC_PCR2_TAR_Pos) /*!< 0x00004000 */
9094 #define FMC_PCR2_TAR_2 (0x4U << FMC_PCR2_TAR_Pos) /*!< 0x00008000 */
9095 #define FMC_PCR2_TAR_3 (0x8U << FMC_PCR2_TAR_Pos) /*!< 0x00010000 */
9096
9097 #define FMC_PCR2_ECCPS_Pos (17U)
9098 #define FMC_PCR2_ECCPS_Msk (0x7U << FMC_PCR2_ECCPS_Pos) /*!< 0x000E0000 */
9099 #define FMC_PCR2_ECCPS FMC_PCR2_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
9100 #define FMC_PCR2_ECCPS_0 (0x1U << FMC_PCR2_ECCPS_Pos) /*!< 0x00020000 */
9101 #define FMC_PCR2_ECCPS_1 (0x2U << FMC_PCR2_ECCPS_Pos) /*!< 0x00040000 */
9102 #define FMC_PCR2_ECCPS_2 (0x4U << FMC_PCR2_ECCPS_Pos) /*!< 0x00080000 */
9103
9104 /****************** Bit definition for FMC_PCR3 register *******************/
9105 #define FMC_PCR3_PWAITEN_Pos (1U)
9106 #define FMC_PCR3_PWAITEN_Msk (0x1U << FMC_PCR3_PWAITEN_Pos) /*!< 0x00000002 */
9107 #define FMC_PCR3_PWAITEN FMC_PCR3_PWAITEN_Msk /*!<Wait feature enable bit */
9108 #define FMC_PCR3_PBKEN_Pos (2U)
9109 #define FMC_PCR3_PBKEN_Msk (0x1U << FMC_PCR3_PBKEN_Pos) /*!< 0x00000004 */
9110 #define FMC_PCR3_PBKEN FMC_PCR3_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
9111 #define FMC_PCR3_PTYP_Pos (3U)
9112 #define FMC_PCR3_PTYP_Msk (0x1U << FMC_PCR3_PTYP_Pos) /*!< 0x00000008 */
9113 #define FMC_PCR3_PTYP FMC_PCR3_PTYP_Msk /*!<Memory type */
9114
9115 #define FMC_PCR3_PWID_Pos (4U)
9116 #define FMC_PCR3_PWID_Msk (0x3U << FMC_PCR3_PWID_Pos) /*!< 0x00000030 */
9117 #define FMC_PCR3_PWID FMC_PCR3_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
9118 #define FMC_PCR3_PWID_0 (0x1U << FMC_PCR3_PWID_Pos) /*!< 0x00000010 */
9119 #define FMC_PCR3_PWID_1 (0x2U << FMC_PCR3_PWID_Pos) /*!< 0x00000020 */
9120
9121 #define FMC_PCR3_ECCEN_Pos (6U)
9122 #define FMC_PCR3_ECCEN_Msk (0x1U << FMC_PCR3_ECCEN_Pos) /*!< 0x00000040 */
9123 #define FMC_PCR3_ECCEN FMC_PCR3_ECCEN_Msk /*!<ECC computation logic enable bit */
9124
9125 #define FMC_PCR3_TCLR_Pos (9U)
9126 #define FMC_PCR3_TCLR_Msk (0xFU << FMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
9127 #define FMC_PCR3_TCLR FMC_PCR3_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
9128 #define FMC_PCR3_TCLR_0 (0x1U << FMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
9129 #define FMC_PCR3_TCLR_1 (0x2U << FMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
9130 #define FMC_PCR3_TCLR_2 (0x4U << FMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
9131 #define FMC_PCR3_TCLR_3 (0x8U << FMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
9132
9133 #define FMC_PCR3_TAR_Pos (13U)
9134 #define FMC_PCR3_TAR_Msk (0xFU << FMC_PCR3_TAR_Pos) /*!< 0x0001E000 */
9135 #define FMC_PCR3_TAR FMC_PCR3_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
9136 #define FMC_PCR3_TAR_0 (0x1U << FMC_PCR3_TAR_Pos) /*!< 0x00002000 */
9137 #define FMC_PCR3_TAR_1 (0x2U << FMC_PCR3_TAR_Pos) /*!< 0x00004000 */
9138 #define FMC_PCR3_TAR_2 (0x4U << FMC_PCR3_TAR_Pos) /*!< 0x00008000 */
9139 #define FMC_PCR3_TAR_3 (0x8U << FMC_PCR3_TAR_Pos) /*!< 0x00010000 */
9140
9141 #define FMC_PCR3_ECCPS_Pos (17U)
9142 #define FMC_PCR3_ECCPS_Msk (0x7U << FMC_PCR3_ECCPS_Pos) /*!< 0x000E0000 */
9143 #define FMC_PCR3_ECCPS FMC_PCR3_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
9144 #define FMC_PCR3_ECCPS_0 (0x1U << FMC_PCR3_ECCPS_Pos) /*!< 0x00020000 */
9145 #define FMC_PCR3_ECCPS_1 (0x2U << FMC_PCR3_ECCPS_Pos) /*!< 0x00040000 */
9146 #define FMC_PCR3_ECCPS_2 (0x4U << FMC_PCR3_ECCPS_Pos) /*!< 0x00080000 */
9147
9148 /****************** Bit definition for FMC_PCR4 register *******************/
9149 #define FMC_PCR4_PWAITEN_Pos (1U)
9150 #define FMC_PCR4_PWAITEN_Msk (0x1U << FMC_PCR4_PWAITEN_Pos) /*!< 0x00000002 */
9151 #define FMC_PCR4_PWAITEN FMC_PCR4_PWAITEN_Msk /*!<Wait feature enable bit */
9152 #define FMC_PCR4_PBKEN_Pos (2U)
9153 #define FMC_PCR4_PBKEN_Msk (0x1U << FMC_PCR4_PBKEN_Pos) /*!< 0x00000004 */
9154 #define FMC_PCR4_PBKEN FMC_PCR4_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
9155 #define FMC_PCR4_PTYP_Pos (3U)
9156 #define FMC_PCR4_PTYP_Msk (0x1U << FMC_PCR4_PTYP_Pos) /*!< 0x00000008 */
9157 #define FMC_PCR4_PTYP FMC_PCR4_PTYP_Msk /*!<Memory type */
9158
9159 #define FMC_PCR4_PWID_Pos (4U)
9160 #define FMC_PCR4_PWID_Msk (0x3U << FMC_PCR4_PWID_Pos) /*!< 0x00000030 */
9161 #define FMC_PCR4_PWID FMC_PCR4_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
9162 #define FMC_PCR4_PWID_0 (0x1U << FMC_PCR4_PWID_Pos) /*!< 0x00000010 */
9163 #define FMC_PCR4_PWID_1 (0x2U << FMC_PCR4_PWID_Pos) /*!< 0x00000020 */
9164
9165 #define FMC_PCR4_ECCEN_Pos (6U)
9166 #define FMC_PCR4_ECCEN_Msk (0x1U << FMC_PCR4_ECCEN_Pos) /*!< 0x00000040 */
9167 #define FMC_PCR4_ECCEN FMC_PCR4_ECCEN_Msk /*!<ECC computation logic enable bit */
9168
9169 #define FMC_PCR4_TCLR_Pos (9U)
9170 #define FMC_PCR4_TCLR_Msk (0xFU << FMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */
9171 #define FMC_PCR4_TCLR FMC_PCR4_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
9172 #define FMC_PCR4_TCLR_0 (0x1U << FMC_PCR4_TCLR_Pos) /*!< 0x00000200 */
9173 #define FMC_PCR4_TCLR_1 (0x2U << FMC_PCR4_TCLR_Pos) /*!< 0x00000400 */
9174 #define FMC_PCR4_TCLR_2 (0x4U << FMC_PCR4_TCLR_Pos) /*!< 0x00000800 */
9175 #define FMC_PCR4_TCLR_3 (0x8U << FMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
9176
9177 #define FMC_PCR4_TAR_Pos (13U)
9178 #define FMC_PCR4_TAR_Msk (0xFU << FMC_PCR4_TAR_Pos) /*!< 0x0001E000 */
9179 #define FMC_PCR4_TAR FMC_PCR4_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
9180 #define FMC_PCR4_TAR_0 (0x1U << FMC_PCR4_TAR_Pos) /*!< 0x00002000 */
9181 #define FMC_PCR4_TAR_1 (0x2U << FMC_PCR4_TAR_Pos) /*!< 0x00004000 */
9182 #define FMC_PCR4_TAR_2 (0x4U << FMC_PCR4_TAR_Pos) /*!< 0x00008000 */
9183 #define FMC_PCR4_TAR_3 (0x8U << FMC_PCR4_TAR_Pos) /*!< 0x00010000 */
9184
9185 #define FMC_PCR4_ECCPS_Pos (17U)
9186 #define FMC_PCR4_ECCPS_Msk (0x7U << FMC_PCR4_ECCPS_Pos) /*!< 0x000E0000 */
9187 #define FMC_PCR4_ECCPS FMC_PCR4_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
9188 #define FMC_PCR4_ECCPS_0 (0x1U << FMC_PCR4_ECCPS_Pos) /*!< 0x00020000 */
9189 #define FMC_PCR4_ECCPS_1 (0x2U << FMC_PCR4_ECCPS_Pos) /*!< 0x00040000 */
9190 #define FMC_PCR4_ECCPS_2 (0x4U << FMC_PCR4_ECCPS_Pos) /*!< 0x00080000 */
9191
9192 /******************* Bit definition for FMC_SRx register *******************/
9193 #define FMC_SRx_IRS_Pos (0U)
9194 #define FMC_SRx_IRS_Msk (0x1U << FMC_SRx_IRS_Pos) /*!< 0x00000001 */
9195 #define FMC_SRx_IRS FMC_SRx_IRS_Msk /*!<Interrupt Rising Edge status */
9196 #define FMC_SRx_ILS_Pos (1U)
9197 #define FMC_SRx_ILS_Msk (0x1U << FMC_SRx_ILS_Pos) /*!< 0x00000002 */
9198 #define FMC_SRx_ILS FMC_SRx_ILS_Msk /*!<Interrupt Level status */
9199 #define FMC_SRx_IFS_Pos (2U)
9200 #define FMC_SRx_IFS_Msk (0x1U << FMC_SRx_IFS_Pos) /*!< 0x00000004 */
9201 #define FMC_SRx_IFS FMC_SRx_IFS_Msk /*!<Interrupt Falling Edge status */
9202 #define FMC_SRx_IREN_Pos (3U)
9203 #define FMC_SRx_IREN_Msk (0x1U << FMC_SRx_IREN_Pos) /*!< 0x00000008 */
9204 #define FMC_SRx_IREN FMC_SRx_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
9205 #define FMC_SRx_ILEN_Pos (4U)
9206 #define FMC_SRx_ILEN_Msk (0x1U << FMC_SRx_ILEN_Pos) /*!< 0x00000010 */
9207 #define FMC_SRx_ILEN FMC_SRx_ILEN_Msk /*!<Interrupt Level detection Enable bit */
9208 #define FMC_SRx_IFEN_Pos (5U)
9209 #define FMC_SRx_IFEN_Msk (0x1U << FMC_SRx_IFEN_Pos) /*!< 0x00000020 */
9210 #define FMC_SRx_IFEN FMC_SRx_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
9211 #define FMC_SRx_FEMPT_Pos (6U)
9212 #define FMC_SRx_FEMPT_Msk (0x1U << FMC_SRx_FEMPT_Pos) /*!< 0x00000040 */
9213 #define FMC_SRx_FEMPT FMC_SRx_FEMPT_Msk /*!<FIFO empty */
9214
9215 /******************* Bit definition for FMC_SR2 register *******************/
9216 #define FMC_SR2_IRS_Pos (0U)
9217 #define FMC_SR2_IRS_Msk (0x1U << FMC_SR2_IRS_Pos) /*!< 0x00000001 */
9218 #define FMC_SR2_IRS FMC_SR2_IRS_Msk /*!<Interrupt Rising Edge status */
9219 #define FMC_SR2_ILS_Pos (1U)
9220 #define FMC_SR2_ILS_Msk (0x1U << FMC_SR2_ILS_Pos) /*!< 0x00000002 */
9221 #define FMC_SR2_ILS FMC_SR2_ILS_Msk /*!<Interrupt Level status */
9222 #define FMC_SR2_IFS_Pos (2U)
9223 #define FMC_SR2_IFS_Msk (0x1U << FMC_SR2_IFS_Pos) /*!< 0x00000004 */
9224 #define FMC_SR2_IFS FMC_SR2_IFS_Msk /*!<Interrupt Falling Edge status */
9225 #define FMC_SR2_IREN_Pos (3U)
9226 #define FMC_SR2_IREN_Msk (0x1U << FMC_SR2_IREN_Pos) /*!< 0x00000008 */
9227 #define FMC_SR2_IREN FMC_SR2_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
9228 #define FMC_SR2_ILEN_Pos (4U)
9229 #define FMC_SR2_ILEN_Msk (0x1U << FMC_SR2_ILEN_Pos) /*!< 0x00000010 */
9230 #define FMC_SR2_ILEN FMC_SR2_ILEN_Msk /*!<Interrupt Level detection Enable bit */
9231 #define FMC_SR2_IFEN_Pos (5U)
9232 #define FMC_SR2_IFEN_Msk (0x1U << FMC_SR2_IFEN_Pos) /*!< 0x00000020 */
9233 #define FMC_SR2_IFEN FMC_SR2_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
9234 #define FMC_SR2_FEMPT_Pos (6U)
9235 #define FMC_SR2_FEMPT_Msk (0x1U << FMC_SR2_FEMPT_Pos) /*!< 0x00000040 */
9236 #define FMC_SR2_FEMPT FMC_SR2_FEMPT_Msk /*!<FIFO empty */
9237
9238 /******************* Bit definition for FMC_SR3 register *******************/
9239 #define FMC_SR3_IRS_Pos (0U)
9240 #define FMC_SR3_IRS_Msk (0x1U << FMC_SR3_IRS_Pos) /*!< 0x00000001 */
9241 #define FMC_SR3_IRS FMC_SR3_IRS_Msk /*!<Interrupt Rising Edge status */
9242 #define FMC_SR3_ILS_Pos (1U)
9243 #define FMC_SR3_ILS_Msk (0x1U << FMC_SR3_ILS_Pos) /*!< 0x00000002 */
9244 #define FMC_SR3_ILS FMC_SR3_ILS_Msk /*!<Interrupt Level status */
9245 #define FMC_SR3_IFS_Pos (2U)
9246 #define FMC_SR3_IFS_Msk (0x1U << FMC_SR3_IFS_Pos) /*!< 0x00000004 */
9247 #define FMC_SR3_IFS FMC_SR3_IFS_Msk /*!<Interrupt Falling Edge status */
9248 #define FMC_SR3_IREN_Pos (3U)
9249 #define FMC_SR3_IREN_Msk (0x1U << FMC_SR3_IREN_Pos) /*!< 0x00000008 */
9250 #define FMC_SR3_IREN FMC_SR3_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
9251 #define FMC_SR3_ILEN_Pos (4U)
9252 #define FMC_SR3_ILEN_Msk (0x1U << FMC_SR3_ILEN_Pos) /*!< 0x00000010 */
9253 #define FMC_SR3_ILEN FMC_SR3_ILEN_Msk /*!<Interrupt Level detection Enable bit */
9254 #define FMC_SR3_IFEN_Pos (5U)
9255 #define FMC_SR3_IFEN_Msk (0x1U << FMC_SR3_IFEN_Pos) /*!< 0x00000020 */
9256 #define FMC_SR3_IFEN FMC_SR3_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
9257 #define FMC_SR3_FEMPT_Pos (6U)
9258 #define FMC_SR3_FEMPT_Msk (0x1U << FMC_SR3_FEMPT_Pos) /*!< 0x00000040 */
9259 #define FMC_SR3_FEMPT FMC_SR3_FEMPT_Msk /*!<FIFO empty */
9260
9261 /******************* Bit definition for FMC_SR4 register *******************/
9262 #define FMC_SR4_IRS_Pos (0U)
9263 #define FMC_SR4_IRS_Msk (0x1U << FMC_SR4_IRS_Pos) /*!< 0x00000001 */
9264 #define FMC_SR4_IRS FMC_SR4_IRS_Msk /*!<Interrupt Rising Edge status */
9265 #define FMC_SR4_ILS_Pos (1U)
9266 #define FMC_SR4_ILS_Msk (0x1U << FMC_SR4_ILS_Pos) /*!< 0x00000002 */
9267 #define FMC_SR4_ILS FMC_SR4_ILS_Msk /*!<Interrupt Level status */
9268 #define FMC_SR4_IFS_Pos (2U)
9269 #define FMC_SR4_IFS_Msk (0x1U << FMC_SR4_IFS_Pos) /*!< 0x00000004 */
9270 #define FMC_SR4_IFS FMC_SR4_IFS_Msk /*!<Interrupt Falling Edge status */
9271 #define FMC_SR4_IREN_Pos (3U)
9272 #define FMC_SR4_IREN_Msk (0x1U << FMC_SR4_IREN_Pos) /*!< 0x00000008 */
9273 #define FMC_SR4_IREN FMC_SR4_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
9274 #define FMC_SR4_ILEN_Pos (4U)
9275 #define FMC_SR4_ILEN_Msk (0x1U << FMC_SR4_ILEN_Pos) /*!< 0x00000010 */
9276 #define FMC_SR4_ILEN FMC_SR4_ILEN_Msk /*!<Interrupt Level detection Enable bit */
9277 #define FMC_SR4_IFEN_Pos (5U)
9278 #define FMC_SR4_IFEN_Msk (0x1U << FMC_SR4_IFEN_Pos) /*!< 0x00000020 */
9279 #define FMC_SR4_IFEN FMC_SR4_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
9280 #define FMC_SR4_FEMPT_Pos (6U)
9281 #define FMC_SR4_FEMPT_Msk (0x1U << FMC_SR4_FEMPT_Pos) /*!< 0x00000040 */
9282 #define FMC_SR4_FEMPT FMC_SR4_FEMPT_Msk /*!<FIFO empty */
9283
9284 /****************** Bit definition for FMC_PMEMx register ******************/
9285 #define FMC_PMEMx_MEMSETx_Pos (0U)
9286 #define FMC_PMEMx_MEMSETx_Msk (0xFFU << FMC_PMEMx_MEMSETx_Pos) /*!< 0x000000FF */
9287 #define FMC_PMEMx_MEMSETx FMC_PMEMx_MEMSETx_Msk /*!<MEMSETx[7:0] bits (Common memory x setup time) */
9288 #define FMC_PMEMx_MEMSETx_0 (0x01U << FMC_PMEMx_MEMSETx_Pos) /*!< 0x00000001 */
9289 #define FMC_PMEMx_MEMSETx_1 (0x02U << FMC_PMEMx_MEMSETx_Pos) /*!< 0x00000002 */
9290 #define FMC_PMEMx_MEMSETx_2 (0x04U << FMC_PMEMx_MEMSETx_Pos) /*!< 0x00000004 */
9291 #define FMC_PMEMx_MEMSETx_3 (0x08U << FMC_PMEMx_MEMSETx_Pos) /*!< 0x00000008 */
9292 #define FMC_PMEMx_MEMSETx_4 (0x10U << FMC_PMEMx_MEMSETx_Pos) /*!< 0x00000010 */
9293 #define FMC_PMEMx_MEMSETx_5 (0x20U << FMC_PMEMx_MEMSETx_Pos) /*!< 0x00000020 */
9294 #define FMC_PMEMx_MEMSETx_6 (0x40U << FMC_PMEMx_MEMSETx_Pos) /*!< 0x00000040 */
9295 #define FMC_PMEMx_MEMSETx_7 (0x80U << FMC_PMEMx_MEMSETx_Pos) /*!< 0x00000080 */
9296
9297 #define FMC_PMEMx_MEMWAITx_Pos (8U)
9298 #define FMC_PMEMx_MEMWAITx_Msk (0xFFU << FMC_PMEMx_MEMWAITx_Pos) /*!< 0x0000FF00 */
9299 #define FMC_PMEMx_MEMWAITx FMC_PMEMx_MEMWAITx_Msk /*!<MEMWAITx[7:0] bits (Common memory x wait time) */
9300 #define FMC_PMEMx_MEMWAITx_0 (0x01U << FMC_PMEMx_MEMWAITx_Pos) /*!< 0x00000100 */
9301 #define FMC_PMEMx_MEMWAITx_1 (0x02U << FMC_PMEMx_MEMWAITx_Pos) /*!< 0x00000200 */
9302 #define FMC_PMEMx_MEMWAITx_2 (0x04U << FMC_PMEMx_MEMWAITx_Pos) /*!< 0x00000400 */
9303 #define FMC_PMEMx_MEMWAITx_3 (0x08U << FMC_PMEMx_MEMWAITx_Pos) /*!< 0x00000800 */
9304 #define FMC_PMEMx_MEMWAITx_4 (0x10U << FMC_PMEMx_MEMWAITx_Pos) /*!< 0x00001000 */
9305 #define FMC_PMEMx_MEMWAITx_5 (0x20U << FMC_PMEMx_MEMWAITx_Pos) /*!< 0x00002000 */
9306 #define FMC_PMEMx_MEMWAITx_6 (0x40U << FMC_PMEMx_MEMWAITx_Pos) /*!< 0x00004000 */
9307 #define FMC_PMEMx_MEMWAITx_7 (0x80U << FMC_PMEMx_MEMWAITx_Pos) /*!< 0x00008000 */
9308
9309 #define FMC_PMEMx_MEMHOLDx_Pos (16U)
9310 #define FMC_PMEMx_MEMHOLDx_Msk (0xFFU << FMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00FF0000 */
9311 #define FMC_PMEMx_MEMHOLDx FMC_PMEMx_MEMHOLDx_Msk /*!<MEMHOLDx[7:0] bits (Common memory x hold time) */
9312 #define FMC_PMEMx_MEMHOLDx_0 (0x01U << FMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00010000 */
9313 #define FMC_PMEMx_MEMHOLDx_1 (0x02U << FMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00020000 */
9314 #define FMC_PMEMx_MEMHOLDx_2 (0x04U << FMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00040000 */
9315 #define FMC_PMEMx_MEMHOLDx_3 (0x08U << FMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00080000 */
9316 #define FMC_PMEMx_MEMHOLDx_4 (0x10U << FMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00100000 */
9317 #define FMC_PMEMx_MEMHOLDx_5 (0x20U << FMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00200000 */
9318 #define FMC_PMEMx_MEMHOLDx_6 (0x40U << FMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00400000 */
9319 #define FMC_PMEMx_MEMHOLDx_7 (0x80U << FMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00800000 */
9320
9321 #define FMC_PMEMx_MEMHIZx_Pos (24U)
9322 #define FMC_PMEMx_MEMHIZx_Msk (0xFFU << FMC_PMEMx_MEMHIZx_Pos) /*!< 0xFF000000 */
9323 #define FMC_PMEMx_MEMHIZx FMC_PMEMx_MEMHIZx_Msk /*!<MEMHIZx[7:0] bits (Common memory x databus HiZ time) */
9324 #define FMC_PMEMx_MEMHIZx_0 (0x01U << FMC_PMEMx_MEMHIZx_Pos) /*!< 0x01000000 */
9325 #define FMC_PMEMx_MEMHIZx_1 (0x02U << FMC_PMEMx_MEMHIZx_Pos) /*!< 0x02000000 */
9326 #define FMC_PMEMx_MEMHIZx_2 (0x04U << FMC_PMEMx_MEMHIZx_Pos) /*!< 0x04000000 */
9327 #define FMC_PMEMx_MEMHIZx_3 (0x08U << FMC_PMEMx_MEMHIZx_Pos) /*!< 0x08000000 */
9328 #define FMC_PMEMx_MEMHIZx_4 (0x10U << FMC_PMEMx_MEMHIZx_Pos) /*!< 0x10000000 */
9329 #define FMC_PMEMx_MEMHIZx_5 (0x20U << FMC_PMEMx_MEMHIZx_Pos) /*!< 0x20000000 */
9330 #define FMC_PMEMx_MEMHIZx_6 (0x40U << FMC_PMEMx_MEMHIZx_Pos) /*!< 0x40000000 */
9331 #define FMC_PMEMx_MEMHIZx_7 (0x80U << FMC_PMEMx_MEMHIZx_Pos) /*!< 0x80000000 */
9332
9333 /****************** Bit definition for FMC_PMEM2 register ******************/
9334 #define FMC_PMEM2_MEMSET2_Pos (0U)
9335 #define FMC_PMEM2_MEMSET2_Msk (0xFFU << FMC_PMEM2_MEMSET2_Pos) /*!< 0x000000FF */
9336 #define FMC_PMEM2_MEMSET2 FMC_PMEM2_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
9337 #define FMC_PMEM2_MEMSET2_0 (0x01U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000001 */
9338 #define FMC_PMEM2_MEMSET2_1 (0x02U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000002 */
9339 #define FMC_PMEM2_MEMSET2_2 (0x04U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000004 */
9340 #define FMC_PMEM2_MEMSET2_3 (0x08U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000008 */
9341 #define FMC_PMEM2_MEMSET2_4 (0x10U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000010 */
9342 #define FMC_PMEM2_MEMSET2_5 (0x20U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000020 */
9343 #define FMC_PMEM2_MEMSET2_6 (0x40U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000040 */
9344 #define FMC_PMEM2_MEMSET2_7 (0x80U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000080 */
9345
9346 #define FMC_PMEM2_MEMWAIT2_Pos (8U)
9347 #define FMC_PMEM2_MEMWAIT2_Msk (0xFFU << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x0000FF00 */
9348 #define FMC_PMEM2_MEMWAIT2 FMC_PMEM2_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
9349 #define FMC_PMEM2_MEMWAIT2_0 (0x01U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000100 */
9350 #define FMC_PMEM2_MEMWAIT2_1 (0x02U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000200 */
9351 #define FMC_PMEM2_MEMWAIT2_2 (0x04U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000400 */
9352 #define FMC_PMEM2_MEMWAIT2_3 (0x08U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000800 */
9353 #define FMC_PMEM2_MEMWAIT2_4 (0x10U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00001000 */
9354 #define FMC_PMEM2_MEMWAIT2_5 (0x20U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00002000 */
9355 #define FMC_PMEM2_MEMWAIT2_6 (0x40U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00004000 */
9356 #define FMC_PMEM2_MEMWAIT2_7 (0x80U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00008000 */
9357
9358 #define FMC_PMEM2_MEMHOLD2_Pos (16U)
9359 #define FMC_PMEM2_MEMHOLD2_Msk (0xFFU << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00FF0000 */
9360 #define FMC_PMEM2_MEMHOLD2 FMC_PMEM2_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
9361 #define FMC_PMEM2_MEMHOLD2_0 (0x01U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00010000 */
9362 #define FMC_PMEM2_MEMHOLD2_1 (0x02U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00020000 */
9363 #define FMC_PMEM2_MEMHOLD2_2 (0x04U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00040000 */
9364 #define FMC_PMEM2_MEMHOLD2_3 (0x08U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00080000 */
9365 #define FMC_PMEM2_MEMHOLD2_4 (0x10U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00100000 */
9366 #define FMC_PMEM2_MEMHOLD2_5 (0x20U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00200000 */
9367 #define FMC_PMEM2_MEMHOLD2_6 (0x40U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00400000 */
9368 #define FMC_PMEM2_MEMHOLD2_7 (0x80U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00800000 */
9369
9370 #define FMC_PMEM2_MEMHIZ2_Pos (24U)
9371 #define FMC_PMEM2_MEMHIZ2_Msk (0xFFU << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0xFF000000 */
9372 #define FMC_PMEM2_MEMHIZ2 FMC_PMEM2_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
9373 #define FMC_PMEM2_MEMHIZ2_0 (0x01U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x01000000 */
9374 #define FMC_PMEM2_MEMHIZ2_1 (0x02U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x02000000 */
9375 #define FMC_PMEM2_MEMHIZ2_2 (0x04U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x04000000 */
9376 #define FMC_PMEM2_MEMHIZ2_3 (0x08U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x08000000 */
9377 #define FMC_PMEM2_MEMHIZ2_4 (0x10U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x10000000 */
9378 #define FMC_PMEM2_MEMHIZ2_5 (0x20U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x20000000 */
9379 #define FMC_PMEM2_MEMHIZ2_6 (0x40U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x40000000 */
9380 #define FMC_PMEM2_MEMHIZ2_7 (0x80U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x80000000 */
9381
9382 /****************** Bit definition for FMC_PMEM3 register ******************/
9383 #define FMC_PMEM3_MEMSET3_Pos (0U)
9384 #define FMC_PMEM3_MEMSET3_Msk (0xFFU << FMC_PMEM3_MEMSET3_Pos) /*!< 0x000000FF */
9385 #define FMC_PMEM3_MEMSET3 FMC_PMEM3_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
9386 #define FMC_PMEM3_MEMSET3_0 (0x01U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000001 */
9387 #define FMC_PMEM3_MEMSET3_1 (0x02U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000002 */
9388 #define FMC_PMEM3_MEMSET3_2 (0x04U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000004 */
9389 #define FMC_PMEM3_MEMSET3_3 (0x08U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000008 */
9390 #define FMC_PMEM3_MEMSET3_4 (0x10U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000010 */
9391 #define FMC_PMEM3_MEMSET3_5 (0x20U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000020 */
9392 #define FMC_PMEM3_MEMSET3_6 (0x40U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000040 */
9393 #define FMC_PMEM3_MEMSET3_7 (0x80U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000080 */
9394
9395 #define FMC_PMEM3_MEMWAIT3_Pos (8U)
9396 #define FMC_PMEM3_MEMWAIT3_Msk (0xFFU << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x0000FF00 */
9397 #define FMC_PMEM3_MEMWAIT3 FMC_PMEM3_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
9398 #define FMC_PMEM3_MEMWAIT3_0 (0x01U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000100 */
9399 #define FMC_PMEM3_MEMWAIT3_1 (0x02U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000200 */
9400 #define FMC_PMEM3_MEMWAIT3_2 (0x04U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000400 */
9401 #define FMC_PMEM3_MEMWAIT3_3 (0x08U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000800 */
9402 #define FMC_PMEM3_MEMWAIT3_4 (0x10U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00001000 */
9403 #define FMC_PMEM3_MEMWAIT3_5 (0x20U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00002000 */
9404 #define FMC_PMEM3_MEMWAIT3_6 (0x40U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00004000 */
9405 #define FMC_PMEM3_MEMWAIT3_7 (0x80U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00008000 */
9406
9407 #define FMC_PMEM3_MEMHOLD3_Pos (16U)
9408 #define FMC_PMEM3_MEMHOLD3_Msk (0xFFU << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00FF0000 */
9409 #define FMC_PMEM3_MEMHOLD3 FMC_PMEM3_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
9410 #define FMC_PMEM3_MEMHOLD3_0 (0x01U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00010000 */
9411 #define FMC_PMEM3_MEMHOLD3_1 (0x02U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00020000 */
9412 #define FMC_PMEM3_MEMHOLD3_2 (0x04U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00040000 */
9413 #define FMC_PMEM3_MEMHOLD3_3 (0x08U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00080000 */
9414 #define FMC_PMEM3_MEMHOLD3_4 (0x10U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00100000 */
9415 #define FMC_PMEM3_MEMHOLD3_5 (0x20U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00200000 */
9416 #define FMC_PMEM3_MEMHOLD3_6 (0x40U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00400000 */
9417 #define FMC_PMEM3_MEMHOLD3_7 (0x80U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00800000 */
9418
9419 #define FMC_PMEM3_MEMHIZ3_Pos (24U)
9420 #define FMC_PMEM3_MEMHIZ3_Msk (0xFFU << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0xFF000000 */
9421 #define FMC_PMEM3_MEMHIZ3 FMC_PMEM3_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
9422 #define FMC_PMEM3_MEMHIZ3_0 (0x01U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x01000000 */
9423 #define FMC_PMEM3_MEMHIZ3_1 (0x02U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x02000000 */
9424 #define FMC_PMEM3_MEMHIZ3_2 (0x04U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x04000000 */
9425 #define FMC_PMEM3_MEMHIZ3_3 (0x08U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x08000000 */
9426 #define FMC_PMEM3_MEMHIZ3_4 (0x10U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x10000000 */
9427 #define FMC_PMEM3_MEMHIZ3_5 (0x20U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x20000000 */
9428 #define FMC_PMEM3_MEMHIZ3_6 (0x40U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x40000000 */
9429 #define FMC_PMEM3_MEMHIZ3_7 (0x80U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x80000000 */
9430
9431 /****************** Bit definition for FMC_PMEM4 register ******************/
9432 #define FMC_PMEM4_MEMSET4_Pos (0U)
9433 #define FMC_PMEM4_MEMSET4_Msk (0xFFU << FMC_PMEM4_MEMSET4_Pos) /*!< 0x000000FF */
9434 #define FMC_PMEM4_MEMSET4 FMC_PMEM4_MEMSET4_Msk /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
9435 #define FMC_PMEM4_MEMSET4_0 (0x01U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000001 */
9436 #define FMC_PMEM4_MEMSET4_1 (0x02U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000002 */
9437 #define FMC_PMEM4_MEMSET4_2 (0x04U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000004 */
9438 #define FMC_PMEM4_MEMSET4_3 (0x08U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000008 */
9439 #define FMC_PMEM4_MEMSET4_4 (0x10U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000010 */
9440 #define FMC_PMEM4_MEMSET4_5 (0x20U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000020 */
9441 #define FMC_PMEM4_MEMSET4_6 (0x40U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000040 */
9442 #define FMC_PMEM4_MEMSET4_7 (0x80U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000080 */
9443
9444 #define FMC_PMEM4_MEMWAIT4_Pos (8U)
9445 #define FMC_PMEM4_MEMWAIT4_Msk (0xFFU << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x0000FF00 */
9446 #define FMC_PMEM4_MEMWAIT4 FMC_PMEM4_MEMWAIT4_Msk /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
9447 #define FMC_PMEM4_MEMWAIT4_0 (0x01U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000100 */
9448 #define FMC_PMEM4_MEMWAIT4_1 (0x02U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000200 */
9449 #define FMC_PMEM4_MEMWAIT4_2 (0x04U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000400 */
9450 #define FMC_PMEM4_MEMWAIT4_3 (0x08U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000800 */
9451 #define FMC_PMEM4_MEMWAIT4_4 (0x10U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00001000 */
9452 #define FMC_PMEM4_MEMWAIT4_5 (0x20U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00002000 */
9453 #define FMC_PMEM4_MEMWAIT4_6 (0x40U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00004000 */
9454 #define FMC_PMEM4_MEMWAIT4_7 (0x80U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00008000 */
9455
9456 #define FMC_PMEM4_MEMHOLD4_Pos (16U)
9457 #define FMC_PMEM4_MEMHOLD4_Msk (0xFFU << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00FF0000 */
9458 #define FMC_PMEM4_MEMHOLD4 FMC_PMEM4_MEMHOLD4_Msk /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
9459 #define FMC_PMEM4_MEMHOLD4_0 (0x01U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00010000 */
9460 #define FMC_PMEM4_MEMHOLD4_1 (0x02U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00020000 */
9461 #define FMC_PMEM4_MEMHOLD4_2 (0x04U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00040000 */
9462 #define FMC_PMEM4_MEMHOLD4_3 (0x08U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00080000 */
9463 #define FMC_PMEM4_MEMHOLD4_4 (0x10U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00100000 */
9464 #define FMC_PMEM4_MEMHOLD4_5 (0x20U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00200000 */
9465 #define FMC_PMEM4_MEMHOLD4_6 (0x40U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00400000 */
9466 #define FMC_PMEM4_MEMHOLD4_7 (0x80U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00800000 */
9467
9468 #define FMC_PMEM4_MEMHIZ4_Pos (24U)
9469 #define FMC_PMEM4_MEMHIZ4_Msk (0xFFU << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0xFF000000 */
9470 #define FMC_PMEM4_MEMHIZ4 FMC_PMEM4_MEMHIZ4_Msk /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
9471 #define FMC_PMEM4_MEMHIZ4_0 (0x01U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x01000000 */
9472 #define FMC_PMEM4_MEMHIZ4_1 (0x02U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x02000000 */
9473 #define FMC_PMEM4_MEMHIZ4_2 (0x04U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x04000000 */
9474 #define FMC_PMEM4_MEMHIZ4_3 (0x08U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x08000000 */
9475 #define FMC_PMEM4_MEMHIZ4_4 (0x10U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x10000000 */
9476 #define FMC_PMEM4_MEMHIZ4_5 (0x20U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x20000000 */
9477 #define FMC_PMEM4_MEMHIZ4_6 (0x40U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x40000000 */
9478 #define FMC_PMEM4_MEMHIZ4_7 (0x80U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x80000000 */
9479
9480 /****************** Bit definition for FMC_PATTx register ******************/
9481 #define FMC_PATTx_ATTSETx_Pos (0U)
9482 #define FMC_PATTx_ATTSETx_Msk (0xFFU << FMC_PATTx_ATTSETx_Pos) /*!< 0x000000FF */
9483 #define FMC_PATTx_ATTSETx FMC_PATTx_ATTSETx_Msk /*!<ATTSETx[7:0] bits (Attribute memory x setup time) */
9484 #define FMC_PATTx_ATTSETx_0 (0x01U << FMC_PATTx_ATTSETx_Pos) /*!< 0x00000001 */
9485 #define FMC_PATTx_ATTSETx_1 (0x02U << FMC_PATTx_ATTSETx_Pos) /*!< 0x00000002 */
9486 #define FMC_PATTx_ATTSETx_2 (0x04U << FMC_PATTx_ATTSETx_Pos) /*!< 0x00000004 */
9487 #define FMC_PATTx_ATTSETx_3 (0x08U << FMC_PATTx_ATTSETx_Pos) /*!< 0x00000008 */
9488 #define FMC_PATTx_ATTSETx_4 (0x10U << FMC_PATTx_ATTSETx_Pos) /*!< 0x00000010 */
9489 #define FMC_PATTx_ATTSETx_5 (0x20U << FMC_PATTx_ATTSETx_Pos) /*!< 0x00000020 */
9490 #define FMC_PATTx_ATTSETx_6 (0x40U << FMC_PATTx_ATTSETx_Pos) /*!< 0x00000040 */
9491 #define FMC_PATTx_ATTSETx_7 (0x80U << FMC_PATTx_ATTSETx_Pos) /*!< 0x00000080 */
9492
9493 #define FMC_PATTx_ATTWAITx_Pos (8U)
9494 #define FMC_PATTx_ATTWAITx_Msk (0xFFU << FMC_PATTx_ATTWAITx_Pos) /*!< 0x0000FF00 */
9495 #define FMC_PATTx_ATTWAITx FMC_PATTx_ATTWAITx_Msk /*!<ATTWAITx[7:0] bits (Attribute memory x wait time) */
9496 #define FMC_PATTx_ATTWAITx_0 (0x01U << FMC_PATTx_ATTWAITx_Pos) /*!< 0x00000100 */
9497 #define FMC_PATTx_ATTWAITx_1 (0x02U << FMC_PATTx_ATTWAITx_Pos) /*!< 0x00000200 */
9498 #define FMC_PATTx_ATTWAITx_2 (0x04U << FMC_PATTx_ATTWAITx_Pos) /*!< 0x00000400 */
9499 #define FMC_PATTx_ATTWAITx_3 (0x08U << FMC_PATTx_ATTWAITx_Pos) /*!< 0x00000800 */
9500 #define FMC_PATTx_ATTWAITx_4 (0x10U << FMC_PATTx_ATTWAITx_Pos) /*!< 0x00001000 */
9501 #define FMC_PATTx_ATTWAITx_5 (0x20U << FMC_PATTx_ATTWAITx_Pos) /*!< 0x00002000 */
9502 #define FMC_PATTx_ATTWAITx_6 (0x40U << FMC_PATTx_ATTWAITx_Pos) /*!< 0x00004000 */
9503 #define FMC_PATTx_ATTWAITx_7 (0x80U << FMC_PATTx_ATTWAITx_Pos) /*!< 0x00008000 */
9504
9505 #define FMC_PATTx_ATTHOLDx_Pos (16U)
9506 #define FMC_PATTx_ATTHOLDx_Msk (0xFFU << FMC_PATTx_ATTHOLDx_Pos) /*!< 0x00FF0000 */
9507 #define FMC_PATTx_ATTHOLDx FMC_PATTx_ATTHOLDx_Msk /*!<ATTHOLDx[7:0] bits (Attribute memory x hold time) */
9508 #define FMC_PATTx_ATTHOLDx_0 (0x01U << FMC_PATTx_ATTHOLDx_Pos) /*!< 0x00010000 */
9509 #define FMC_PATTx_ATTHOLDx_1 (0x02U << FMC_PATTx_ATTHOLDx_Pos) /*!< 0x00020000 */
9510 #define FMC_PATTx_ATTHOLDx_2 (0x04U << FMC_PATTx_ATTHOLDx_Pos) /*!< 0x00040000 */
9511 #define FMC_PATTx_ATTHOLDx_3 (0x08U << FMC_PATTx_ATTHOLDx_Pos) /*!< 0x00080000 */
9512 #define FMC_PATTx_ATTHOLDx_4 (0x10U << FMC_PATTx_ATTHOLDx_Pos) /*!< 0x00100000 */
9513 #define FMC_PATTx_ATTHOLDx_5 (0x20U << FMC_PATTx_ATTHOLDx_Pos) /*!< 0x00200000 */
9514 #define FMC_PATTx_ATTHOLDx_6 (0x40U << FMC_PATTx_ATTHOLDx_Pos) /*!< 0x00400000 */
9515 #define FMC_PATTx_ATTHOLDx_7 (0x80U << FMC_PATTx_ATTHOLDx_Pos) /*!< 0x00800000 */
9516
9517 #define FMC_PATTx_ATTHIZx_Pos (24U)
9518 #define FMC_PATTx_ATTHIZx_Msk (0xFFU << FMC_PATTx_ATTHIZx_Pos) /*!< 0xFF000000 */
9519 #define FMC_PATTx_ATTHIZx FMC_PATTx_ATTHIZx_Msk /*!<ATTHIZx[7:0] bits (Attribute memory x databus HiZ time) */
9520 #define FMC_PATTx_ATTHIZx_0 (0x01U << FMC_PATTx_ATTHIZx_Pos) /*!< 0x01000000 */
9521 #define FMC_PATTx_ATTHIZx_1 (0x02U << FMC_PATTx_ATTHIZx_Pos) /*!< 0x02000000 */
9522 #define FMC_PATTx_ATTHIZx_2 (0x04U << FMC_PATTx_ATTHIZx_Pos) /*!< 0x04000000 */
9523 #define FMC_PATTx_ATTHIZx_3 (0x08U << FMC_PATTx_ATTHIZx_Pos) /*!< 0x08000000 */
9524 #define FMC_PATTx_ATTHIZx_4 (0x10U << FMC_PATTx_ATTHIZx_Pos) /*!< 0x10000000 */
9525 #define FMC_PATTx_ATTHIZx_5 (0x20U << FMC_PATTx_ATTHIZx_Pos) /*!< 0x20000000 */
9526 #define FMC_PATTx_ATTHIZx_6 (0x40U << FMC_PATTx_ATTHIZx_Pos) /*!< 0x40000000 */
9527 #define FMC_PATTx_ATTHIZx_7 (0x80U << FMC_PATTx_ATTHIZx_Pos) /*!< 0x80000000 */
9528
9529 /****************** Bit definition for FMC_PATT2 register ******************/
9530 #define FMC_PATT2_ATTSET2_Pos (0U)
9531 #define FMC_PATT2_ATTSET2_Msk (0xFFU << FMC_PATT2_ATTSET2_Pos) /*!< 0x000000FF */
9532 #define FMC_PATT2_ATTSET2 FMC_PATT2_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
9533 #define FMC_PATT2_ATTSET2_0 (0x01U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000001 */
9534 #define FMC_PATT2_ATTSET2_1 (0x02U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000002 */
9535 #define FMC_PATT2_ATTSET2_2 (0x04U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000004 */
9536 #define FMC_PATT2_ATTSET2_3 (0x08U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000008 */
9537 #define FMC_PATT2_ATTSET2_4 (0x10U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000010 */
9538 #define FMC_PATT2_ATTSET2_5 (0x20U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000020 */
9539 #define FMC_PATT2_ATTSET2_6 (0x40U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000040 */
9540 #define FMC_PATT2_ATTSET2_7 (0x80U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000080 */
9541
9542 #define FMC_PATT2_ATTWAIT2_Pos (8U)
9543 #define FMC_PATT2_ATTWAIT2_Msk (0xFFU << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x0000FF00 */
9544 #define FMC_PATT2_ATTWAIT2 FMC_PATT2_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
9545 #define FMC_PATT2_ATTWAIT2_0 (0x01U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000100 */
9546 #define FMC_PATT2_ATTWAIT2_1 (0x02U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000200 */
9547 #define FMC_PATT2_ATTWAIT2_2 (0x04U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000400 */
9548 #define FMC_PATT2_ATTWAIT2_3 (0x08U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000800 */
9549 #define FMC_PATT2_ATTWAIT2_4 (0x10U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00001000 */
9550 #define FMC_PATT2_ATTWAIT2_5 (0x20U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00002000 */
9551 #define FMC_PATT2_ATTWAIT2_6 (0x40U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00004000 */
9552 #define FMC_PATT2_ATTWAIT2_7 (0x80U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00008000 */
9553
9554 #define FMC_PATT2_ATTHOLD2_Pos (16U)
9555 #define FMC_PATT2_ATTHOLD2_Msk (0xFFU << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00FF0000 */
9556 #define FMC_PATT2_ATTHOLD2 FMC_PATT2_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
9557 #define FMC_PATT2_ATTHOLD2_0 (0x01U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00010000 */
9558 #define FMC_PATT2_ATTHOLD2_1 (0x02U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00020000 */
9559 #define FMC_PATT2_ATTHOLD2_2 (0x04U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00040000 */
9560 #define FMC_PATT2_ATTHOLD2_3 (0x08U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00080000 */
9561 #define FMC_PATT2_ATTHOLD2_4 (0x10U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00100000 */
9562 #define FMC_PATT2_ATTHOLD2_5 (0x20U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00200000 */
9563 #define FMC_PATT2_ATTHOLD2_6 (0x40U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00400000 */
9564 #define FMC_PATT2_ATTHOLD2_7 (0x80U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00800000 */
9565
9566 #define FMC_PATT2_ATTHIZ2_Pos (24U)
9567 #define FMC_PATT2_ATTHIZ2_Msk (0xFFU << FMC_PATT2_ATTHIZ2_Pos) /*!< 0xFF000000 */
9568 #define FMC_PATT2_ATTHIZ2 FMC_PATT2_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
9569 #define FMC_PATT2_ATTHIZ2_0 (0x01U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x01000000 */
9570 #define FMC_PATT2_ATTHIZ2_1 (0x02U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x02000000 */
9571 #define FMC_PATT2_ATTHIZ2_2 (0x04U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x04000000 */
9572 #define FMC_PATT2_ATTHIZ2_3 (0x08U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x08000000 */
9573 #define FMC_PATT2_ATTHIZ2_4 (0x10U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x10000000 */
9574 #define FMC_PATT2_ATTHIZ2_5 (0x20U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x20000000 */
9575 #define FMC_PATT2_ATTHIZ2_6 (0x40U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x40000000 */
9576 #define FMC_PATT2_ATTHIZ2_7 (0x80U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x80000000 */
9577
9578 /****************** Bit definition for FMC_PATT3 register ******************/
9579 #define FMC_PATT3_ATTSET3_Pos (0U)
9580 #define FMC_PATT3_ATTSET3_Msk (0xFFU << FMC_PATT3_ATTSET3_Pos) /*!< 0x000000FF */
9581 #define FMC_PATT3_ATTSET3 FMC_PATT3_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
9582 #define FMC_PATT3_ATTSET3_0 (0x01U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000001 */
9583 #define FMC_PATT3_ATTSET3_1 (0x02U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000002 */
9584 #define FMC_PATT3_ATTSET3_2 (0x04U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000004 */
9585 #define FMC_PATT3_ATTSET3_3 (0x08U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000008 */
9586 #define FMC_PATT3_ATTSET3_4 (0x10U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000010 */
9587 #define FMC_PATT3_ATTSET3_5 (0x20U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000020 */
9588 #define FMC_PATT3_ATTSET3_6 (0x40U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000040 */
9589 #define FMC_PATT3_ATTSET3_7 (0x80U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000080 */
9590
9591 #define FMC_PATT3_ATTWAIT3_Pos (8U)
9592 #define FMC_PATT3_ATTWAIT3_Msk (0xFFU << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x0000FF00 */
9593 #define FMC_PATT3_ATTWAIT3 FMC_PATT3_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
9594 #define FMC_PATT3_ATTWAIT3_0 (0x01U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000100 */
9595 #define FMC_PATT3_ATTWAIT3_1 (0x02U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000200 */
9596 #define FMC_PATT3_ATTWAIT3_2 (0x04U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000400 */
9597 #define FMC_PATT3_ATTWAIT3_3 (0x08U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000800 */
9598 #define FMC_PATT3_ATTWAIT3_4 (0x10U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00001000 */
9599 #define FMC_PATT3_ATTWAIT3_5 (0x20U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00002000 */
9600 #define FMC_PATT3_ATTWAIT3_6 (0x40U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00004000 */
9601 #define FMC_PATT3_ATTWAIT3_7 (0x80U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00008000 */
9602
9603 #define FMC_PATT3_ATTHOLD3_Pos (16U)
9604 #define FMC_PATT3_ATTHOLD3_Msk (0xFFU << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00FF0000 */
9605 #define FMC_PATT3_ATTHOLD3 FMC_PATT3_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
9606 #define FMC_PATT3_ATTHOLD3_0 (0x01U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00010000 */
9607 #define FMC_PATT3_ATTHOLD3_1 (0x02U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00020000 */
9608 #define FMC_PATT3_ATTHOLD3_2 (0x04U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00040000 */
9609 #define FMC_PATT3_ATTHOLD3_3 (0x08U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00080000 */
9610 #define FMC_PATT3_ATTHOLD3_4 (0x10U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00100000 */
9611 #define FMC_PATT3_ATTHOLD3_5 (0x20U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00200000 */
9612 #define FMC_PATT3_ATTHOLD3_6 (0x40U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00400000 */
9613 #define FMC_PATT3_ATTHOLD3_7 (0x80U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00800000 */
9614
9615 #define FMC_PATT3_ATTHIZ3_Pos (24U)
9616 #define FMC_PATT3_ATTHIZ3_Msk (0xFFU << FMC_PATT3_ATTHIZ3_Pos) /*!< 0xFF000000 */
9617 #define FMC_PATT3_ATTHIZ3 FMC_PATT3_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
9618 #define FMC_PATT3_ATTHIZ3_0 (0x01U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x01000000 */
9619 #define FMC_PATT3_ATTHIZ3_1 (0x02U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x02000000 */
9620 #define FMC_PATT3_ATTHIZ3_2 (0x04U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x04000000 */
9621 #define FMC_PATT3_ATTHIZ3_3 (0x08U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x08000000 */
9622 #define FMC_PATT3_ATTHIZ3_4 (0x10U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x10000000 */
9623 #define FMC_PATT3_ATTHIZ3_5 (0x20U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x20000000 */
9624 #define FMC_PATT3_ATTHIZ3_6 (0x40U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x40000000 */
9625 #define FMC_PATT3_ATTHIZ3_7 (0x80U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x80000000 */
9626
9627 /****************** Bit definition for FMC_PATT4 register ******************/
9628 #define FMC_PATT4_ATTSET4_Pos (0U)
9629 #define FMC_PATT4_ATTSET4_Msk (0xFFU << FMC_PATT4_ATTSET4_Pos) /*!< 0x000000FF */
9630 #define FMC_PATT4_ATTSET4 FMC_PATT4_ATTSET4_Msk /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
9631 #define FMC_PATT4_ATTSET4_0 (0x01U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000001 */
9632 #define FMC_PATT4_ATTSET4_1 (0x02U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000002 */
9633 #define FMC_PATT4_ATTSET4_2 (0x04U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000004 */
9634 #define FMC_PATT4_ATTSET4_3 (0x08U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000008 */
9635 #define FMC_PATT4_ATTSET4_4 (0x10U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000010 */
9636 #define FMC_PATT4_ATTSET4_5 (0x20U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000020 */
9637 #define FMC_PATT4_ATTSET4_6 (0x40U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000040 */
9638 #define FMC_PATT4_ATTSET4_7 (0x80U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000080 */
9639
9640 #define FMC_PATT4_ATTWAIT4_Pos (8U)
9641 #define FMC_PATT4_ATTWAIT4_Msk (0xFFU << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x0000FF00 */
9642 #define FMC_PATT4_ATTWAIT4 FMC_PATT4_ATTWAIT4_Msk /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
9643 #define FMC_PATT4_ATTWAIT4_0 (0x01U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000100 */
9644 #define FMC_PATT4_ATTWAIT4_1 (0x02U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000200 */
9645 #define FMC_PATT4_ATTWAIT4_2 (0x04U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000400 */
9646 #define FMC_PATT4_ATTWAIT4_3 (0x08U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000800 */
9647 #define FMC_PATT4_ATTWAIT4_4 (0x10U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00001000 */
9648 #define FMC_PATT4_ATTWAIT4_5 (0x20U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00002000 */
9649 #define FMC_PATT4_ATTWAIT4_6 (0x40U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00004000 */
9650 #define FMC_PATT4_ATTWAIT4_7 (0x80U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00008000 */
9651
9652 #define FMC_PATT4_ATTHOLD4_Pos (16U)
9653 #define FMC_PATT4_ATTHOLD4_Msk (0xFFU << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00FF0000 */
9654 #define FMC_PATT4_ATTHOLD4 FMC_PATT4_ATTHOLD4_Msk /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
9655 #define FMC_PATT4_ATTHOLD4_0 (0x01U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00010000 */
9656 #define FMC_PATT4_ATTHOLD4_1 (0x02U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00020000 */
9657 #define FMC_PATT4_ATTHOLD4_2 (0x04U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00040000 */
9658 #define FMC_PATT4_ATTHOLD4_3 (0x08U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00080000 */
9659 #define FMC_PATT4_ATTHOLD4_4 (0x10U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00100000 */
9660 #define FMC_PATT4_ATTHOLD4_5 (0x20U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00200000 */
9661 #define FMC_PATT4_ATTHOLD4_6 (0x40U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00400000 */
9662 #define FMC_PATT4_ATTHOLD4_7 (0x80U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00800000 */
9663
9664 #define FMC_PATT4_ATTHIZ4_Pos (24U)
9665 #define FMC_PATT4_ATTHIZ4_Msk (0xFFU << FMC_PATT4_ATTHIZ4_Pos) /*!< 0xFF000000 */
9666 #define FMC_PATT4_ATTHIZ4 FMC_PATT4_ATTHIZ4_Msk /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
9667 #define FMC_PATT4_ATTHIZ4_0 (0x01U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x01000000 */
9668 #define FMC_PATT4_ATTHIZ4_1 (0x02U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x02000000 */
9669 #define FMC_PATT4_ATTHIZ4_2 (0x04U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x04000000 */
9670 #define FMC_PATT4_ATTHIZ4_3 (0x08U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x08000000 */
9671 #define FMC_PATT4_ATTHIZ4_4 (0x10U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x10000000 */
9672 #define FMC_PATT4_ATTHIZ4_5 (0x20U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x20000000 */
9673 #define FMC_PATT4_ATTHIZ4_6 (0x40U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x40000000 */
9674 #define FMC_PATT4_ATTHIZ4_7 (0x80U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x80000000 */
9675
9676 /****************** Bit definition for FMC_PIO4 register *******************/
9677 #define FMC_PIO4_IOSET4_Pos (0U)
9678 #define FMC_PIO4_IOSET4_Msk (0xFFU << FMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */
9679 #define FMC_PIO4_IOSET4 FMC_PIO4_IOSET4_Msk /*!<IOSET4[7:0] bits (I/O 4 setup time) */
9680 #define FMC_PIO4_IOSET4_0 (0x01U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */
9681 #define FMC_PIO4_IOSET4_1 (0x02U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */
9682 #define FMC_PIO4_IOSET4_2 (0x04U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */
9683 #define FMC_PIO4_IOSET4_3 (0x08U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */
9684 #define FMC_PIO4_IOSET4_4 (0x10U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */
9685 #define FMC_PIO4_IOSET4_5 (0x20U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */
9686 #define FMC_PIO4_IOSET4_6 (0x40U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */
9687 #define FMC_PIO4_IOSET4_7 (0x80U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */
9688
9689 #define FMC_PIO4_IOWAIT4_Pos (8U)
9690 #define FMC_PIO4_IOWAIT4_Msk (0xFFU << FMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */
9691 #define FMC_PIO4_IOWAIT4 FMC_PIO4_IOWAIT4_Msk /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
9692 #define FMC_PIO4_IOWAIT4_0 (0x01U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */
9693 #define FMC_PIO4_IOWAIT4_1 (0x02U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */
9694 #define FMC_PIO4_IOWAIT4_2 (0x04U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */
9695 #define FMC_PIO4_IOWAIT4_3 (0x08U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */
9696 #define FMC_PIO4_IOWAIT4_4 (0x10U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */
9697 #define FMC_PIO4_IOWAIT4_5 (0x20U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */
9698 #define FMC_PIO4_IOWAIT4_6 (0x40U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */
9699 #define FMC_PIO4_IOWAIT4_7 (0x80U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */
9700
9701 #define FMC_PIO4_IOHOLD4_Pos (16U)
9702 #define FMC_PIO4_IOHOLD4_Msk (0xFFU << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */
9703 #define FMC_PIO4_IOHOLD4 FMC_PIO4_IOHOLD4_Msk /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
9704 #define FMC_PIO4_IOHOLD4_0 (0x01U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */
9705 #define FMC_PIO4_IOHOLD4_1 (0x02U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */
9706 #define FMC_PIO4_IOHOLD4_2 (0x04U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */
9707 #define FMC_PIO4_IOHOLD4_3 (0x08U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */
9708 #define FMC_PIO4_IOHOLD4_4 (0x10U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */
9709 #define FMC_PIO4_IOHOLD4_5 (0x20U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */
9710 #define FMC_PIO4_IOHOLD4_6 (0x40U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */
9711 #define FMC_PIO4_IOHOLD4_7 (0x80U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */
9712
9713 #define FMC_PIO4_IOHIZ4_Pos (24U)
9714 #define FMC_PIO4_IOHIZ4_Msk (0xFFU << FMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */
9715 #define FMC_PIO4_IOHIZ4 FMC_PIO4_IOHIZ4_Msk /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
9716 #define FMC_PIO4_IOHIZ4_0 (0x01U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */
9717 #define FMC_PIO4_IOHIZ4_1 (0x02U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */
9718 #define FMC_PIO4_IOHIZ4_2 (0x04U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */
9719 #define FMC_PIO4_IOHIZ4_3 (0x08U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */
9720 #define FMC_PIO4_IOHIZ4_4 (0x10U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */
9721 #define FMC_PIO4_IOHIZ4_5 (0x20U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */
9722 #define FMC_PIO4_IOHIZ4_6 (0x40U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */
9723 #define FMC_PIO4_IOHIZ4_7 (0x80U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */
9724
9725 /****************** Bit definition for FMC_ECCR2 register ******************/
9726 #define FMC_ECCR2_ECC2_Pos (0U)
9727 #define FMC_ECCR2_ECC2_Msk (0xFFFFFFFFU << FMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */
9728 #define FMC_ECCR2_ECC2 FMC_ECCR2_ECC2_Msk /*!<ECC result */
9729
9730 /****************** Bit definition for FMC_ECCR3 register ******************/
9731 #define FMC_ECCR3_ECC3_Pos (0U)
9732 #define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFU << FMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
9733 #define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk /*!<ECC result */
9734
9735 /******************************************************************************/
9736 /* */
9737 /* General Purpose I/O (GPIO) */
9738 /* */
9739 /******************************************************************************/
9740 /******************* Bit definition for GPIO_MODER register *****************/
9741 #define GPIO_MODER_MODER0_Pos (0U)
9742 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
9743 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
9744 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
9745 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
9746 #define GPIO_MODER_MODER1_Pos (2U)
9747 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
9748 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
9749 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
9750 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
9751 #define GPIO_MODER_MODER2_Pos (4U)
9752 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
9753 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
9754 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
9755 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
9756 #define GPIO_MODER_MODER3_Pos (6U)
9757 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
9758 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
9759 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
9760 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
9761 #define GPIO_MODER_MODER4_Pos (8U)
9762 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
9763 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
9764 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
9765 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
9766 #define GPIO_MODER_MODER5_Pos (10U)
9767 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
9768 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
9769 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
9770 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
9771 #define GPIO_MODER_MODER6_Pos (12U)
9772 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
9773 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
9774 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
9775 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
9776 #define GPIO_MODER_MODER7_Pos (14U)
9777 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
9778 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
9779 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
9780 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
9781 #define GPIO_MODER_MODER8_Pos (16U)
9782 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
9783 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
9784 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
9785 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
9786 #define GPIO_MODER_MODER9_Pos (18U)
9787 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
9788 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
9789 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
9790 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
9791 #define GPIO_MODER_MODER10_Pos (20U)
9792 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
9793 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
9794 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
9795 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
9796 #define GPIO_MODER_MODER11_Pos (22U)
9797 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
9798 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
9799 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
9800 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
9801 #define GPIO_MODER_MODER12_Pos (24U)
9802 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
9803 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
9804 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
9805 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
9806 #define GPIO_MODER_MODER13_Pos (26U)
9807 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
9808 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
9809 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
9810 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
9811 #define GPIO_MODER_MODER14_Pos (28U)
9812 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
9813 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
9814 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
9815 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
9816 #define GPIO_MODER_MODER15_Pos (30U)
9817 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
9818 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
9819 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
9820 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
9821
9822 /****************** Bit definition for GPIO_OTYPER register *****************/
9823 #define GPIO_OTYPER_OT_0 (0x00000001U)
9824 #define GPIO_OTYPER_OT_1 (0x00000002U)
9825 #define GPIO_OTYPER_OT_2 (0x00000004U)
9826 #define GPIO_OTYPER_OT_3 (0x00000008U)
9827 #define GPIO_OTYPER_OT_4 (0x00000010U)
9828 #define GPIO_OTYPER_OT_5 (0x00000020U)
9829 #define GPIO_OTYPER_OT_6 (0x00000040U)
9830 #define GPIO_OTYPER_OT_7 (0x00000080U)
9831 #define GPIO_OTYPER_OT_8 (0x00000100U)
9832 #define GPIO_OTYPER_OT_9 (0x00000200U)
9833 #define GPIO_OTYPER_OT_10 (0x00000400U)
9834 #define GPIO_OTYPER_OT_11 (0x00000800U)
9835 #define GPIO_OTYPER_OT_12 (0x00001000U)
9836 #define GPIO_OTYPER_OT_13 (0x00002000U)
9837 #define GPIO_OTYPER_OT_14 (0x00004000U)
9838 #define GPIO_OTYPER_OT_15 (0x00008000U)
9839
9840 /**************** Bit definition for GPIO_OSPEEDR register ******************/
9841 #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
9842 #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
9843 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
9844 #define GPIO_OSPEEDER_OSPEEDR0_0 (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
9845 #define GPIO_OSPEEDER_OSPEEDR0_1 (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
9846 #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
9847 #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
9848 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
9849 #define GPIO_OSPEEDER_OSPEEDR1_0 (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
9850 #define GPIO_OSPEEDER_OSPEEDR1_1 (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
9851 #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
9852 #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
9853 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
9854 #define GPIO_OSPEEDER_OSPEEDR2_0 (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
9855 #define GPIO_OSPEEDER_OSPEEDR2_1 (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
9856 #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
9857 #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
9858 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
9859 #define GPIO_OSPEEDER_OSPEEDR3_0 (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
9860 #define GPIO_OSPEEDER_OSPEEDR3_1 (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
9861 #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
9862 #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
9863 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
9864 #define GPIO_OSPEEDER_OSPEEDR4_0 (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
9865 #define GPIO_OSPEEDER_OSPEEDR4_1 (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
9866 #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
9867 #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
9868 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
9869 #define GPIO_OSPEEDER_OSPEEDR5_0 (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
9870 #define GPIO_OSPEEDER_OSPEEDR5_1 (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
9871 #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
9872 #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
9873 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
9874 #define GPIO_OSPEEDER_OSPEEDR6_0 (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
9875 #define GPIO_OSPEEDER_OSPEEDR6_1 (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
9876 #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
9877 #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
9878 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
9879 #define GPIO_OSPEEDER_OSPEEDR7_0 (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
9880 #define GPIO_OSPEEDER_OSPEEDR7_1 (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
9881 #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
9882 #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
9883 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
9884 #define GPIO_OSPEEDER_OSPEEDR8_0 (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
9885 #define GPIO_OSPEEDER_OSPEEDR8_1 (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
9886 #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
9887 #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
9888 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
9889 #define GPIO_OSPEEDER_OSPEEDR9_0 (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
9890 #define GPIO_OSPEEDER_OSPEEDR9_1 (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
9891 #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
9892 #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
9893 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
9894 #define GPIO_OSPEEDER_OSPEEDR10_0 (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
9895 #define GPIO_OSPEEDER_OSPEEDR10_1 (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
9896 #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
9897 #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
9898 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
9899 #define GPIO_OSPEEDER_OSPEEDR11_0 (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
9900 #define GPIO_OSPEEDER_OSPEEDR11_1 (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
9901 #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
9902 #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
9903 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
9904 #define GPIO_OSPEEDER_OSPEEDR12_0 (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
9905 #define GPIO_OSPEEDER_OSPEEDR12_1 (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
9906 #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
9907 #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
9908 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
9909 #define GPIO_OSPEEDER_OSPEEDR13_0 (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
9910 #define GPIO_OSPEEDER_OSPEEDR13_1 (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
9911 #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
9912 #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
9913 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
9914 #define GPIO_OSPEEDER_OSPEEDR14_0 (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
9915 #define GPIO_OSPEEDER_OSPEEDR14_1 (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
9916 #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
9917 #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
9918 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
9919 #define GPIO_OSPEEDER_OSPEEDR15_0 (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
9920 #define GPIO_OSPEEDER_OSPEEDR15_1 (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
9921
9922 /******************* Bit definition for GPIO_PUPDR register ******************/
9923 #define GPIO_PUPDR_PUPDR0_Pos (0U)
9924 #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
9925 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
9926 #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
9927 #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
9928 #define GPIO_PUPDR_PUPDR1_Pos (2U)
9929 #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
9930 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
9931 #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
9932 #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
9933 #define GPIO_PUPDR_PUPDR2_Pos (4U)
9934 #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
9935 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
9936 #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
9937 #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
9938 #define GPIO_PUPDR_PUPDR3_Pos (6U)
9939 #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
9940 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
9941 #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
9942 #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
9943 #define GPIO_PUPDR_PUPDR4_Pos (8U)
9944 #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
9945 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
9946 #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
9947 #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
9948 #define GPIO_PUPDR_PUPDR5_Pos (10U)
9949 #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
9950 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
9951 #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
9952 #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
9953 #define GPIO_PUPDR_PUPDR6_Pos (12U)
9954 #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
9955 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
9956 #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
9957 #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
9958 #define GPIO_PUPDR_PUPDR7_Pos (14U)
9959 #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
9960 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
9961 #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
9962 #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
9963 #define GPIO_PUPDR_PUPDR8_Pos (16U)
9964 #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
9965 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
9966 #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
9967 #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
9968 #define GPIO_PUPDR_PUPDR9_Pos (18U)
9969 #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
9970 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
9971 #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
9972 #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
9973 #define GPIO_PUPDR_PUPDR10_Pos (20U)
9974 #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
9975 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
9976 #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
9977 #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
9978 #define GPIO_PUPDR_PUPDR11_Pos (22U)
9979 #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
9980 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
9981 #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
9982 #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
9983 #define GPIO_PUPDR_PUPDR12_Pos (24U)
9984 #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
9985 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
9986 #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
9987 #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
9988 #define GPIO_PUPDR_PUPDR13_Pos (26U)
9989 #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
9990 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
9991 #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
9992 #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
9993 #define GPIO_PUPDR_PUPDR14_Pos (28U)
9994 #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
9995 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
9996 #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
9997 #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
9998 #define GPIO_PUPDR_PUPDR15_Pos (30U)
9999 #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
10000 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
10001 #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
10002 #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
10003
10004 /******************* Bit definition for GPIO_IDR register *******************/
10005 #define GPIO_IDR_0 (0x00000001U)
10006 #define GPIO_IDR_1 (0x00000002U)
10007 #define GPIO_IDR_2 (0x00000004U)
10008 #define GPIO_IDR_3 (0x00000008U)
10009 #define GPIO_IDR_4 (0x00000010U)
10010 #define GPIO_IDR_5 (0x00000020U)
10011 #define GPIO_IDR_6 (0x00000040U)
10012 #define GPIO_IDR_7 (0x00000080U)
10013 #define GPIO_IDR_8 (0x00000100U)
10014 #define GPIO_IDR_9 (0x00000200U)
10015 #define GPIO_IDR_10 (0x00000400U)
10016 #define GPIO_IDR_11 (0x00000800U)
10017 #define GPIO_IDR_12 (0x00001000U)
10018 #define GPIO_IDR_13 (0x00002000U)
10019 #define GPIO_IDR_14 (0x00004000U)
10020 #define GPIO_IDR_15 (0x00008000U)
10021
10022 /****************** Bit definition for GPIO_ODR register ********************/
10023 #define GPIO_ODR_0 (0x00000001U)
10024 #define GPIO_ODR_1 (0x00000002U)
10025 #define GPIO_ODR_2 (0x00000004U)
10026 #define GPIO_ODR_3 (0x00000008U)
10027 #define GPIO_ODR_4 (0x00000010U)
10028 #define GPIO_ODR_5 (0x00000020U)
10029 #define GPIO_ODR_6 (0x00000040U)
10030 #define GPIO_ODR_7 (0x00000080U)
10031 #define GPIO_ODR_8 (0x00000100U)
10032 #define GPIO_ODR_9 (0x00000200U)
10033 #define GPIO_ODR_10 (0x00000400U)
10034 #define GPIO_ODR_11 (0x00000800U)
10035 #define GPIO_ODR_12 (0x00001000U)
10036 #define GPIO_ODR_13 (0x00002000U)
10037 #define GPIO_ODR_14 (0x00004000U)
10038 #define GPIO_ODR_15 (0x00008000U)
10039
10040 /****************** Bit definition for GPIO_BSRR register ********************/
10041 #define GPIO_BSRR_BS_0 (0x00000001U)
10042 #define GPIO_BSRR_BS_1 (0x00000002U)
10043 #define GPIO_BSRR_BS_2 (0x00000004U)
10044 #define GPIO_BSRR_BS_3 (0x00000008U)
10045 #define GPIO_BSRR_BS_4 (0x00000010U)
10046 #define GPIO_BSRR_BS_5 (0x00000020U)
10047 #define GPIO_BSRR_BS_6 (0x00000040U)
10048 #define GPIO_BSRR_BS_7 (0x00000080U)
10049 #define GPIO_BSRR_BS_8 (0x00000100U)
10050 #define GPIO_BSRR_BS_9 (0x00000200U)
10051 #define GPIO_BSRR_BS_10 (0x00000400U)
10052 #define GPIO_BSRR_BS_11 (0x00000800U)
10053 #define GPIO_BSRR_BS_12 (0x00001000U)
10054 #define GPIO_BSRR_BS_13 (0x00002000U)
10055 #define GPIO_BSRR_BS_14 (0x00004000U)
10056 #define GPIO_BSRR_BS_15 (0x00008000U)
10057 #define GPIO_BSRR_BR_0 (0x00010000U)
10058 #define GPIO_BSRR_BR_1 (0x00020000U)
10059 #define GPIO_BSRR_BR_2 (0x00040000U)
10060 #define GPIO_BSRR_BR_3 (0x00080000U)
10061 #define GPIO_BSRR_BR_4 (0x00100000U)
10062 #define GPIO_BSRR_BR_5 (0x00200000U)
10063 #define GPIO_BSRR_BR_6 (0x00400000U)
10064 #define GPIO_BSRR_BR_7 (0x00800000U)
10065 #define GPIO_BSRR_BR_8 (0x01000000U)
10066 #define GPIO_BSRR_BR_9 (0x02000000U)
10067 #define GPIO_BSRR_BR_10 (0x04000000U)
10068 #define GPIO_BSRR_BR_11 (0x08000000U)
10069 #define GPIO_BSRR_BR_12 (0x10000000U)
10070 #define GPIO_BSRR_BR_13 (0x20000000U)
10071 #define GPIO_BSRR_BR_14 (0x40000000U)
10072 #define GPIO_BSRR_BR_15 (0x80000000U)
10073
10074 /****************** Bit definition for GPIO_LCKR register ********************/
10075 #define GPIO_LCKR_LCK0_Pos (0U)
10076 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
10077 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
10078 #define GPIO_LCKR_LCK1_Pos (1U)
10079 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
10080 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
10081 #define GPIO_LCKR_LCK2_Pos (2U)
10082 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
10083 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
10084 #define GPIO_LCKR_LCK3_Pos (3U)
10085 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
10086 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
10087 #define GPIO_LCKR_LCK4_Pos (4U)
10088 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
10089 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
10090 #define GPIO_LCKR_LCK5_Pos (5U)
10091 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
10092 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
10093 #define GPIO_LCKR_LCK6_Pos (6U)
10094 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
10095 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
10096 #define GPIO_LCKR_LCK7_Pos (7U)
10097 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
10098 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
10099 #define GPIO_LCKR_LCK8_Pos (8U)
10100 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
10101 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
10102 #define GPIO_LCKR_LCK9_Pos (9U)
10103 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
10104 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
10105 #define GPIO_LCKR_LCK10_Pos (10U)
10106 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
10107 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
10108 #define GPIO_LCKR_LCK11_Pos (11U)
10109 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
10110 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
10111 #define GPIO_LCKR_LCK12_Pos (12U)
10112 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
10113 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
10114 #define GPIO_LCKR_LCK13_Pos (13U)
10115 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
10116 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
10117 #define GPIO_LCKR_LCK14_Pos (14U)
10118 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
10119 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
10120 #define GPIO_LCKR_LCK15_Pos (15U)
10121 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
10122 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
10123 #define GPIO_LCKR_LCKK_Pos (16U)
10124 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
10125 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
10126
10127 /****************** Bit definition for GPIO_AFRL register ********************/
10128 #define GPIO_AFRL_AFRL0_Pos (0U)
10129 #define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
10130 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
10131 #define GPIO_AFRL_AFRL1_Pos (4U)
10132 #define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
10133 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
10134 #define GPIO_AFRL_AFRL2_Pos (8U)
10135 #define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
10136 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
10137 #define GPIO_AFRL_AFRL3_Pos (12U)
10138 #define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
10139 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
10140 #define GPIO_AFRL_AFRL4_Pos (16U)
10141 #define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
10142 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
10143 #define GPIO_AFRL_AFRL5_Pos (20U)
10144 #define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
10145 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
10146 #define GPIO_AFRL_AFRL6_Pos (24U)
10147 #define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
10148 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
10149 #define GPIO_AFRL_AFRL7_Pos (28U)
10150 #define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
10151 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
10152
10153 /****************** Bit definition for GPIO_AFRH register ********************/
10154 #define GPIO_AFRH_AFRH0_Pos (0U)
10155 #define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
10156 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
10157 #define GPIO_AFRH_AFRH1_Pos (4U)
10158 #define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
10159 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
10160 #define GPIO_AFRH_AFRH2_Pos (8U)
10161 #define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
10162 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
10163 #define GPIO_AFRH_AFRH3_Pos (12U)
10164 #define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
10165 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
10166 #define GPIO_AFRH_AFRH4_Pos (16U)
10167 #define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
10168 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
10169 #define GPIO_AFRH_AFRH5_Pos (20U)
10170 #define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
10171 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
10172 #define GPIO_AFRH_AFRH6_Pos (24U)
10173 #define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
10174 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
10175 #define GPIO_AFRH_AFRH7_Pos (28U)
10176 #define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
10177 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
10178
10179 /****************** Bit definition for GPIO_BRR register *********************/
10180 #define GPIO_BRR_BR_0 (0x00000001U)
10181 #define GPIO_BRR_BR_1 (0x00000002U)
10182 #define GPIO_BRR_BR_2 (0x00000004U)
10183 #define GPIO_BRR_BR_3 (0x00000008U)
10184 #define GPIO_BRR_BR_4 (0x00000010U)
10185 #define GPIO_BRR_BR_5 (0x00000020U)
10186 #define GPIO_BRR_BR_6 (0x00000040U)
10187 #define GPIO_BRR_BR_7 (0x00000080U)
10188 #define GPIO_BRR_BR_8 (0x00000100U)
10189 #define GPIO_BRR_BR_9 (0x00000200U)
10190 #define GPIO_BRR_BR_10 (0x00000400U)
10191 #define GPIO_BRR_BR_11 (0x00000800U)
10192 #define GPIO_BRR_BR_12 (0x00001000U)
10193 #define GPIO_BRR_BR_13 (0x00002000U)
10194 #define GPIO_BRR_BR_14 (0x00004000U)
10195 #define GPIO_BRR_BR_15 (0x00008000U)
10196
10197 /******************************************************************************/
10198 /* */
10199 /* Inter-integrated Circuit Interface (I2C) */
10200 /* */
10201 /******************************************************************************/
10202 /******************* Bit definition for I2C_CR1 register *******************/
10203 #define I2C_CR1_PE_Pos (0U)
10204 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
10205 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
10206 #define I2C_CR1_TXIE_Pos (1U)
10207 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
10208 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
10209 #define I2C_CR1_RXIE_Pos (2U)
10210 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
10211 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
10212 #define I2C_CR1_ADDRIE_Pos (3U)
10213 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
10214 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
10215 #define I2C_CR1_NACKIE_Pos (4U)
10216 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
10217 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
10218 #define I2C_CR1_STOPIE_Pos (5U)
10219 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
10220 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
10221 #define I2C_CR1_TCIE_Pos (6U)
10222 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
10223 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
10224 #define I2C_CR1_ERRIE_Pos (7U)
10225 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
10226 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
10227 #define I2C_CR1_DNF_Pos (8U)
10228 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
10229 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
10230 #define I2C_CR1_ANFOFF_Pos (12U)
10231 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
10232 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
10233 #define I2C_CR1_SWRST_Pos (13U)
10234 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
10235 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
10236 #define I2C_CR1_TXDMAEN_Pos (14U)
10237 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
10238 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
10239 #define I2C_CR1_RXDMAEN_Pos (15U)
10240 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
10241 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
10242 #define I2C_CR1_SBC_Pos (16U)
10243 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
10244 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
10245 #define I2C_CR1_NOSTRETCH_Pos (17U)
10246 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
10247 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
10248 #define I2C_CR1_WUPEN_Pos (18U)
10249 #define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
10250 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
10251 #define I2C_CR1_GCEN_Pos (19U)
10252 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
10253 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
10254 #define I2C_CR1_SMBHEN_Pos (20U)
10255 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
10256 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
10257 #define I2C_CR1_SMBDEN_Pos (21U)
10258 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
10259 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
10260 #define I2C_CR1_ALERTEN_Pos (22U)
10261 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
10262 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
10263 #define I2C_CR1_PECEN_Pos (23U)
10264 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
10265 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
10266
10267 /* Legacy defines */
10268 #define I2C_CR1_DFN I2C_CR1_DNF
10269
10270 /****************** Bit definition for I2C_CR2 register ********************/
10271 #define I2C_CR2_SADD_Pos (0U)
10272 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
10273 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
10274 #define I2C_CR2_RD_WRN_Pos (10U)
10275 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
10276 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
10277 #define I2C_CR2_ADD10_Pos (11U)
10278 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
10279 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
10280 #define I2C_CR2_HEAD10R_Pos (12U)
10281 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
10282 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
10283 #define I2C_CR2_START_Pos (13U)
10284 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
10285 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
10286 #define I2C_CR2_STOP_Pos (14U)
10287 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
10288 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
10289 #define I2C_CR2_NACK_Pos (15U)
10290 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
10291 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
10292 #define I2C_CR2_NBYTES_Pos (16U)
10293 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
10294 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
10295 #define I2C_CR2_RELOAD_Pos (24U)
10296 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
10297 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
10298 #define I2C_CR2_AUTOEND_Pos (25U)
10299 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
10300 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
10301 #define I2C_CR2_PECBYTE_Pos (26U)
10302 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
10303 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
10304
10305 /******************* Bit definition for I2C_OAR1 register ******************/
10306 #define I2C_OAR1_OA1_Pos (0U)
10307 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
10308 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
10309 #define I2C_OAR1_OA1MODE_Pos (10U)
10310 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
10311 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
10312 #define I2C_OAR1_OA1EN_Pos (15U)
10313 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
10314 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
10315
10316 /******************* Bit definition for I2C_OAR2 register *******************/
10317 #define I2C_OAR2_OA2_Pos (1U)
10318 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
10319 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
10320 #define I2C_OAR2_OA2MSK_Pos (8U)
10321 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
10322 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
10323 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
10324 #define I2C_OAR2_OA2MASK01_Pos (8U)
10325 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
10326 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
10327 #define I2C_OAR2_OA2MASK02_Pos (9U)
10328 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
10329 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
10330 #define I2C_OAR2_OA2MASK03_Pos (8U)
10331 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
10332 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
10333 #define I2C_OAR2_OA2MASK04_Pos (10U)
10334 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
10335 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
10336 #define I2C_OAR2_OA2MASK05_Pos (8U)
10337 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
10338 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
10339 #define I2C_OAR2_OA2MASK06_Pos (9U)
10340 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
10341 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
10342 #define I2C_OAR2_OA2MASK07_Pos (8U)
10343 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
10344 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
10345 #define I2C_OAR2_OA2EN_Pos (15U)
10346 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
10347 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
10348
10349 /******************* Bit definition for I2C_TIMINGR register *****************/
10350 #define I2C_TIMINGR_SCLL_Pos (0U)
10351 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
10352 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
10353 #define I2C_TIMINGR_SCLH_Pos (8U)
10354 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
10355 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
10356 #define I2C_TIMINGR_SDADEL_Pos (16U)
10357 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
10358 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
10359 #define I2C_TIMINGR_SCLDEL_Pos (20U)
10360 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
10361 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
10362 #define I2C_TIMINGR_PRESC_Pos (28U)
10363 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
10364 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
10365
10366 /******************* Bit definition for I2C_TIMEOUTR register *****************/
10367 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
10368 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
10369 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
10370 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
10371 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
10372 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
10373 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
10374 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
10375 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
10376 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
10377 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
10378 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
10379 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
10380 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
10381 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
10382
10383 /****************** Bit definition for I2C_ISR register *********************/
10384 #define I2C_ISR_TXE_Pos (0U)
10385 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
10386 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
10387 #define I2C_ISR_TXIS_Pos (1U)
10388 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
10389 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
10390 #define I2C_ISR_RXNE_Pos (2U)
10391 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
10392 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
10393 #define I2C_ISR_ADDR_Pos (3U)
10394 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
10395 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
10396 #define I2C_ISR_NACKF_Pos (4U)
10397 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
10398 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
10399 #define I2C_ISR_STOPF_Pos (5U)
10400 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
10401 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
10402 #define I2C_ISR_TC_Pos (6U)
10403 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
10404 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
10405 #define I2C_ISR_TCR_Pos (7U)
10406 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
10407 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
10408 #define I2C_ISR_BERR_Pos (8U)
10409 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
10410 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
10411 #define I2C_ISR_ARLO_Pos (9U)
10412 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
10413 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
10414 #define I2C_ISR_OVR_Pos (10U)
10415 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
10416 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
10417 #define I2C_ISR_PECERR_Pos (11U)
10418 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
10419 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
10420 #define I2C_ISR_TIMEOUT_Pos (12U)
10421 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
10422 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
10423 #define I2C_ISR_ALERT_Pos (13U)
10424 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
10425 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
10426 #define I2C_ISR_BUSY_Pos (15U)
10427 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
10428 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
10429 #define I2C_ISR_DIR_Pos (16U)
10430 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
10431 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
10432 #define I2C_ISR_ADDCODE_Pos (17U)
10433 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
10434 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
10435
10436 /****************** Bit definition for I2C_ICR register *********************/
10437 #define I2C_ICR_ADDRCF_Pos (3U)
10438 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
10439 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
10440 #define I2C_ICR_NACKCF_Pos (4U)
10441 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
10442 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
10443 #define I2C_ICR_STOPCF_Pos (5U)
10444 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
10445 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
10446 #define I2C_ICR_BERRCF_Pos (8U)
10447 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
10448 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
10449 #define I2C_ICR_ARLOCF_Pos (9U)
10450 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
10451 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
10452 #define I2C_ICR_OVRCF_Pos (10U)
10453 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
10454 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
10455 #define I2C_ICR_PECCF_Pos (11U)
10456 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
10457 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
10458 #define I2C_ICR_TIMOUTCF_Pos (12U)
10459 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
10460 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
10461 #define I2C_ICR_ALERTCF_Pos (13U)
10462 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
10463 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
10464
10465 /****************** Bit definition for I2C_PECR register ********************/
10466 #define I2C_PECR_PEC_Pos (0U)
10467 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
10468 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
10469
10470 /****************** Bit definition for I2C_RXDR register *********************/
10471 #define I2C_RXDR_RXDATA_Pos (0U)
10472 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
10473 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
10474
10475 /****************** Bit definition for I2C_TXDR register *********************/
10476 #define I2C_TXDR_TXDATA_Pos (0U)
10477 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
10478 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
10479
10480
10481 /******************************************************************************/
10482 /* */
10483 /* Independent WATCHDOG (IWDG) */
10484 /* */
10485 /******************************************************************************/
10486 /******************* Bit definition for IWDG_KR register ********************/
10487 #define IWDG_KR_KEY_Pos (0U)
10488 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
10489 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
10490
10491 /******************* Bit definition for IWDG_PR register ********************/
10492 #define IWDG_PR_PR_Pos (0U)
10493 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
10494 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
10495 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
10496 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
10497 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
10498
10499 /******************* Bit definition for IWDG_RLR register *******************/
10500 #define IWDG_RLR_RL_Pos (0U)
10501 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
10502 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
10503
10504 /******************* Bit definition for IWDG_SR register ********************/
10505 #define IWDG_SR_PVU_Pos (0U)
10506 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
10507 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
10508 #define IWDG_SR_RVU_Pos (1U)
10509 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
10510 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
10511 #define IWDG_SR_WVU_Pos (2U)
10512 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
10513 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
10514
10515 /******************* Bit definition for IWDG_KR register ********************/
10516 #define IWDG_WINR_WIN_Pos (0U)
10517 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
10518 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
10519
10520 /******************************************************************************/
10521 /* */
10522 /* Power Control */
10523 /* */
10524 /******************************************************************************/
10525 #define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
10526 /******************** Bit definition for PWR_CR register ********************/
10527 #define PWR_CR_LPDS_Pos (0U)
10528 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
10529 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-power Deepsleep */
10530 #define PWR_CR_PDDS_Pos (1U)
10531 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
10532 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
10533 #define PWR_CR_CWUF_Pos (2U)
10534 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
10535 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
10536 #define PWR_CR_CSBF_Pos (3U)
10537 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
10538 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
10539 #define PWR_CR_PVDE_Pos (4U)
10540 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
10541 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
10542
10543 #define PWR_CR_PLS_Pos (5U)
10544 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
10545 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
10546 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
10547 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
10548 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
10549
10550 /*!< PVD level configuration */
10551 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
10552 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
10553 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
10554 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
10555 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
10556 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
10557 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
10558 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
10559
10560 #define PWR_CR_DBP_Pos (8U)
10561 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
10562 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
10563
10564 /******************* Bit definition for PWR_CSR register ********************/
10565 #define PWR_CSR_WUF_Pos (0U)
10566 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
10567 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
10568 #define PWR_CSR_SBF_Pos (1U)
10569 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
10570 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
10571 #define PWR_CSR_PVDO_Pos (2U)
10572 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
10573 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
10574 #define PWR_CSR_VREFINTRDYF_Pos (3U)
10575 #define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
10576 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
10577
10578 #define PWR_CSR_EWUP1_Pos (8U)
10579 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
10580 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
10581 #define PWR_CSR_EWUP2_Pos (9U)
10582 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
10583 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
10584 #define PWR_CSR_EWUP3_Pos (10U)
10585 #define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
10586 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
10587
10588 /******************************************************************************/
10589 /* */
10590 /* Reset and Clock Control */
10591 /* */
10592 /******************************************************************************/
10593 /*
10594 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
10595 */
10596 #define RCC_PLLSRC_PREDIV1_SUPPORT /*!< PREDIV support used as PLL source input */
10597
10598 /******************** Bit definition for RCC_CR register ********************/
10599 #define RCC_CR_HSION_Pos (0U)
10600 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
10601 #define RCC_CR_HSION RCC_CR_HSION_Msk
10602 #define RCC_CR_HSIRDY_Pos (1U)
10603 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
10604 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
10605
10606 #define RCC_CR_HSITRIM_Pos (3U)
10607 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
10608 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
10609 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
10610 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
10611 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
10612 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
10613 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
10614
10615 #define RCC_CR_HSICAL_Pos (8U)
10616 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
10617 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
10618 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
10619 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
10620 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
10621 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
10622 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
10623 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
10624 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
10625 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
10626
10627 #define RCC_CR_HSEON_Pos (16U)
10628 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
10629 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
10630 #define RCC_CR_HSERDY_Pos (17U)
10631 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
10632 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
10633 #define RCC_CR_HSEBYP_Pos (18U)
10634 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
10635 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
10636 #define RCC_CR_CSSON_Pos (19U)
10637 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
10638 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
10639 #define RCC_CR_PLLON_Pos (24U)
10640 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
10641 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
10642 #define RCC_CR_PLLRDY_Pos (25U)
10643 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
10644 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
10645
10646 /******************** Bit definition for RCC_CFGR register ******************/
10647 /*!< SW configuration */
10648 #define RCC_CFGR_SW_Pos (0U)
10649 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
10650 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
10651 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
10652 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
10653
10654 #define RCC_CFGR_SW_HSI (0x00000000U) /*!< HSI selected as system clock */
10655 #define RCC_CFGR_SW_HSE (0x00000001U) /*!< HSE selected as system clock */
10656 #define RCC_CFGR_SW_PLL (0x00000002U) /*!< PLL selected as system clock */
10657
10658 /*!< SWS configuration */
10659 #define RCC_CFGR_SWS_Pos (2U)
10660 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
10661 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
10662 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
10663 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
10664
10665 #define RCC_CFGR_SWS_HSI (0x00000000U) /*!< HSI oscillator used as system clock */
10666 #define RCC_CFGR_SWS_HSE (0x00000004U) /*!< HSE oscillator used as system clock */
10667 #define RCC_CFGR_SWS_PLL (0x00000008U) /*!< PLL used as system clock */
10668
10669 /*!< HPRE configuration */
10670 #define RCC_CFGR_HPRE_Pos (4U)
10671 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
10672 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
10673 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
10674 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
10675 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
10676 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
10677
10678 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
10679 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
10680 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
10681 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
10682 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
10683 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
10684 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
10685 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
10686 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
10687
10688 /*!< PPRE1 configuration */
10689 #define RCC_CFGR_PPRE1_Pos (8U)
10690 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
10691 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
10692 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
10693 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
10694 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
10695
10696 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
10697 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
10698 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
10699 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
10700 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
10701
10702 /*!< PPRE2 configuration */
10703 #define RCC_CFGR_PPRE2_Pos (11U)
10704 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
10705 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
10706 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
10707 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
10708 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
10709
10710 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
10711 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
10712 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
10713 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
10714 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
10715
10716 #define RCC_CFGR_PLLSRC_Pos (15U)
10717 #define RCC_CFGR_PLLSRC_Msk (0x3U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00018000 */
10718 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
10719 #define RCC_CFGR_PLLSRC_HSI_PREDIV (0x00008000U) /*!< HSI/PREDIV clock as PLL entry clock source */
10720 #define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U) /*!< HSE/PREDIV clock selected as PLL entry clock source */
10721
10722 #define RCC_CFGR_PLLXTPRE_Pos (17U)
10723 #define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
10724 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
10725 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U) /*!< HSE/PREDIV clock not divided for PLL entry */
10726 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
10727
10728 /*!< PLLMUL configuration */
10729 #define RCC_CFGR_PLLMUL_Pos (18U)
10730 #define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
10731 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
10732 #define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
10733 #define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
10734 #define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
10735 #define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
10736
10737 #define RCC_CFGR_PLLMUL2 (0x00000000U) /*!< PLL input clock*2 */
10738 #define RCC_CFGR_PLLMUL3 (0x00040000U) /*!< PLL input clock*3 */
10739 #define RCC_CFGR_PLLMUL4 (0x00080000U) /*!< PLL input clock*4 */
10740 #define RCC_CFGR_PLLMUL5 (0x000C0000U) /*!< PLL input clock*5 */
10741 #define RCC_CFGR_PLLMUL6 (0x00100000U) /*!< PLL input clock*6 */
10742 #define RCC_CFGR_PLLMUL7 (0x00140000U) /*!< PLL input clock*7 */
10743 #define RCC_CFGR_PLLMUL8 (0x00180000U) /*!< PLL input clock*8 */
10744 #define RCC_CFGR_PLLMUL9 (0x001C0000U) /*!< PLL input clock*9 */
10745 #define RCC_CFGR_PLLMUL10 (0x00200000U) /*!< PLL input clock10 */
10746 #define RCC_CFGR_PLLMUL11 (0x00240000U) /*!< PLL input clock*11 */
10747 #define RCC_CFGR_PLLMUL12 (0x00280000U) /*!< PLL input clock*12 */
10748 #define RCC_CFGR_PLLMUL13 (0x002C0000U) /*!< PLL input clock*13 */
10749 #define RCC_CFGR_PLLMUL14 (0x00300000U) /*!< PLL input clock*14 */
10750 #define RCC_CFGR_PLLMUL15 (0x00340000U) /*!< PLL input clock*15 */
10751 #define RCC_CFGR_PLLMUL16 (0x00380000U) /*!< PLL input clock*16 */
10752
10753 /*!< USB configuration */
10754 #define RCC_CFGR_USBPRE_Pos (22U)
10755 #define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */
10756 #define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB prescaler */
10757
10758 #define RCC_CFGR_USBPRE_DIV1_5 (0x00000000U) /*!< USB prescaler is PLL clock divided by 1.5 */
10759 #define RCC_CFGR_USBPRE_DIV1 (0x00400000U) /*!< USB prescaler is PLL clock divided by 1 */
10760
10761 /*!< I2S configuration */
10762 #define RCC_CFGR_I2SSRC_Pos (23U)
10763 #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
10764 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk /*!< I2S external clock source selection */
10765
10766 #define RCC_CFGR_I2SSRC_SYSCLK (0x00000000U) /*!< System clock selected as I2S clock source */
10767 #define RCC_CFGR_I2SSRC_EXT (0x00800000U) /*!< External clock selected as I2S clock source */
10768
10769 /*!< MCO configuration */
10770 #define RCC_CFGR_MCO_Pos (24U)
10771 #define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
10772 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
10773 #define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
10774 #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
10775 #define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
10776
10777 #define RCC_CFGR_MCO_NOCLOCK (0x00000000U) /*!< No clock */
10778 #define RCC_CFGR_MCO_LSI (0x02000000U) /*!< LSI clock selected as MCO source */
10779 #define RCC_CFGR_MCO_LSE (0x03000000U) /*!< LSE clock selected as MCO source */
10780 #define RCC_CFGR_MCO_SYSCLK (0x04000000U) /*!< System clock selected as MCO source */
10781 #define RCC_CFGR_MCO_HSI (0x05000000U) /*!< HSI clock selected as MCO source */
10782 #define RCC_CFGR_MCO_HSE (0x06000000U) /*!< HSE clock selected as MCO source */
10783 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divided by 2 selected as MCO source */
10784
10785 #define RCC_CFGR_MCOPRE_Pos (28U)
10786 #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
10787 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCOPRE[3:0] bits (Microcontroller Clock Output Prescaler) */
10788 #define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
10789 #define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
10790 #define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
10791
10792 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
10793 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
10794 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
10795 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
10796 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
10797 #define RCC_CFGR_MCOPRE_DIV32 (0x50000000U) /*!< MCO is divided by 32 */
10798 #define RCC_CFGR_MCOPRE_DIV64 (0x60000000U) /*!< MCO is divided by 64 */
10799 #define RCC_CFGR_MCOPRE_DIV128 (0x70000000U) /*!< MCO is divided by 128 */
10800
10801 #define RCC_CFGR_PLLNODIV_Pos (31U)
10802 #define RCC_CFGR_PLLNODIV_Msk (0x1U << RCC_CFGR_PLLNODIV_Pos) /*!< 0x80000000 */
10803 #define RCC_CFGR_PLLNODIV RCC_CFGR_PLLNODIV_Msk /*!< Do not divide PLL to MCO */
10804
10805 /* Reference defines */
10806 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
10807 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
10808 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
10809 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
10810 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
10811 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI
10812 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE
10813 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
10814 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
10815 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
10816 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
10817
10818 /********************* Bit definition for RCC_CIR register ********************/
10819 #define RCC_CIR_LSIRDYF_Pos (0U)
10820 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
10821 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
10822 #define RCC_CIR_LSERDYF_Pos (1U)
10823 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
10824 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
10825 #define RCC_CIR_HSIRDYF_Pos (2U)
10826 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
10827 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
10828 #define RCC_CIR_HSERDYF_Pos (3U)
10829 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
10830 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
10831 #define RCC_CIR_PLLRDYF_Pos (4U)
10832 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
10833 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
10834 #define RCC_CIR_CSSF_Pos (7U)
10835 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
10836 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
10837 #define RCC_CIR_LSIRDYIE_Pos (8U)
10838 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
10839 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
10840 #define RCC_CIR_LSERDYIE_Pos (9U)
10841 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
10842 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
10843 #define RCC_CIR_HSIRDYIE_Pos (10U)
10844 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
10845 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
10846 #define RCC_CIR_HSERDYIE_Pos (11U)
10847 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
10848 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
10849 #define RCC_CIR_PLLRDYIE_Pos (12U)
10850 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
10851 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
10852 #define RCC_CIR_LSIRDYC_Pos (16U)
10853 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
10854 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
10855 #define RCC_CIR_LSERDYC_Pos (17U)
10856 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
10857 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
10858 #define RCC_CIR_HSIRDYC_Pos (18U)
10859 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
10860 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
10861 #define RCC_CIR_HSERDYC_Pos (19U)
10862 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
10863 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
10864 #define RCC_CIR_PLLRDYC_Pos (20U)
10865 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
10866 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
10867 #define RCC_CIR_CSSC_Pos (23U)
10868 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
10869 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
10870
10871 /****************** Bit definition for RCC_APB2RSTR register *****************/
10872 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
10873 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
10874 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
10875 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
10876 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
10877 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */
10878 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
10879 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
10880 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
10881 #define RCC_APB2RSTR_TIM8RST_Pos (13U)
10882 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */
10883 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 reset */
10884 #define RCC_APB2RSTR_USART1RST_Pos (14U)
10885 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
10886 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
10887 #define RCC_APB2RSTR_SPI4RST_Pos (15U)
10888 #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00008000 */
10889 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk /*!< SPI4 reset */
10890 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
10891 #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
10892 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */
10893 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
10894 #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
10895 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */
10896 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
10897 #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
10898 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */
10899 #define RCC_APB2RSTR_TIM20RST_Pos (20U)
10900 #define RCC_APB2RSTR_TIM20RST_Msk (0x1U << RCC_APB2RSTR_TIM20RST_Pos) /*!< 0x00100000 */
10901 #define RCC_APB2RSTR_TIM20RST RCC_APB2RSTR_TIM20RST_Msk /*!< TIM20 reset */
10902
10903 /****************** Bit definition for RCC_APB1RSTR register ******************/
10904 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
10905 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
10906 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
10907 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
10908 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
10909 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
10910 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
10911 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
10912 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
10913 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
10914 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
10915 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
10916 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
10917 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
10918 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */
10919 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
10920 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
10921 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
10922 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
10923 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
10924 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */
10925 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
10926 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
10927 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI3 reset */
10928 #define RCC_APB1RSTR_USART2RST_Pos (17U)
10929 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
10930 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
10931 #define RCC_APB1RSTR_USART3RST_Pos (18U)
10932 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
10933 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
10934 #define RCC_APB1RSTR_UART4RST_Pos (19U)
10935 #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
10936 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */
10937 #define RCC_APB1RSTR_UART5RST_Pos (20U)
10938 #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
10939 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */
10940 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
10941 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
10942 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
10943 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
10944 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
10945 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
10946 #define RCC_APB1RSTR_USBRST_Pos (23U)
10947 #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
10948 #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */
10949 #define RCC_APB1RSTR_CANRST_Pos (25U)
10950 #define RCC_APB1RSTR_CANRST_Msk (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */
10951 #define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN reset */
10952 #define RCC_APB1RSTR_PWRRST_Pos (28U)
10953 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
10954 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
10955 #define RCC_APB1RSTR_DAC1RST_Pos (29U)
10956 #define RCC_APB1RSTR_DAC1RST_Msk (0x1U << RCC_APB1RSTR_DAC1RST_Pos) /*!< 0x20000000 */
10957 #define RCC_APB1RSTR_DAC1RST RCC_APB1RSTR_DAC1RST_Msk /*!< DAC 1 reset */
10958 #define RCC_APB1RSTR_I2C3RST_Pos (30U)
10959 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x40000000 */
10960 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk /*!< I2C 3 reset */
10961
10962 /****************** Bit definition for RCC_AHBENR register ******************/
10963 #define RCC_AHBENR_DMA1EN_Pos (0U)
10964 #define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
10965 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
10966 #define RCC_AHBENR_DMA2EN_Pos (1U)
10967 #define RCC_AHBENR_DMA2EN_Msk (0x1U << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */
10968 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */
10969 #define RCC_AHBENR_SRAMEN_Pos (2U)
10970 #define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
10971 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
10972 #define RCC_AHBENR_FLITFEN_Pos (4U)
10973 #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
10974 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
10975 #define RCC_AHBENR_FMCEN_Pos (5U)
10976 #define RCC_AHBENR_FMCEN_Msk (0x1U << RCC_AHBENR_FMCEN_Pos) /*!< 0x00000020 */
10977 #define RCC_AHBENR_FMCEN RCC_AHBENR_FMCEN_Msk /*!< FMC clock enable */
10978 #define RCC_AHBENR_CRCEN_Pos (6U)
10979 #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
10980 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
10981 #define RCC_AHBENR_GPIOHEN_Pos (16U)
10982 #define RCC_AHBENR_GPIOHEN_Msk (0x1U << RCC_AHBENR_GPIOHEN_Pos) /*!< 0x00010000 */
10983 #define RCC_AHBENR_GPIOHEN RCC_AHBENR_GPIOHEN_Msk /*!< GPIOH clock enable */
10984 #define RCC_AHBENR_GPIOAEN_Pos (17U)
10985 #define RCC_AHBENR_GPIOAEN_Msk (0x1U << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */
10986 #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIOA clock enable */
10987 #define RCC_AHBENR_GPIOBEN_Pos (18U)
10988 #define RCC_AHBENR_GPIOBEN_Msk (0x1U << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */
10989 #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIOB clock enable */
10990 #define RCC_AHBENR_GPIOCEN_Pos (19U)
10991 #define RCC_AHBENR_GPIOCEN_Msk (0x1U << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */
10992 #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIOC clock enable */
10993 #define RCC_AHBENR_GPIODEN_Pos (20U)
10994 #define RCC_AHBENR_GPIODEN_Msk (0x1U << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00100000 */
10995 #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIOD clock enable */
10996 #define RCC_AHBENR_GPIOEEN_Pos (21U)
10997 #define RCC_AHBENR_GPIOEEN_Msk (0x1U << RCC_AHBENR_GPIOEEN_Pos) /*!< 0x00200000 */
10998 #define RCC_AHBENR_GPIOEEN RCC_AHBENR_GPIOEEN_Msk /*!< GPIOE clock enable */
10999 #define RCC_AHBENR_GPIOFEN_Pos (22U)
11000 #define RCC_AHBENR_GPIOFEN_Msk (0x1U << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */
11001 #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIOF clock enable */
11002 #define RCC_AHBENR_GPIOGEN_Pos (23U)
11003 #define RCC_AHBENR_GPIOGEN_Msk (0x1U << RCC_AHBENR_GPIOGEN_Pos) /*!< 0x00800000 */
11004 #define RCC_AHBENR_GPIOGEN RCC_AHBENR_GPIOGEN_Msk /*!< GPIOG clock enable */
11005 #define RCC_AHBENR_TSCEN_Pos (24U)
11006 #define RCC_AHBENR_TSCEN_Msk (0x1U << RCC_AHBENR_TSCEN_Pos) /*!< 0x01000000 */
11007 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TS clock enable */
11008 #define RCC_AHBENR_ADC12EN_Pos (28U)
11009 #define RCC_AHBENR_ADC12EN_Msk (0x1U << RCC_AHBENR_ADC12EN_Pos) /*!< 0x10000000 */
11010 #define RCC_AHBENR_ADC12EN RCC_AHBENR_ADC12EN_Msk /*!< ADC1/ ADC2 clock enable */
11011 #define RCC_AHBENR_ADC34EN_Pos (29U)
11012 #define RCC_AHBENR_ADC34EN_Msk (0x1U << RCC_AHBENR_ADC34EN_Pos) /*!< 0x20000000 */
11013 #define RCC_AHBENR_ADC34EN RCC_AHBENR_ADC34EN_Msk /*!< ADC3/ ADC4 clock enable */
11014
11015 /***************** Bit definition for RCC_APB2ENR register ******************/
11016 #define RCC_APB2ENR_SYSCFGEN_Pos (0U)
11017 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
11018 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
11019 #define RCC_APB2ENR_TIM1EN_Pos (11U)
11020 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
11021 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */
11022 #define RCC_APB2ENR_SPI1EN_Pos (12U)
11023 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
11024 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
11025 #define RCC_APB2ENR_TIM8EN_Pos (13U)
11026 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
11027 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 clock enable */
11028 #define RCC_APB2ENR_USART1EN_Pos (14U)
11029 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
11030 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
11031 #define RCC_APB2ENR_SPI4EN_Pos (15U)
11032 #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00008000 */
11033 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk /*!< SPI4 clock enable */
11034 #define RCC_APB2ENR_TIM15EN_Pos (16U)
11035 #define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
11036 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */
11037 #define RCC_APB2ENR_TIM16EN_Pos (17U)
11038 #define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
11039 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */
11040 #define RCC_APB2ENR_TIM17EN_Pos (18U)
11041 #define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
11042 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */
11043 #define RCC_APB2ENR_TIM20EN_Pos (20U)
11044 #define RCC_APB2ENR_TIM20EN_Msk (0x1U << RCC_APB2ENR_TIM20EN_Pos) /*!< 0x00100000 */
11045 #define RCC_APB2ENR_TIM20EN RCC_APB2ENR_TIM20EN_Msk /*!< TIM20 clock enable */
11046
11047 /****************** Bit definition for RCC_APB1ENR register ******************/
11048 #define RCC_APB1ENR_TIM2EN_Pos (0U)
11049 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
11050 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
11051 #define RCC_APB1ENR_TIM3EN_Pos (1U)
11052 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
11053 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
11054 #define RCC_APB1ENR_TIM4EN_Pos (2U)
11055 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
11056 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
11057 #define RCC_APB1ENR_TIM6EN_Pos (4U)
11058 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
11059 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
11060 #define RCC_APB1ENR_TIM7EN_Pos (5U)
11061 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
11062 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
11063 #define RCC_APB1ENR_WWDGEN_Pos (11U)
11064 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
11065 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
11066 #define RCC_APB1ENR_SPI2EN_Pos (14U)
11067 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
11068 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */
11069 #define RCC_APB1ENR_SPI3EN_Pos (15U)
11070 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
11071 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI3 clock enable */
11072 #define RCC_APB1ENR_USART2EN_Pos (17U)
11073 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
11074 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
11075 #define RCC_APB1ENR_USART3EN_Pos (18U)
11076 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
11077 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
11078 #define RCC_APB1ENR_UART4EN_Pos (19U)
11079 #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
11080 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */
11081 #define RCC_APB1ENR_UART5EN_Pos (20U)
11082 #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
11083 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */
11084 #define RCC_APB1ENR_I2C1EN_Pos (21U)
11085 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
11086 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
11087 #define RCC_APB1ENR_I2C2EN_Pos (22U)
11088 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
11089 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
11090 #define RCC_APB1ENR_USBEN_Pos (23U)
11091 #define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
11092 #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */
11093 #define RCC_APB1ENR_CANEN_Pos (25U)
11094 #define RCC_APB1ENR_CANEN_Msk (0x1U << RCC_APB1ENR_CANEN_Pos) /*!< 0x02000000 */
11095 #define RCC_APB1ENR_CANEN RCC_APB1ENR_CANEN_Msk /*!< CAN clock enable */
11096 #define RCC_APB1ENR_PWREN_Pos (28U)
11097 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
11098 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
11099 #define RCC_APB1ENR_DAC1EN_Pos (29U)
11100 #define RCC_APB1ENR_DAC1EN_Msk (0x1U << RCC_APB1ENR_DAC1EN_Pos) /*!< 0x20000000 */
11101 #define RCC_APB1ENR_DAC1EN RCC_APB1ENR_DAC1EN_Msk /*!< DAC 1 clock enable */
11102 #define RCC_APB1ENR_I2C3EN_Pos (30U)
11103 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x40000000 */
11104 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C 3 clock enable */
11105
11106 /******************** Bit definition for RCC_BDCR register ******************/
11107 #define RCC_BDCR_LSE_Pos (0U)
11108 #define RCC_BDCR_LSE_Msk (0x7U << RCC_BDCR_LSE_Pos) /*!< 0x00000007 */
11109 #define RCC_BDCR_LSE RCC_BDCR_LSE_Msk /*!< External Low Speed oscillator [2:0] bits */
11110 #define RCC_BDCR_LSEON_Pos (0U)
11111 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
11112 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
11113 #define RCC_BDCR_LSERDY_Pos (1U)
11114 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
11115 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
11116 #define RCC_BDCR_LSEBYP_Pos (2U)
11117 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
11118 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
11119
11120 #define RCC_BDCR_LSEDRV_Pos (3U)
11121 #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
11122 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
11123 #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
11124 #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
11125
11126 #define RCC_BDCR_RTCSEL_Pos (8U)
11127 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
11128 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
11129 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
11130 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
11131
11132 /*!< RTC configuration */
11133 #define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
11134 #define RCC_BDCR_RTCSEL_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock */
11135 #define RCC_BDCR_RTCSEL_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock */
11136 #define RCC_BDCR_RTCSEL_HSE (0x00000300U) /*!< HSE oscillator clock divided by 32 used as RTC clock */
11137
11138 #define RCC_BDCR_RTCEN_Pos (15U)
11139 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
11140 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
11141 #define RCC_BDCR_BDRST_Pos (16U)
11142 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
11143 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
11144
11145 /******************** Bit definition for RCC_CSR register *******************/
11146 #define RCC_CSR_LSION_Pos (0U)
11147 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
11148 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
11149 #define RCC_CSR_LSIRDY_Pos (1U)
11150 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
11151 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
11152 #define RCC_CSR_V18PWRRSTF_Pos (23U)
11153 #define RCC_CSR_V18PWRRSTF_Msk (0x1U << RCC_CSR_V18PWRRSTF_Pos) /*!< 0x00800000 */
11154 #define RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk /*!< V1.8 power domain reset flag */
11155 #define RCC_CSR_RMVF_Pos (24U)
11156 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
11157 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
11158 #define RCC_CSR_OBLRSTF_Pos (25U)
11159 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
11160 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
11161 #define RCC_CSR_PINRSTF_Pos (26U)
11162 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
11163 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
11164 #define RCC_CSR_PORRSTF_Pos (27U)
11165 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
11166 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
11167 #define RCC_CSR_SFTRSTF_Pos (28U)
11168 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
11169 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
11170 #define RCC_CSR_IWDGRSTF_Pos (29U)
11171 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
11172 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
11173 #define RCC_CSR_WWDGRSTF_Pos (30U)
11174 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
11175 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
11176 #define RCC_CSR_LPWRRSTF_Pos (31U)
11177 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
11178 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
11179
11180 /* Legacy defines */
11181 #define RCC_CSR_VREGRSTF RCC_CSR_V18PWRRSTF
11182
11183 /******************* Bit definition for RCC_AHBRSTR register ****************/
11184 #define RCC_AHBRSTR_FMCRST_Pos (5U)
11185 #define RCC_AHBRSTR_FMCRST_Msk (0x1U << RCC_AHBRSTR_FMCRST_Pos) /*!< 0x00000020 */
11186 #define RCC_AHBRSTR_FMCRST RCC_AHBRSTR_FMCRST_Msk /*!< FMC reset */
11187 #define RCC_AHBRSTR_GPIOHRST_Pos (16U)
11188 #define RCC_AHBRSTR_GPIOHRST_Msk (0x1U << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00010000 */
11189 #define RCC_AHBRSTR_GPIOHRST RCC_AHBRSTR_GPIOHRST_Msk /*!< GPIOH reset */
11190 #define RCC_AHBRSTR_GPIOARST_Pos (17U)
11191 #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
11192 #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */
11193 #define RCC_AHBRSTR_GPIOBRST_Pos (18U)
11194 #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
11195 #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */
11196 #define RCC_AHBRSTR_GPIOCRST_Pos (19U)
11197 #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
11198 #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */
11199 #define RCC_AHBRSTR_GPIODRST_Pos (20U)
11200 #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
11201 #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */
11202 #define RCC_AHBRSTR_GPIOERST_Pos (21U)
11203 #define RCC_AHBRSTR_GPIOERST_Msk (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00200000 */
11204 #define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIOE reset */
11205 #define RCC_AHBRSTR_GPIOFRST_Pos (22U)
11206 #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
11207 #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */
11208 #define RCC_AHBRSTR_GPIOGRST_Pos (23U)
11209 #define RCC_AHBRSTR_GPIOGRST_Msk (0x1U << RCC_AHBRSTR_GPIOGRST_Pos) /*!< 0x00800000 */
11210 #define RCC_AHBRSTR_GPIOGRST RCC_AHBRSTR_GPIOGRST_Msk /*!< GPIOG reset */
11211 #define RCC_AHBRSTR_TSCRST_Pos (24U)
11212 #define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */
11213 #define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TSC reset */
11214 #define RCC_AHBRSTR_ADC12RST_Pos (28U)
11215 #define RCC_AHBRSTR_ADC12RST_Msk (0x1U << RCC_AHBRSTR_ADC12RST_Pos) /*!< 0x10000000 */
11216 #define RCC_AHBRSTR_ADC12RST RCC_AHBRSTR_ADC12RST_Msk /*!< ADC1 & ADC2 reset */
11217 #define RCC_AHBRSTR_ADC34RST_Pos (29U)
11218 #define RCC_AHBRSTR_ADC34RST_Msk (0x1U << RCC_AHBRSTR_ADC34RST_Pos) /*!< 0x20000000 */
11219 #define RCC_AHBRSTR_ADC34RST RCC_AHBRSTR_ADC34RST_Msk /*!< ADC3 & ADC4 reset */
11220
11221 /******************* Bit definition for RCC_CFGR2 register ******************/
11222 /*!< PREDIV configuration */
11223 #define RCC_CFGR2_PREDIV_Pos (0U)
11224 #define RCC_CFGR2_PREDIV_Msk (0xFU << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */
11225 #define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk /*!< PREDIV[3:0] bits */
11226 #define RCC_CFGR2_PREDIV_0 (0x1U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */
11227 #define RCC_CFGR2_PREDIV_1 (0x2U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */
11228 #define RCC_CFGR2_PREDIV_2 (0x4U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */
11229 #define RCC_CFGR2_PREDIV_3 (0x8U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */
11230
11231 #define RCC_CFGR2_PREDIV_DIV1 (0x00000000U) /*!< PREDIV input clock not divided */
11232 #define RCC_CFGR2_PREDIV_DIV2 (0x00000001U) /*!< PREDIV input clock divided by 2 */
11233 #define RCC_CFGR2_PREDIV_DIV3 (0x00000002U) /*!< PREDIV input clock divided by 3 */
11234 #define RCC_CFGR2_PREDIV_DIV4 (0x00000003U) /*!< PREDIV input clock divided by 4 */
11235 #define RCC_CFGR2_PREDIV_DIV5 (0x00000004U) /*!< PREDIV input clock divided by 5 */
11236 #define RCC_CFGR2_PREDIV_DIV6 (0x00000005U) /*!< PREDIV input clock divided by 6 */
11237 #define RCC_CFGR2_PREDIV_DIV7 (0x00000006U) /*!< PREDIV input clock divided by 7 */
11238 #define RCC_CFGR2_PREDIV_DIV8 (0x00000007U) /*!< PREDIV input clock divided by 8 */
11239 #define RCC_CFGR2_PREDIV_DIV9 (0x00000008U) /*!< PREDIV input clock divided by 9 */
11240 #define RCC_CFGR2_PREDIV_DIV10 (0x00000009U) /*!< PREDIV input clock divided by 10 */
11241 #define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU) /*!< PREDIV input clock divided by 11 */
11242 #define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU) /*!< PREDIV input clock divided by 12 */
11243 #define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU) /*!< PREDIV input clock divided by 13 */
11244 #define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU) /*!< PREDIV input clock divided by 14 */
11245 #define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU) /*!< PREDIV input clock divided by 15 */
11246 #define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU) /*!< PREDIV input clock divided by 16 */
11247
11248 /*!< ADCPRE12 configuration */
11249 #define RCC_CFGR2_ADCPRE12_Pos (4U)
11250 #define RCC_CFGR2_ADCPRE12_Msk (0x1FU << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x000001F0 */
11251 #define RCC_CFGR2_ADCPRE12 RCC_CFGR2_ADCPRE12_Msk /*!< ADCPRE12[8:4] bits */
11252 #define RCC_CFGR2_ADCPRE12_0 (0x01U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000010 */
11253 #define RCC_CFGR2_ADCPRE12_1 (0x02U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000020 */
11254 #define RCC_CFGR2_ADCPRE12_2 (0x04U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000040 */
11255 #define RCC_CFGR2_ADCPRE12_3 (0x08U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000080 */
11256 #define RCC_CFGR2_ADCPRE12_4 (0x10U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000100 */
11257
11258 #define RCC_CFGR2_ADCPRE12_NO (0x00000000U) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
11259 #define RCC_CFGR2_ADCPRE12_DIV1 (0x00000100U) /*!< ADC12 PLL clock divided by 1 */
11260 #define RCC_CFGR2_ADCPRE12_DIV2 (0x00000110U) /*!< ADC12 PLL clock divided by 2 */
11261 #define RCC_CFGR2_ADCPRE12_DIV4 (0x00000120U) /*!< ADC12 PLL clock divided by 4 */
11262 #define RCC_CFGR2_ADCPRE12_DIV6 (0x00000130U) /*!< ADC12 PLL clock divided by 6 */
11263 #define RCC_CFGR2_ADCPRE12_DIV8 (0x00000140U) /*!< ADC12 PLL clock divided by 8 */
11264 #define RCC_CFGR2_ADCPRE12_DIV10 (0x00000150U) /*!< ADC12 PLL clock divided by 10 */
11265 #define RCC_CFGR2_ADCPRE12_DIV12 (0x00000160U) /*!< ADC12 PLL clock divided by 12 */
11266 #define RCC_CFGR2_ADCPRE12_DIV16 (0x00000170U) /*!< ADC12 PLL clock divided by 16 */
11267 #define RCC_CFGR2_ADCPRE12_DIV32 (0x00000180U) /*!< ADC12 PLL clock divided by 32 */
11268 #define RCC_CFGR2_ADCPRE12_DIV64 (0x00000190U) /*!< ADC12 PLL clock divided by 64 */
11269 #define RCC_CFGR2_ADCPRE12_DIV128 (0x000001A0U) /*!< ADC12 PLL clock divided by 128 */
11270 #define RCC_CFGR2_ADCPRE12_DIV256 (0x000001B0U) /*!< ADC12 PLL clock divided by 256 */
11271
11272 /*!< ADCPRE34 configuration */
11273 #define RCC_CFGR2_ADCPRE34_Pos (9U)
11274 #define RCC_CFGR2_ADCPRE34_Msk (0x1FU << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00003E00 */
11275 #define RCC_CFGR2_ADCPRE34 RCC_CFGR2_ADCPRE34_Msk /*!< ADCPRE34[13:5] bits */
11276 #define RCC_CFGR2_ADCPRE34_0 (0x01U << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00000200 */
11277 #define RCC_CFGR2_ADCPRE34_1 (0x02U << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00000400 */
11278 #define RCC_CFGR2_ADCPRE34_2 (0x04U << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00000800 */
11279 #define RCC_CFGR2_ADCPRE34_3 (0x08U << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00001000 */
11280 #define RCC_CFGR2_ADCPRE34_4 (0x10U << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00002000 */
11281
11282 #define RCC_CFGR2_ADCPRE34_NO (0x00000000U) /*!< ADC34 clock disabled, ADC34 can use AHB clock */
11283 #define RCC_CFGR2_ADCPRE34_DIV1 (0x00002000U) /*!< ADC34 PLL clock divided by 1 */
11284 #define RCC_CFGR2_ADCPRE34_DIV2 (0x00002200U) /*!< ADC34 PLL clock divided by 2 */
11285 #define RCC_CFGR2_ADCPRE34_DIV4 (0x00002400U) /*!< ADC34 PLL clock divided by 4 */
11286 #define RCC_CFGR2_ADCPRE34_DIV6 (0x00002600U) /*!< ADC34 PLL clock divided by 6 */
11287 #define RCC_CFGR2_ADCPRE34_DIV8 (0x00002800U) /*!< ADC34 PLL clock divided by 8 */
11288 #define RCC_CFGR2_ADCPRE34_DIV10 (0x00002A00U) /*!< ADC34 PLL clock divided by 10 */
11289 #define RCC_CFGR2_ADCPRE34_DIV12 (0x00002C00U) /*!< ADC34 PLL clock divided by 12 */
11290 #define RCC_CFGR2_ADCPRE34_DIV16 (0x00002E00U) /*!< ADC34 PLL clock divided by 16 */
11291 #define RCC_CFGR2_ADCPRE34_DIV32 (0x00003000U) /*!< ADC34 PLL clock divided by 32 */
11292 #define RCC_CFGR2_ADCPRE34_DIV64 (0x00003200U) /*!< ADC34 PLL clock divided by 64 */
11293 #define RCC_CFGR2_ADCPRE34_DIV128 (0x00003400U) /*!< ADC34 PLL clock divided by 128 */
11294 #define RCC_CFGR2_ADCPRE34_DIV256 (0x00003600U) /*!< ADC34 PLL clock divided by 256 */
11295
11296 /******************* Bit definition for RCC_CFGR3 register ******************/
11297 #define RCC_CFGR3_USART1SW_Pos (0U)
11298 #define RCC_CFGR3_USART1SW_Msk (0x3U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */
11299 #define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk /*!< USART1SW[1:0] bits */
11300 #define RCC_CFGR3_USART1SW_0 (0x1U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */
11301 #define RCC_CFGR3_USART1SW_1 (0x2U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */
11302
11303 #define RCC_CFGR3_USART1SW_PCLK2 (0x00000000U) /*!< PCLK2 clock used as USART1 clock source */
11304 #define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U) /*!< System clock selected as USART1 clock source */
11305 #define RCC_CFGR3_USART1SW_LSE (0x00000002U) /*!< LSE oscillator clock used as USART1 clock source */
11306 #define RCC_CFGR3_USART1SW_HSI (0x00000003U) /*!< HSI oscillator clock used as USART1 clock source */
11307 /* Legacy defines */
11308 #define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK2
11309
11310 #define RCC_CFGR3_I2CSW_Pos (4U)
11311 #define RCC_CFGR3_I2CSW_Msk (0x7U << RCC_CFGR3_I2CSW_Pos) /*!< 0x00000070 */
11312 #define RCC_CFGR3_I2CSW RCC_CFGR3_I2CSW_Msk /*!< I2CSW bits */
11313 #define RCC_CFGR3_I2C1SW_Pos (4U)
11314 #define RCC_CFGR3_I2C1SW_Msk (0x1U << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */
11315 #define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk /*!< I2C1SW bits */
11316 #define RCC_CFGR3_I2C2SW_Pos (5U)
11317 #define RCC_CFGR3_I2C2SW_Msk (0x1U << RCC_CFGR3_I2C2SW_Pos) /*!< 0x00000020 */
11318 #define RCC_CFGR3_I2C2SW RCC_CFGR3_I2C2SW_Msk /*!< I2C2SW bits */
11319 #define RCC_CFGR3_I2C3SW_Pos (6U)
11320 #define RCC_CFGR3_I2C3SW_Msk (0x1U << RCC_CFGR3_I2C3SW_Pos) /*!< 0x00000040 */
11321 #define RCC_CFGR3_I2C3SW RCC_CFGR3_I2C3SW_Msk /*!< I2C3SW bits */
11322
11323 #define RCC_CFGR3_I2C1SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C1 clock source */
11324 #define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U)
11325 #define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1U << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */
11326 #define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk /*!< System clock selected as I2C1 clock source */
11327 #define RCC_CFGR3_I2C2SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C2 clock source */
11328 #define RCC_CFGR3_I2C2SW_SYSCLK_Pos (5U)
11329 #define RCC_CFGR3_I2C2SW_SYSCLK_Msk (0x1U << RCC_CFGR3_I2C2SW_SYSCLK_Pos) /*!< 0x00000020 */
11330 #define RCC_CFGR3_I2C2SW_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK_Msk /*!< System clock selected as I2C2 clock source */
11331 #define RCC_CFGR3_I2C3SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C3 clock source */
11332 #define RCC_CFGR3_I2C3SW_SYSCLK_Pos (6U)
11333 #define RCC_CFGR3_I2C3SW_SYSCLK_Msk (0x1U << RCC_CFGR3_I2C3SW_SYSCLK_Pos) /*!< 0x00000040 */
11334 #define RCC_CFGR3_I2C3SW_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK_Msk /*!< System clock selected as I2C3 clock source */
11335
11336 #define RCC_CFGR3_TIMSW_Pos (8U)
11337 #define RCC_CFGR3_TIMSW_Msk (0xAFU << RCC_CFGR3_TIMSW_Pos) /*!< 0x0000AF00 */
11338 #define RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk /*!< TIMSW bits */
11339 #define RCC_CFGR3_TIM1SW_Pos (8U)
11340 #define RCC_CFGR3_TIM1SW_Msk (0x1U << RCC_CFGR3_TIM1SW_Pos) /*!< 0x00000100 */
11341 #define RCC_CFGR3_TIM1SW RCC_CFGR3_TIM1SW_Msk /*!< TIM1SW bits */
11342 #define RCC_CFGR3_TIM8SW_Pos (9U)
11343 #define RCC_CFGR3_TIM8SW_Msk (0x1U << RCC_CFGR3_TIM8SW_Pos) /*!< 0x00000200 */
11344 #define RCC_CFGR3_TIM8SW RCC_CFGR3_TIM8SW_Msk /*!< TIM8SW bits */
11345 #define RCC_CFGR3_TIM15SW_Pos (10U)
11346 #define RCC_CFGR3_TIM15SW_Msk (0x1U << RCC_CFGR3_TIM15SW_Pos) /*!< 0x00000400 */
11347 #define RCC_CFGR3_TIM15SW RCC_CFGR3_TIM15SW_Msk /*!< TIM15SW bits */
11348 #define RCC_CFGR3_TIM16SW_Pos (11U)
11349 #define RCC_CFGR3_TIM16SW_Msk (0x1U << RCC_CFGR3_TIM16SW_Pos) /*!< 0x00000800 */
11350 #define RCC_CFGR3_TIM16SW RCC_CFGR3_TIM16SW_Msk /*!< TIM16SW bits */
11351 #define RCC_CFGR3_TIM17SW_Pos (13U)
11352 #define RCC_CFGR3_TIM17SW_Msk (0x1U << RCC_CFGR3_TIM17SW_Pos) /*!< 0x00002000 */
11353 #define RCC_CFGR3_TIM17SW RCC_CFGR3_TIM17SW_Msk /*!< TIM17SW bits */
11354 #define RCC_CFGR3_TIM20SW_Pos (15U)
11355 #define RCC_CFGR3_TIM20SW_Msk (0x1U << RCC_CFGR3_TIM20SW_Pos) /*!< 0x00008000 */
11356 #define RCC_CFGR3_TIM20SW RCC_CFGR3_TIM20SW_Msk /*!< TIM20SW bits */
11357 #define RCC_CFGR3_TIM2SW_Pos (24U)
11358 #define RCC_CFGR3_TIM2SW_Msk (0x1U << RCC_CFGR3_TIM2SW_Pos) /*!< 0x01000000 */
11359 #define RCC_CFGR3_TIM2SW RCC_CFGR3_TIM2SW_Msk /*!< TIM2SW bits */
11360 #define RCC_CFGR3_TIM34SW_Pos (25U)
11361 #define RCC_CFGR3_TIM34SW_Msk (0x1U << RCC_CFGR3_TIM34SW_Pos) /*!< 0x02000000 */
11362 #define RCC_CFGR3_TIM34SW RCC_CFGR3_TIM34SW_Msk /*!< TIM34SW bits */
11363 #define RCC_CFGR3_TIM1SW_PCLK2 (0x00000000U) /*!< PCLK2 used as TIM1 clock source */
11364 #define RCC_CFGR3_TIM1SW_PLL_Pos (8U)
11365 #define RCC_CFGR3_TIM1SW_PLL_Msk (0x1U << RCC_CFGR3_TIM1SW_PLL_Pos) /*!< 0x00000100 */
11366 #define RCC_CFGR3_TIM1SW_PLL RCC_CFGR3_TIM1SW_PLL_Msk /*!< PLL clock used as TIM1 clock source */
11367 #define RCC_CFGR3_TIM8SW_PCLK2 (0x00000000U) /*!< PCLK2 used as TIM8 clock source */
11368 #define RCC_CFGR3_TIM8SW_PLL_Pos (9U)
11369 #define RCC_CFGR3_TIM8SW_PLL_Msk (0x1U << RCC_CFGR3_TIM8SW_PLL_Pos) /*!< 0x00000200 */
11370 #define RCC_CFGR3_TIM8SW_PLL RCC_CFGR3_TIM8SW_PLL_Msk /*!< PLL clock used as TIM8 clock source */
11371 #define RCC_CFGR3_TIM15SW_PCLK2 (0x00000000U) /*!< PCLK2 used as TIM15 clock source */
11372 #define RCC_CFGR3_TIM15SW_PLL_Pos (10U)
11373 #define RCC_CFGR3_TIM15SW_PLL_Msk (0x1U << RCC_CFGR3_TIM15SW_PLL_Pos) /*!< 0x00000400 */
11374 #define RCC_CFGR3_TIM15SW_PLL RCC_CFGR3_TIM15SW_PLL_Msk /*!< PLL clock used as TIM15 clock source */
11375 #define RCC_CFGR3_TIM16SW_PCLK2 (0x00000000U) /*!< PCLK2 used as TIM16 clock source */
11376 #define RCC_CFGR3_TIM16SW_PLL_Pos (11U)
11377 #define RCC_CFGR3_TIM16SW_PLL_Msk (0x1U << RCC_CFGR3_TIM16SW_PLL_Pos) /*!< 0x00000800 */
11378 #define RCC_CFGR3_TIM16SW_PLL RCC_CFGR3_TIM16SW_PLL_Msk /*!< PLL clock used as TIM16 clock source */
11379 #define RCC_CFGR3_TIM17SW_PCLK2 (0x00000000U) /*!< PCLK2 used as TIM17 clock source */
11380 #define RCC_CFGR3_TIM17SW_PLL_Pos (13U)
11381 #define RCC_CFGR3_TIM17SW_PLL_Msk (0x1U << RCC_CFGR3_TIM17SW_PLL_Pos) /*!< 0x00002000 */
11382 #define RCC_CFGR3_TIM17SW_PLL RCC_CFGR3_TIM17SW_PLL_Msk /*!< PLL clock used as TIM17 clock source */
11383 #define RCC_CFGR3_TIM20SW_PCLK2 (0x00000000U) /*!< PCLK2 used as TIM20 clock source */
11384 #define RCC_CFGR3_TIM20SW_PLL_Pos (15U)
11385 #define RCC_CFGR3_TIM20SW_PLL_Msk (0x1U << RCC_CFGR3_TIM20SW_PLL_Pos) /*!< 0x00008000 */
11386 #define RCC_CFGR3_TIM20SW_PLL RCC_CFGR3_TIM20SW_PLL_Msk /*!< PLL clock used as TIM20 clock source */
11387
11388 #define RCC_CFGR3_USART2SW_Pos (16U)
11389 #define RCC_CFGR3_USART2SW_Msk (0x3U << RCC_CFGR3_USART2SW_Pos) /*!< 0x00030000 */
11390 #define RCC_CFGR3_USART2SW RCC_CFGR3_USART2SW_Msk /*!< USART2SW[1:0] bits */
11391 #define RCC_CFGR3_USART2SW_0 (0x1U << RCC_CFGR3_USART2SW_Pos) /*!< 0x00010000 */
11392 #define RCC_CFGR3_USART2SW_1 (0x2U << RCC_CFGR3_USART2SW_Pos) /*!< 0x00020000 */
11393
11394 #define RCC_CFGR3_USART2SW_PCLK (0x00000000U) /*!< PCLK1 clock used as USART2 clock source */
11395 #define RCC_CFGR3_USART2SW_SYSCLK (0x00010000U) /*!< System clock selected as USART2 clock source */
11396 #define RCC_CFGR3_USART2SW_LSE (0x00020000U) /*!< LSE oscillator clock used as USART2 clock source */
11397 #define RCC_CFGR3_USART2SW_HSI (0x00030000U) /*!< HSI oscillator clock used as USART2 clock source */
11398
11399 #define RCC_CFGR3_USART3SW_Pos (18U)
11400 #define RCC_CFGR3_USART3SW_Msk (0x3U << RCC_CFGR3_USART3SW_Pos) /*!< 0x000C0000 */
11401 #define RCC_CFGR3_USART3SW RCC_CFGR3_USART3SW_Msk /*!< USART3SW[1:0] bits */
11402 #define RCC_CFGR3_USART3SW_0 (0x1U << RCC_CFGR3_USART3SW_Pos) /*!< 0x00040000 */
11403 #define RCC_CFGR3_USART3SW_1 (0x2U << RCC_CFGR3_USART3SW_Pos) /*!< 0x00080000 */
11404
11405 #define RCC_CFGR3_USART3SW_PCLK (0x00000000U) /*!< PCLK1 clock used as USART3 clock source */
11406 #define RCC_CFGR3_USART3SW_SYSCLK (0x00040000U) /*!< System clock selected as USART3 clock source */
11407 #define RCC_CFGR3_USART3SW_LSE (0x00080000U) /*!< LSE oscillator clock used as USART3 clock source */
11408 #define RCC_CFGR3_USART3SW_HSI (0x000C0000U) /*!< HSI oscillator clock used as USART3 clock source */
11409
11410 #define RCC_CFGR3_UART4SW_Pos (20U)
11411 #define RCC_CFGR3_UART4SW_Msk (0x3U << RCC_CFGR3_UART4SW_Pos) /*!< 0x00300000 */
11412 #define RCC_CFGR3_UART4SW RCC_CFGR3_UART4SW_Msk /*!< UART4SW[1:0] bits */
11413 #define RCC_CFGR3_UART4SW_0 (0x1U << RCC_CFGR3_UART4SW_Pos) /*!< 0x00100000 */
11414 #define RCC_CFGR3_UART4SW_1 (0x2U << RCC_CFGR3_UART4SW_Pos) /*!< 0x00200000 */
11415
11416 #define RCC_CFGR3_UART4SW_PCLK (0x00000000U) /*!< PCLK1 clock used as UART4 clock source */
11417 #define RCC_CFGR3_UART4SW_SYSCLK (0x00100000U) /*!< System clock selected as UART4 clock source */
11418 #define RCC_CFGR3_UART4SW_LSE (0x00200000U) /*!< LSE oscillator clock used as UART4 clock source */
11419 #define RCC_CFGR3_UART4SW_HSI (0x00300000U) /*!< HSI oscillator clock used as UART4 clock source */
11420
11421 #define RCC_CFGR3_UART5SW_Pos (22U)
11422 #define RCC_CFGR3_UART5SW_Msk (0x3U << RCC_CFGR3_UART5SW_Pos) /*!< 0x00C00000 */
11423 #define RCC_CFGR3_UART5SW RCC_CFGR3_UART5SW_Msk /*!< UART5SW[1:0] bits */
11424 #define RCC_CFGR3_UART5SW_0 (0x1U << RCC_CFGR3_UART5SW_Pos) /*!< 0x00400000 */
11425 #define RCC_CFGR3_UART5SW_1 (0x2U << RCC_CFGR3_UART5SW_Pos) /*!< 0x00800000 */
11426
11427 #define RCC_CFGR3_UART5SW_PCLK (0x00000000U) /*!< PCLK1 clock used as UART5 clock source */
11428 #define RCC_CFGR3_UART5SW_SYSCLK (0x00400000U) /*!< System clock selected as UART5 clock source */
11429 #define RCC_CFGR3_UART5SW_LSE (0x00800000U) /*!< LSE oscillator clock used as UART5 clock source */
11430 #define RCC_CFGR3_UART5SW_HSI (0x00C00000U) /*!< HSI oscillator clock used as UART5 clock source */
11431
11432 #define RCC_CFGR3_TIM2SW_PCLK1 (0x00000000U) /*!< PCLK1 used as TIM2 clock source */
11433 #define RCC_CFGR3_TIM2SW_PLL_Pos (24U)
11434 #define RCC_CFGR3_TIM2SW_PLL_Msk (0x1U << RCC_CFGR3_TIM2SW_PLL_Pos) /*!< 0x01000000 */
11435 #define RCC_CFGR3_TIM2SW_PLL RCC_CFGR3_TIM2SW_PLL_Msk /*!< PLL clock used as TIM2 clock source */
11436
11437 #define RCC_CFGR3_TIM34SW_PCLK1 (0x00000000U) /*!< PCLK1 used as TIM3/TIM4 clock source */
11438 #define RCC_CFGR3_TIM34SW_PLL_Pos (25U)
11439 #define RCC_CFGR3_TIM34SW_PLL_Msk (0x1U << RCC_CFGR3_TIM34SW_PLL_Pos) /*!< 0x02000000 */
11440 #define RCC_CFGR3_TIM34SW_PLL RCC_CFGR3_TIM34SW_PLL_Msk /*!< PLL clock used as TIM3/TIM4 clock source */
11441
11442 /* Legacy defines */
11443 #define RCC_CFGR3_TIM1SW_HCLK RCC_CFGR3_TIM1SW_PCLK2
11444 #define RCC_CFGR3_TIM8SW_HCLK RCC_CFGR3_TIM8SW_PCLK2
11445 #define RCC_CFGR3_TIM15SW_HCLK RCC_CFGR3_TIM15SW_PCLK2
11446 #define RCC_CFGR3_TIM16SW_HCLK RCC_CFGR3_TIM16SW_PCLK2
11447 #define RCC_CFGR3_TIM17SW_HCLK RCC_CFGR3_TIM17SW_PCLK2
11448 #define RCC_CFGR3_TIM20SW_HCLK RCC_CFGR3_TIM20SW_PCLK2
11449 #define RCC_CFGR3_TIM2SW_HCLK RCC_CFGR3_TIM2SW_PCLK1
11450 #define RCC_CFGR3_TIM34SW_HCLK RCC_CFGR3_TIM34SW_PCLK1
11451
11452 /******************************************************************************/
11453 /* */
11454 /* Real-Time Clock (RTC) */
11455 /* */
11456 /******************************************************************************/
11457 /*
11458 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
11459 */
11460 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
11461 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
11462 #define RTC_TAMPER3_SUPPORT /*!< TAMPER 3 feature support */
11463 #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */
11464 #define RTC_WAKEUP_SUPPORT /*!< WAKEUP feature support */
11465
11466 /******************** Bits definition for RTC_TR register *******************/
11467 #define RTC_TR_PM_Pos (22U)
11468 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
11469 #define RTC_TR_PM RTC_TR_PM_Msk
11470 #define RTC_TR_HT_Pos (20U)
11471 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
11472 #define RTC_TR_HT RTC_TR_HT_Msk
11473 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
11474 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
11475 #define RTC_TR_HU_Pos (16U)
11476 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
11477 #define RTC_TR_HU RTC_TR_HU_Msk
11478 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
11479 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
11480 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
11481 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
11482 #define RTC_TR_MNT_Pos (12U)
11483 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
11484 #define RTC_TR_MNT RTC_TR_MNT_Msk
11485 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
11486 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
11487 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
11488 #define RTC_TR_MNU_Pos (8U)
11489 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
11490 #define RTC_TR_MNU RTC_TR_MNU_Msk
11491 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
11492 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
11493 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
11494 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
11495 #define RTC_TR_ST_Pos (4U)
11496 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
11497 #define RTC_TR_ST RTC_TR_ST_Msk
11498 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
11499 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
11500 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
11501 #define RTC_TR_SU_Pos (0U)
11502 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
11503 #define RTC_TR_SU RTC_TR_SU_Msk
11504 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
11505 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
11506 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
11507 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
11508
11509 /******************** Bits definition for RTC_DR register *******************/
11510 #define RTC_DR_YT_Pos (20U)
11511 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
11512 #define RTC_DR_YT RTC_DR_YT_Msk
11513 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
11514 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
11515 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
11516 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
11517 #define RTC_DR_YU_Pos (16U)
11518 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
11519 #define RTC_DR_YU RTC_DR_YU_Msk
11520 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
11521 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
11522 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
11523 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
11524 #define RTC_DR_WDU_Pos (13U)
11525 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
11526 #define RTC_DR_WDU RTC_DR_WDU_Msk
11527 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
11528 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
11529 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
11530 #define RTC_DR_MT_Pos (12U)
11531 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
11532 #define RTC_DR_MT RTC_DR_MT_Msk
11533 #define RTC_DR_MU_Pos (8U)
11534 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
11535 #define RTC_DR_MU RTC_DR_MU_Msk
11536 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
11537 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
11538 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
11539 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
11540 #define RTC_DR_DT_Pos (4U)
11541 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
11542 #define RTC_DR_DT RTC_DR_DT_Msk
11543 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
11544 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
11545 #define RTC_DR_DU_Pos (0U)
11546 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
11547 #define RTC_DR_DU RTC_DR_DU_Msk
11548 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
11549 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
11550 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
11551 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
11552
11553 /******************** Bits definition for RTC_CR register *******************/
11554 #define RTC_CR_COE_Pos (23U)
11555 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
11556 #define RTC_CR_COE RTC_CR_COE_Msk
11557 #define RTC_CR_OSEL_Pos (21U)
11558 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
11559 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
11560 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
11561 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
11562 #define RTC_CR_POL_Pos (20U)
11563 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
11564 #define RTC_CR_POL RTC_CR_POL_Msk
11565 #define RTC_CR_COSEL_Pos (19U)
11566 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
11567 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
11568 #define RTC_CR_BKP_Pos (18U)
11569 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
11570 #define RTC_CR_BKP RTC_CR_BKP_Msk
11571 #define RTC_CR_SUB1H_Pos (17U)
11572 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
11573 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
11574 #define RTC_CR_ADD1H_Pos (16U)
11575 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
11576 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
11577 #define RTC_CR_TSIE_Pos (15U)
11578 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
11579 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
11580 #define RTC_CR_WUTIE_Pos (14U)
11581 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
11582 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
11583 #define RTC_CR_ALRBIE_Pos (13U)
11584 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
11585 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
11586 #define RTC_CR_ALRAIE_Pos (12U)
11587 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
11588 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
11589 #define RTC_CR_TSE_Pos (11U)
11590 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
11591 #define RTC_CR_TSE RTC_CR_TSE_Msk
11592 #define RTC_CR_WUTE_Pos (10U)
11593 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
11594 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
11595 #define RTC_CR_ALRBE_Pos (9U)
11596 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
11597 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
11598 #define RTC_CR_ALRAE_Pos (8U)
11599 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
11600 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
11601 #define RTC_CR_FMT_Pos (6U)
11602 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
11603 #define RTC_CR_FMT RTC_CR_FMT_Msk
11604 #define RTC_CR_BYPSHAD_Pos (5U)
11605 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
11606 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
11607 #define RTC_CR_REFCKON_Pos (4U)
11608 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
11609 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
11610 #define RTC_CR_TSEDGE_Pos (3U)
11611 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
11612 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
11613 #define RTC_CR_WUCKSEL_Pos (0U)
11614 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
11615 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
11616 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
11617 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
11618 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
11619
11620 /* Legacy defines */
11621 #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
11622 #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
11623 #define RTC_CR_BCK RTC_CR_BKP
11624
11625 /******************** Bits definition for RTC_ISR register ******************/
11626 #define RTC_ISR_RECALPF_Pos (16U)
11627 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
11628 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
11629 #define RTC_ISR_TAMP3F_Pos (15U)
11630 #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
11631 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
11632 #define RTC_ISR_TAMP2F_Pos (14U)
11633 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
11634 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
11635 #define RTC_ISR_TAMP1F_Pos (13U)
11636 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
11637 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
11638 #define RTC_ISR_TSOVF_Pos (12U)
11639 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
11640 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
11641 #define RTC_ISR_TSF_Pos (11U)
11642 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
11643 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
11644 #define RTC_ISR_WUTF_Pos (10U)
11645 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
11646 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
11647 #define RTC_ISR_ALRBF_Pos (9U)
11648 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
11649 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
11650 #define RTC_ISR_ALRAF_Pos (8U)
11651 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
11652 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
11653 #define RTC_ISR_INIT_Pos (7U)
11654 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
11655 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
11656 #define RTC_ISR_INITF_Pos (6U)
11657 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
11658 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
11659 #define RTC_ISR_RSF_Pos (5U)
11660 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
11661 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
11662 #define RTC_ISR_INITS_Pos (4U)
11663 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
11664 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
11665 #define RTC_ISR_SHPF_Pos (3U)
11666 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
11667 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
11668 #define RTC_ISR_WUTWF_Pos (2U)
11669 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
11670 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
11671 #define RTC_ISR_ALRBWF_Pos (1U)
11672 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
11673 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
11674 #define RTC_ISR_ALRAWF_Pos (0U)
11675 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
11676 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
11677
11678 /******************** Bits definition for RTC_PRER register *****************/
11679 #define RTC_PRER_PREDIV_A_Pos (16U)
11680 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
11681 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
11682 #define RTC_PRER_PREDIV_S_Pos (0U)
11683 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
11684 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
11685
11686 /******************** Bits definition for RTC_WUTR register *****************/
11687 #define RTC_WUTR_WUT_Pos (0U)
11688 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
11689 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
11690
11691 /******************** Bits definition for RTC_ALRMAR register ***************/
11692 #define RTC_ALRMAR_MSK4_Pos (31U)
11693 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
11694 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
11695 #define RTC_ALRMAR_WDSEL_Pos (30U)
11696 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
11697 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
11698 #define RTC_ALRMAR_DT_Pos (28U)
11699 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
11700 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
11701 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
11702 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
11703 #define RTC_ALRMAR_DU_Pos (24U)
11704 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
11705 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
11706 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
11707 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
11708 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
11709 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
11710 #define RTC_ALRMAR_MSK3_Pos (23U)
11711 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
11712 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
11713 #define RTC_ALRMAR_PM_Pos (22U)
11714 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
11715 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
11716 #define RTC_ALRMAR_HT_Pos (20U)
11717 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
11718 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
11719 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
11720 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
11721 #define RTC_ALRMAR_HU_Pos (16U)
11722 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
11723 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
11724 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
11725 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
11726 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
11727 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
11728 #define RTC_ALRMAR_MSK2_Pos (15U)
11729 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
11730 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
11731 #define RTC_ALRMAR_MNT_Pos (12U)
11732 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
11733 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
11734 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
11735 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
11736 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
11737 #define RTC_ALRMAR_MNU_Pos (8U)
11738 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
11739 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
11740 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
11741 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
11742 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
11743 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
11744 #define RTC_ALRMAR_MSK1_Pos (7U)
11745 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
11746 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
11747 #define RTC_ALRMAR_ST_Pos (4U)
11748 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
11749 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
11750 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
11751 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
11752 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
11753 #define RTC_ALRMAR_SU_Pos (0U)
11754 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
11755 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
11756 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
11757 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
11758 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
11759 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
11760
11761 /******************** Bits definition for RTC_ALRMBR register ***************/
11762 #define RTC_ALRMBR_MSK4_Pos (31U)
11763 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
11764 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
11765 #define RTC_ALRMBR_WDSEL_Pos (30U)
11766 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
11767 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
11768 #define RTC_ALRMBR_DT_Pos (28U)
11769 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
11770 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
11771 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
11772 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
11773 #define RTC_ALRMBR_DU_Pos (24U)
11774 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
11775 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
11776 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
11777 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
11778 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
11779 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
11780 #define RTC_ALRMBR_MSK3_Pos (23U)
11781 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
11782 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
11783 #define RTC_ALRMBR_PM_Pos (22U)
11784 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
11785 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
11786 #define RTC_ALRMBR_HT_Pos (20U)
11787 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
11788 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
11789 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
11790 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
11791 #define RTC_ALRMBR_HU_Pos (16U)
11792 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
11793 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
11794 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
11795 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
11796 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
11797 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
11798 #define RTC_ALRMBR_MSK2_Pos (15U)
11799 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
11800 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
11801 #define RTC_ALRMBR_MNT_Pos (12U)
11802 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
11803 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
11804 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
11805 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
11806 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
11807 #define RTC_ALRMBR_MNU_Pos (8U)
11808 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
11809 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
11810 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
11811 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
11812 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
11813 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
11814 #define RTC_ALRMBR_MSK1_Pos (7U)
11815 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
11816 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
11817 #define RTC_ALRMBR_ST_Pos (4U)
11818 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
11819 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
11820 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
11821 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
11822 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
11823 #define RTC_ALRMBR_SU_Pos (0U)
11824 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
11825 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
11826 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
11827 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
11828 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
11829 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
11830
11831 /******************** Bits definition for RTC_WPR register ******************/
11832 #define RTC_WPR_KEY_Pos (0U)
11833 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
11834 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
11835
11836 /******************** Bits definition for RTC_SSR register ******************/
11837 #define RTC_SSR_SS_Pos (0U)
11838 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
11839 #define RTC_SSR_SS RTC_SSR_SS_Msk
11840
11841 /******************** Bits definition for RTC_SHIFTR register ***************/
11842 #define RTC_SHIFTR_SUBFS_Pos (0U)
11843 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
11844 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
11845 #define RTC_SHIFTR_ADD1S_Pos (31U)
11846 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
11847 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
11848
11849 /******************** Bits definition for RTC_TSTR register *****************/
11850 #define RTC_TSTR_PM_Pos (22U)
11851 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
11852 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
11853 #define RTC_TSTR_HT_Pos (20U)
11854 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
11855 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
11856 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
11857 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
11858 #define RTC_TSTR_HU_Pos (16U)
11859 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
11860 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
11861 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
11862 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
11863 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
11864 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
11865 #define RTC_TSTR_MNT_Pos (12U)
11866 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
11867 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
11868 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
11869 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
11870 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
11871 #define RTC_TSTR_MNU_Pos (8U)
11872 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
11873 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
11874 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
11875 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
11876 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
11877 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
11878 #define RTC_TSTR_ST_Pos (4U)
11879 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
11880 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
11881 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
11882 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
11883 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
11884 #define RTC_TSTR_SU_Pos (0U)
11885 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
11886 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
11887 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
11888 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
11889 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
11890 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
11891
11892 /******************** Bits definition for RTC_TSDR register *****************/
11893 #define RTC_TSDR_WDU_Pos (13U)
11894 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
11895 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
11896 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
11897 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
11898 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
11899 #define RTC_TSDR_MT_Pos (12U)
11900 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
11901 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
11902 #define RTC_TSDR_MU_Pos (8U)
11903 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
11904 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
11905 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
11906 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
11907 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
11908 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
11909 #define RTC_TSDR_DT_Pos (4U)
11910 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
11911 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
11912 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
11913 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
11914 #define RTC_TSDR_DU_Pos (0U)
11915 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
11916 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
11917 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
11918 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
11919 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
11920 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
11921
11922 /******************** Bits definition for RTC_TSSSR register ****************/
11923 #define RTC_TSSSR_SS_Pos (0U)
11924 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
11925 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
11926
11927 /******************** Bits definition for RTC_CAL register *****************/
11928 #define RTC_CALR_CALP_Pos (15U)
11929 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
11930 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
11931 #define RTC_CALR_CALW8_Pos (14U)
11932 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
11933 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
11934 #define RTC_CALR_CALW16_Pos (13U)
11935 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
11936 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
11937 #define RTC_CALR_CALM_Pos (0U)
11938 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
11939 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
11940 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
11941 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
11942 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
11943 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
11944 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
11945 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
11946 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
11947 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
11948 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
11949
11950 /******************** Bits definition for RTC_TAFCR register ****************/
11951 #define RTC_TAFCR_PC15MODE_Pos (23U)
11952 #define RTC_TAFCR_PC15MODE_Msk (0x1U << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */
11953 #define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk
11954 #define RTC_TAFCR_PC15VALUE_Pos (22U)
11955 #define RTC_TAFCR_PC15VALUE_Msk (0x1U << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */
11956 #define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk
11957 #define RTC_TAFCR_PC14MODE_Pos (21U)
11958 #define RTC_TAFCR_PC14MODE_Msk (0x1U << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */
11959 #define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk
11960 #define RTC_TAFCR_PC14VALUE_Pos (20U)
11961 #define RTC_TAFCR_PC14VALUE_Msk (0x1U << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */
11962 #define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk
11963 #define RTC_TAFCR_PC13MODE_Pos (19U)
11964 #define RTC_TAFCR_PC13MODE_Msk (0x1U << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */
11965 #define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk
11966 #define RTC_TAFCR_PC13VALUE_Pos (18U)
11967 #define RTC_TAFCR_PC13VALUE_Msk (0x1U << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */
11968 #define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk
11969 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
11970 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
11971 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
11972 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
11973 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
11974 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
11975 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
11976 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
11977 #define RTC_TAFCR_TAMPFLT_Pos (11U)
11978 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
11979 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
11980 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
11981 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
11982 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
11983 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
11984 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
11985 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
11986 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
11987 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
11988 #define RTC_TAFCR_TAMPTS_Pos (7U)
11989 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
11990 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
11991 #define RTC_TAFCR_TAMP3TRG_Pos (6U)
11992 #define RTC_TAFCR_TAMP3TRG_Msk (0x1U << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */
11993 #define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk
11994 #define RTC_TAFCR_TAMP3E_Pos (5U)
11995 #define RTC_TAFCR_TAMP3E_Msk (0x1U << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */
11996 #define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk
11997 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
11998 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
11999 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
12000 #define RTC_TAFCR_TAMP2E_Pos (3U)
12001 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
12002 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
12003 #define RTC_TAFCR_TAMPIE_Pos (2U)
12004 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
12005 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
12006 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
12007 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
12008 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
12009 #define RTC_TAFCR_TAMP1E_Pos (0U)
12010 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
12011 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
12012
12013 /* Reference defines */
12014 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE
12015
12016 /******************** Bits definition for RTC_ALRMASSR register *************/
12017 #define RTC_ALRMASSR_MASKSS_Pos (24U)
12018 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
12019 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
12020 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
12021 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
12022 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
12023 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
12024 #define RTC_ALRMASSR_SS_Pos (0U)
12025 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
12026 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
12027
12028 /******************** Bits definition for RTC_ALRMBSSR register *************/
12029 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
12030 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
12031 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
12032 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
12033 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
12034 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
12035 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
12036 #define RTC_ALRMBSSR_SS_Pos (0U)
12037 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
12038 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
12039
12040 /******************** Bits definition for RTC_BKP0R register ****************/
12041 #define RTC_BKP0R_Pos (0U)
12042 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
12043 #define RTC_BKP0R RTC_BKP0R_Msk
12044
12045 /******************** Bits definition for RTC_BKP1R register ****************/
12046 #define RTC_BKP1R_Pos (0U)
12047 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
12048 #define RTC_BKP1R RTC_BKP1R_Msk
12049
12050 /******************** Bits definition for RTC_BKP2R register ****************/
12051 #define RTC_BKP2R_Pos (0U)
12052 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
12053 #define RTC_BKP2R RTC_BKP2R_Msk
12054
12055 /******************** Bits definition for RTC_BKP3R register ****************/
12056 #define RTC_BKP3R_Pos (0U)
12057 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
12058 #define RTC_BKP3R RTC_BKP3R_Msk
12059
12060 /******************** Bits definition for RTC_BKP4R register ****************/
12061 #define RTC_BKP4R_Pos (0U)
12062 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
12063 #define RTC_BKP4R RTC_BKP4R_Msk
12064
12065 /******************** Bits definition for RTC_BKP5R register ****************/
12066 #define RTC_BKP5R_Pos (0U)
12067 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
12068 #define RTC_BKP5R RTC_BKP5R_Msk
12069
12070 /******************** Bits definition for RTC_BKP6R register ****************/
12071 #define RTC_BKP6R_Pos (0U)
12072 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
12073 #define RTC_BKP6R RTC_BKP6R_Msk
12074
12075 /******************** Bits definition for RTC_BKP7R register ****************/
12076 #define RTC_BKP7R_Pos (0U)
12077 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
12078 #define RTC_BKP7R RTC_BKP7R_Msk
12079
12080 /******************** Bits definition for RTC_BKP8R register ****************/
12081 #define RTC_BKP8R_Pos (0U)
12082 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
12083 #define RTC_BKP8R RTC_BKP8R_Msk
12084
12085 /******************** Bits definition for RTC_BKP9R register ****************/
12086 #define RTC_BKP9R_Pos (0U)
12087 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
12088 #define RTC_BKP9R RTC_BKP9R_Msk
12089
12090 /******************** Bits definition for RTC_BKP10R register ***************/
12091 #define RTC_BKP10R_Pos (0U)
12092 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
12093 #define RTC_BKP10R RTC_BKP10R_Msk
12094
12095 /******************** Bits definition for RTC_BKP11R register ***************/
12096 #define RTC_BKP11R_Pos (0U)
12097 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
12098 #define RTC_BKP11R RTC_BKP11R_Msk
12099
12100 /******************** Bits definition for RTC_BKP12R register ***************/
12101 #define RTC_BKP12R_Pos (0U)
12102 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
12103 #define RTC_BKP12R RTC_BKP12R_Msk
12104
12105 /******************** Bits definition for RTC_BKP13R register ***************/
12106 #define RTC_BKP13R_Pos (0U)
12107 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
12108 #define RTC_BKP13R RTC_BKP13R_Msk
12109
12110 /******************** Bits definition for RTC_BKP14R register ***************/
12111 #define RTC_BKP14R_Pos (0U)
12112 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
12113 #define RTC_BKP14R RTC_BKP14R_Msk
12114
12115 /******************** Bits definition for RTC_BKP15R register ***************/
12116 #define RTC_BKP15R_Pos (0U)
12117 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
12118 #define RTC_BKP15R RTC_BKP15R_Msk
12119
12120 /******************** Number of backup registers ******************************/
12121 #define RTC_BKP_NUMBER 16
12122
12123 /******************************************************************************/
12124 /* */
12125 /* Serial Peripheral Interface (SPI) */
12126 /* */
12127 /******************************************************************************/
12128
12129 /*
12130 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
12131 */
12132 #define SPI_I2S_SUPPORT /*!< I2S support */
12133 #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
12134
12135 /******************* Bit definition for SPI_CR1 register ********************/
12136 #define SPI_CR1_CPHA_Pos (0U)
12137 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
12138 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
12139 #define SPI_CR1_CPOL_Pos (1U)
12140 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
12141 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
12142 #define SPI_CR1_MSTR_Pos (2U)
12143 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
12144 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
12145 #define SPI_CR1_BR_Pos (3U)
12146 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
12147 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
12148 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
12149 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
12150 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
12151 #define SPI_CR1_SPE_Pos (6U)
12152 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
12153 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
12154 #define SPI_CR1_LSBFIRST_Pos (7U)
12155 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
12156 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
12157 #define SPI_CR1_SSI_Pos (8U)
12158 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
12159 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
12160 #define SPI_CR1_SSM_Pos (9U)
12161 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
12162 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
12163 #define SPI_CR1_RXONLY_Pos (10U)
12164 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
12165 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
12166 #define SPI_CR1_CRCL_Pos (11U)
12167 #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
12168 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
12169 #define SPI_CR1_CRCNEXT_Pos (12U)
12170 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
12171 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
12172 #define SPI_CR1_CRCEN_Pos (13U)
12173 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
12174 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
12175 #define SPI_CR1_BIDIOE_Pos (14U)
12176 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
12177 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
12178 #define SPI_CR1_BIDIMODE_Pos (15U)
12179 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
12180 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
12181
12182 /******************* Bit definition for SPI_CR2 register ********************/
12183 #define SPI_CR2_RXDMAEN_Pos (0U)
12184 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
12185 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
12186 #define SPI_CR2_TXDMAEN_Pos (1U)
12187 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
12188 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
12189 #define SPI_CR2_SSOE_Pos (2U)
12190 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
12191 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
12192 #define SPI_CR2_NSSP_Pos (3U)
12193 #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
12194 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
12195 #define SPI_CR2_FRF_Pos (4U)
12196 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
12197 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
12198 #define SPI_CR2_ERRIE_Pos (5U)
12199 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
12200 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
12201 #define SPI_CR2_RXNEIE_Pos (6U)
12202 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
12203 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
12204 #define SPI_CR2_TXEIE_Pos (7U)
12205 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
12206 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
12207 #define SPI_CR2_DS_Pos (8U)
12208 #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
12209 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
12210 #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
12211 #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
12212 #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
12213 #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
12214 #define SPI_CR2_FRXTH_Pos (12U)
12215 #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
12216 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
12217 #define SPI_CR2_LDMARX_Pos (13U)
12218 #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
12219 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
12220 #define SPI_CR2_LDMATX_Pos (14U)
12221 #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
12222 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
12223
12224 /******************** Bit definition for SPI_SR register ********************/
12225 #define SPI_SR_RXNE_Pos (0U)
12226 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
12227 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
12228 #define SPI_SR_TXE_Pos (1U)
12229 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
12230 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
12231 #define SPI_SR_CHSIDE_Pos (2U)
12232 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
12233 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
12234 #define SPI_SR_UDR_Pos (3U)
12235 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
12236 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
12237 #define SPI_SR_CRCERR_Pos (4U)
12238 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
12239 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
12240 #define SPI_SR_MODF_Pos (5U)
12241 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
12242 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
12243 #define SPI_SR_OVR_Pos (6U)
12244 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
12245 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
12246 #define SPI_SR_BSY_Pos (7U)
12247 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
12248 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
12249 #define SPI_SR_FRE_Pos (8U)
12250 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
12251 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
12252 #define SPI_SR_FRLVL_Pos (9U)
12253 #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
12254 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
12255 #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
12256 #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
12257 #define SPI_SR_FTLVL_Pos (11U)
12258 #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
12259 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
12260 #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
12261 #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
12262
12263 /******************** Bit definition for SPI_DR register ********************/
12264 #define SPI_DR_DR_Pos (0U)
12265 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
12266 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
12267
12268 /******************* Bit definition for SPI_CRCPR register ******************/
12269 #define SPI_CRCPR_CRCPOLY_Pos (0U)
12270 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
12271 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
12272
12273 /****************** Bit definition for SPI_RXCRCR register ******************/
12274 #define SPI_RXCRCR_RXCRC_Pos (0U)
12275 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
12276 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
12277
12278 /****************** Bit definition for SPI_TXCRCR register ******************/
12279 #define SPI_TXCRCR_TXCRC_Pos (0U)
12280 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
12281 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
12282
12283 /****************** Bit definition for SPI_I2SCFGR register *****************/
12284 #define SPI_I2SCFGR_CHLEN_Pos (0U)
12285 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
12286 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
12287 #define SPI_I2SCFGR_DATLEN_Pos (1U)
12288 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
12289 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
12290 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
12291 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
12292 #define SPI_I2SCFGR_CKPOL_Pos (3U)
12293 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
12294 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
12295 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
12296 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
12297 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
12298 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
12299 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
12300 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
12301 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
12302 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
12303 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
12304 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
12305 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
12306 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
12307 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
12308 #define SPI_I2SCFGR_I2SE_Pos (10U)
12309 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
12310 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
12311 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
12312 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
12313 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
12314
12315 /****************** Bit definition for SPI_I2SPR register *******************/
12316 #define SPI_I2SPR_I2SDIV_Pos (0U)
12317 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
12318 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
12319 #define SPI_I2SPR_ODD_Pos (8U)
12320 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
12321 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
12322 #define SPI_I2SPR_MCKOE_Pos (9U)
12323 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
12324 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
12325
12326 /******************************************************************************/
12327 /* */
12328 /* System Configuration(SYSCFG) */
12329 /* */
12330 /******************************************************************************/
12331 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
12332 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
12333 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x7U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000007 */
12334 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
12335 #define SYSCFG_CFGR1_MEM_MODE_0 (0x00000001U) /*!< Bit 0 */
12336 #define SYSCFG_CFGR1_MEM_MODE_1 (0x00000002U) /*!< Bit 1 */
12337 #define SYSCFG_CFGR1_MEM_MODE_2 (0x00000004U) /*!< Bit 2 */
12338 #define SYSCFG_CFGR1_USB_IT_RMP_Pos (5U)
12339 #define SYSCFG_CFGR1_USB_IT_RMP_Msk (0x1U << SYSCFG_CFGR1_USB_IT_RMP_Pos) /*!< 0x00000020 */
12340 #define SYSCFG_CFGR1_USB_IT_RMP SYSCFG_CFGR1_USB_IT_RMP_Msk /*!< USB interrupt remap */
12341 #define SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos (6U)
12342 #define SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos) /*!< 0x00000040 */
12343 #define SYSCFG_CFGR1_TIM1_ITR3_RMP SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk /*!< Timer 1 ITR3 selection */
12344 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos (7U)
12345 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk (0x1U << SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos) /*!< 0x00000080 */
12346 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk /*!< DAC1 Trigger1 remap */
12347 #define SYSCFG_CFGR1_DMA_RMP_Pos (8U)
12348 #define SYSCFG_CFGR1_DMA_RMP_Msk (0x79U << SYSCFG_CFGR1_DMA_RMP_Pos) /*!< 0x00007900 */
12349 #define SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk /*!< DMA remap mask */
12350 #define SYSCFG_CFGR1_ADC24_DMA_RMP_Pos (8U)
12351 #define SYSCFG_CFGR1_ADC24_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_ADC24_DMA_RMP_Pos) /*!< 0x00000100 */
12352 #define SYSCFG_CFGR1_ADC24_DMA_RMP SYSCFG_CFGR1_ADC24_DMA_RMP_Msk /*!< ADC2 and ADC4 DMA remap */
12353 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U)
12354 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /*!< 0x00000800 */
12355 #define SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk /*!< Timer 16 DMA remap */
12356 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U)
12357 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /*!< 0x00001000 */
12358 #define SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk /*!< Timer 17 DMA remap */
12359 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos (13U)
12360 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos) /*!< 0x00002000 */
12361 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk /*!< Timer 6 / DAC1 Ch1 DMA remap */
12362 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos (14U)
12363 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos) /*!< 0x00004000 */
12364 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk /*!< Timer 7 / DAC1 Ch2 DMA remap */
12365 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
12366 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
12367 #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
12368 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
12369 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
12370 #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
12371 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
12372 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
12373 #define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
12374 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
12375 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
12376 #define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
12377 #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
12378 #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
12379 #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
12380 #define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
12381 #define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
12382 #define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
12383 #define SYSCFG_CFGR1_ENCODER_MODE_Pos (22U)
12384 #define SYSCFG_CFGR1_ENCODER_MODE_Msk (0x3U << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00C00000 */
12385 #define SYSCFG_CFGR1_ENCODER_MODE SYSCFG_CFGR1_ENCODER_MODE_Msk /*!< Encoder Mode */
12386 #define SYSCFG_CFGR1_ENCODER_MODE_0 (0x1U << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00400000 */
12387 #define SYSCFG_CFGR1_ENCODER_MODE_1 (0x2U << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00800000 */
12388 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos (22U)
12389 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk (0x1U << SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos) /*!< 0x00400000 */
12390 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2 SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
12391 #define SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos (23U)
12392 #define SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk (0x1U << SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos) /*!< 0x00800000 */
12393 #define SYSCFG_CFGR1_ENCODER_MODE_TIM3 SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
12394 #define SYSCFG_CFGR1_I2C3_FMP_Pos (24U)
12395 #define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x01000000 */
12396 #define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
12397 #define SYSCFG_CFGR1_FPU_IE_Pos (26U)
12398 #define SYSCFG_CFGR1_FPU_IE_Msk (0x3FU << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0xFC000000 */
12399 #define SYSCFG_CFGR1_FPU_IE SYSCFG_CFGR1_FPU_IE_Msk /*!< Floating Point Unit Interrupt Enable */
12400 #define SYSCFG_CFGR1_FPU_IE_0 (0x01U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x04000000 */
12401 #define SYSCFG_CFGR1_FPU_IE_1 (0x02U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x08000000 */
12402 #define SYSCFG_CFGR1_FPU_IE_2 (0x04U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x10000000 */
12403 #define SYSCFG_CFGR1_FPU_IE_3 (0x08U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x20000000 */
12404 #define SYSCFG_CFGR1_FPU_IE_4 (0x10U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x40000000 */
12405 #define SYSCFG_CFGR1_FPU_IE_5 (0x20U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x80000000 */
12406
12407 /***************** Bit definition for SYSCFG_RCR register *******************/
12408 #define SYSCFG_RCR_PAGE0_Pos (0U)
12409 #define SYSCFG_RCR_PAGE0_Msk (0x1U << SYSCFG_RCR_PAGE0_Pos) /*!< 0x00000001 */
12410 #define SYSCFG_RCR_PAGE0 SYSCFG_RCR_PAGE0_Msk /*!< ICODE SRAM Write protection page 0 */
12411 #define SYSCFG_RCR_PAGE1_Pos (1U)
12412 #define SYSCFG_RCR_PAGE1_Msk (0x1U << SYSCFG_RCR_PAGE1_Pos) /*!< 0x00000002 */
12413 #define SYSCFG_RCR_PAGE1 SYSCFG_RCR_PAGE1_Msk /*!< ICODE SRAM Write protection page 1 */
12414 #define SYSCFG_RCR_PAGE2_Pos (2U)
12415 #define SYSCFG_RCR_PAGE2_Msk (0x1U << SYSCFG_RCR_PAGE2_Pos) /*!< 0x00000004 */
12416 #define SYSCFG_RCR_PAGE2 SYSCFG_RCR_PAGE2_Msk /*!< ICODE SRAM Write protection page 2 */
12417 #define SYSCFG_RCR_PAGE3_Pos (3U)
12418 #define SYSCFG_RCR_PAGE3_Msk (0x1U << SYSCFG_RCR_PAGE3_Pos) /*!< 0x00000008 */
12419 #define SYSCFG_RCR_PAGE3 SYSCFG_RCR_PAGE3_Msk /*!< ICODE SRAM Write protection page 3 */
12420 #define SYSCFG_RCR_PAGE4_Pos (4U)
12421 #define SYSCFG_RCR_PAGE4_Msk (0x1U << SYSCFG_RCR_PAGE4_Pos) /*!< 0x00000010 */
12422 #define SYSCFG_RCR_PAGE4 SYSCFG_RCR_PAGE4_Msk /*!< ICODE SRAM Write protection page 4 */
12423 #define SYSCFG_RCR_PAGE5_Pos (5U)
12424 #define SYSCFG_RCR_PAGE5_Msk (0x1U << SYSCFG_RCR_PAGE5_Pos) /*!< 0x00000020 */
12425 #define SYSCFG_RCR_PAGE5 SYSCFG_RCR_PAGE5_Msk /*!< ICODE SRAM Write protection page 5 */
12426 #define SYSCFG_RCR_PAGE6_Pos (6U)
12427 #define SYSCFG_RCR_PAGE6_Msk (0x1U << SYSCFG_RCR_PAGE6_Pos) /*!< 0x00000040 */
12428 #define SYSCFG_RCR_PAGE6 SYSCFG_RCR_PAGE6_Msk /*!< ICODE SRAM Write protection page 6 */
12429 #define SYSCFG_RCR_PAGE7_Pos (7U)
12430 #define SYSCFG_RCR_PAGE7_Msk (0x1U << SYSCFG_RCR_PAGE7_Pos) /*!< 0x00000080 */
12431 #define SYSCFG_RCR_PAGE7 SYSCFG_RCR_PAGE7_Msk /*!< ICODE SRAM Write protection page 7 */
12432 #define SYSCFG_RCR_PAGE8_Pos (8U)
12433 #define SYSCFG_RCR_PAGE8_Msk (0x1U << SYSCFG_RCR_PAGE8_Pos) /*!< 0x00000100 */
12434 #define SYSCFG_RCR_PAGE8 SYSCFG_RCR_PAGE8_Msk /*!< ICODE SRAM Write protection page 8 */
12435 #define SYSCFG_RCR_PAGE9_Pos (9U)
12436 #define SYSCFG_RCR_PAGE9_Msk (0x1U << SYSCFG_RCR_PAGE9_Pos) /*!< 0x00000200 */
12437 #define SYSCFG_RCR_PAGE9 SYSCFG_RCR_PAGE9_Msk /*!< ICODE SRAM Write protection page 9 */
12438 #define SYSCFG_RCR_PAGE10_Pos (10U)
12439 #define SYSCFG_RCR_PAGE10_Msk (0x1U << SYSCFG_RCR_PAGE10_Pos) /*!< 0x00000400 */
12440 #define SYSCFG_RCR_PAGE10 SYSCFG_RCR_PAGE10_Msk /*!< ICODE SRAM Write protection page 10 */
12441 #define SYSCFG_RCR_PAGE11_Pos (11U)
12442 #define SYSCFG_RCR_PAGE11_Msk (0x1U << SYSCFG_RCR_PAGE11_Pos) /*!< 0x00000800 */
12443 #define SYSCFG_RCR_PAGE11 SYSCFG_RCR_PAGE11_Msk /*!< ICODE SRAM Write protection page 11 */
12444 #define SYSCFG_RCR_PAGE12_Pos (12U)
12445 #define SYSCFG_RCR_PAGE12_Msk (0x1U << SYSCFG_RCR_PAGE12_Pos) /*!< 0x00001000 */
12446 #define SYSCFG_RCR_PAGE12 SYSCFG_RCR_PAGE12_Msk /*!< ICODE SRAM Write protection page 12 */
12447 #define SYSCFG_RCR_PAGE13_Pos (13U)
12448 #define SYSCFG_RCR_PAGE13_Msk (0x1U << SYSCFG_RCR_PAGE13_Pos) /*!< 0x00002000 */
12449 #define SYSCFG_RCR_PAGE13 SYSCFG_RCR_PAGE13_Msk /*!< ICODE SRAM Write protection page 13 */
12450 #define SYSCFG_RCR_PAGE14_Pos (14U)
12451 #define SYSCFG_RCR_PAGE14_Msk (0x1U << SYSCFG_RCR_PAGE14_Pos) /*!< 0x00004000 */
12452 #define SYSCFG_RCR_PAGE14 SYSCFG_RCR_PAGE14_Msk /*!< ICODE SRAM Write protection page 14 */
12453 #define SYSCFG_RCR_PAGE15_Pos (15U)
12454 #define SYSCFG_RCR_PAGE15_Msk (0x1U << SYSCFG_RCR_PAGE15_Pos) /*!< 0x00008000 */
12455 #define SYSCFG_RCR_PAGE15 SYSCFG_RCR_PAGE15_Msk /*!< ICODE SRAM Write protection page 15 */
12456
12457 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
12458 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
12459 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
12460 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
12461 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
12462 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
12463 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
12464 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
12465 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
12466 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
12467 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
12468 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
12469 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
12470
12471 /*!<*
12472 * @brief EXTI0 configuration
12473 */
12474 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
12475 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
12476 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
12477 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
12478 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */
12479 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!< PF[0] pin */
12480 #define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!< PG[0] pin */
12481 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!< PH[0] pin */
12482
12483 /*!<*
12484 * @brief EXTI1 configuration
12485 */
12486 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
12487 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
12488 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
12489 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
12490 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */
12491 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!< PF[1] pin */
12492 #define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!< PG[1] pin */
12493 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!< PH[1] pin */
12494
12495 /*!<*
12496 * @brief EXTI2 configuration
12497 */
12498 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
12499 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
12500 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
12501 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
12502 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */
12503 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!< PF[2] pin */
12504 #define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!< PG[2] pin */
12505
12506 /*!<*
12507 * @brief EXTI3 configuration
12508 */
12509 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
12510 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
12511 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
12512 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
12513 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
12514 #define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!< PE[3] pin */
12515 #define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!< PG[3] pin */
12516
12517 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
12518 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
12519 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
12520 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
12521 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
12522 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
12523 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
12524 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
12525 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
12526 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
12527 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
12528 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
12529 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
12530
12531 /*!<*
12532 * @brief EXTI4 configuration
12533 */
12534 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
12535 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
12536 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
12537 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
12538 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */
12539 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!< PF[4] pin */
12540 #define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!< PG[4] pin */
12541 #define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!< PH[4] pin */
12542
12543 /*!<*
12544 * @brief EXTI5 configuration
12545 */
12546 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
12547 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
12548 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
12549 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
12550 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */
12551 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!< PF[5] pin */
12552 #define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!< PG[5] pin */
12553
12554 /*!<*
12555 * @brief EXTI6 configuration
12556 */
12557 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
12558 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
12559 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
12560 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
12561 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */
12562 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!< PF[6] pin */
12563 #define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!< PG[6] pin */
12564
12565 /*!<*
12566 * @brief EXTI7 configuration
12567 */
12568 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
12569 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
12570 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
12571 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
12572 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */
12573 #define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!< PF[7] pin */
12574 #define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!< PG[7] pin */
12575
12576 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
12577 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
12578 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
12579 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
12580 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
12581 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
12582 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
12583 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
12584 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
12585 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
12586 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
12587 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
12588 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
12589
12590 /*!<*
12591 * @brief EXTI8 configuration
12592 */
12593 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
12594 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
12595 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
12596 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
12597 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */
12598 #define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!< PF[8] pin */
12599 #define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!< PG[8] pin */
12600
12601 /*!<*
12602 * @brief EXTI9 configuration
12603 */
12604 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
12605 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
12606 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
12607 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
12608 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */
12609 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!< PF[9] pin */
12610 #define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!< PG[9] pin */
12611
12612 /*!<*
12613 * @brief EXTI10 configuration
12614 */
12615 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
12616 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
12617 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
12618 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
12619 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */
12620 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!< PF[10] pin */
12621 #define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!< PG[10] pin */
12622
12623 /*!<*
12624 * @brief EXTI11 configuration
12625 */
12626 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
12627 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
12628 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
12629 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
12630 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */
12631 #define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!< PF[11] pin */
12632 #define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!< PG[11] pin */
12633
12634 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
12635 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
12636 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
12637 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
12638 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
12639 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
12640 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
12641 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
12642 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
12643 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
12644 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
12645 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
12646 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
12647
12648 /*!<*
12649 * @brief EXTI12 configuration
12650 */
12651 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
12652 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
12653 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
12654 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
12655 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */
12656 #define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!< PF[12] pin */
12657 #define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!< PG[12] pin */
12658
12659 /*!<*
12660 * @brief EXTI13 configuration
12661 */
12662 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
12663 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
12664 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
12665 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
12666 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */
12667 #define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!< PF[13] pin */
12668 #define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!< PG[13] pin */
12669
12670 /*!<*
12671 * @brief EXTI14 configuration
12672 */
12673 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
12674 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
12675 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
12676 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
12677 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */
12678 #define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!< PF[14] pin */
12679 #define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!< PG[14] pin */
12680
12681 /*!<*
12682 * @brief EXTI15 configuration
12683 */
12684 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
12685 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
12686 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
12687 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
12688 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
12689 #define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!< PF[15] pin */
12690 #define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!< PG[15] pin */
12691
12692 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
12693 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
12694 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
12695 #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
12696 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U)
12697 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1U << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */
12698 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
12699 #define SYSCFG_CFGR2_PVD_LOCK_Pos (2U)
12700 #define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1U << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
12701 #define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
12702 #define SYSCFG_CFGR2_BYP_ADDR_PAR_Pos (4U)
12703 #define SYSCFG_CFGR2_BYP_ADDR_PAR_Msk (0x1U << SYSCFG_CFGR2_BYP_ADDR_PAR_Pos) /*!< 0x00000010 */
12704 #define SYSCFG_CFGR2_BYP_ADDR_PAR SYSCFG_CFGR2_BYP_ADDR_PAR_Msk /*!< Disables the adddress parity check on RAM */
12705 #define SYSCFG_CFGR2_SRAM_PE_Pos (8U)
12706 #define SYSCFG_CFGR2_SRAM_PE_Msk (0x1U << SYSCFG_CFGR2_SRAM_PE_Pos) /*!< 0x00000100 */
12707 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PE_Msk /*!< SRAM Parity error flag */
12708 /***************** Bit definition for SYSCFG_CFGR4 register *****************/
12709 #define SYSCFG_CFGR4_ADC12_EXT2_RMP_Pos (0U)
12710 #define SYSCFG_CFGR4_ADC12_EXT2_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC12_EXT2_RMP_Pos) /*!< 0x00000001 */
12711 #define SYSCFG_CFGR4_ADC12_EXT2_RMP SYSCFG_CFGR4_ADC12_EXT2_RMP_Msk /*!< ADC12 regular channel EXT2 remap */
12712 #define SYSCFG_CFGR4_ADC12_EXT3_RMP_Pos (1U)
12713 #define SYSCFG_CFGR4_ADC12_EXT3_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC12_EXT3_RMP_Pos) /*!< 0x00000002 */
12714 #define SYSCFG_CFGR4_ADC12_EXT3_RMP SYSCFG_CFGR4_ADC12_EXT3_RMP_Msk /*!< ADC12 regular channel EXT3 remap */
12715 #define SYSCFG_CFGR4_ADC12_EXT5_RMP_Pos (2U)
12716 #define SYSCFG_CFGR4_ADC12_EXT5_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC12_EXT5_RMP_Pos) /*!< 0x00000004 */
12717 #define SYSCFG_CFGR4_ADC12_EXT5_RMP SYSCFG_CFGR4_ADC12_EXT5_RMP_Msk /*!< ADC12 regular channel EXT5 remap */
12718 #define SYSCFG_CFGR4_ADC12_EXT13_RMP_Pos (3U)
12719 #define SYSCFG_CFGR4_ADC12_EXT13_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC12_EXT13_RMP_Pos) /*!< 0x00000008 */
12720 #define SYSCFG_CFGR4_ADC12_EXT13_RMP SYSCFG_CFGR4_ADC12_EXT13_RMP_Msk /*!< ADC12 regular channel EXT13 remap */
12721 #define SYSCFG_CFGR4_ADC12_EXT15_RMP_Pos (4U)
12722 #define SYSCFG_CFGR4_ADC12_EXT15_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC12_EXT15_RMP_Pos) /*!< 0x00000010 */
12723 #define SYSCFG_CFGR4_ADC12_EXT15_RMP SYSCFG_CFGR4_ADC12_EXT15_RMP_Msk /*!< ADC12 regular channel EXT15 remap */
12724 #define SYSCFG_CFGR4_ADC12_JEXT3_RMP_Pos (5U)
12725 #define SYSCFG_CFGR4_ADC12_JEXT3_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC12_JEXT3_RMP_Pos) /*!< 0x00000020 */
12726 #define SYSCFG_CFGR4_ADC12_JEXT3_RMP SYSCFG_CFGR4_ADC12_JEXT3_RMP_Msk /*!< ADC12 injected channel JEXT3 remap */
12727 #define SYSCFG_CFGR4_ADC12_JEXT6_RMP_Pos (6U)
12728 #define SYSCFG_CFGR4_ADC12_JEXT6_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC12_JEXT6_RMP_Pos) /*!< 0x00000040 */
12729 #define SYSCFG_CFGR4_ADC12_JEXT6_RMP SYSCFG_CFGR4_ADC12_JEXT6_RMP_Msk /*!< ADC12 injected channel JEXT6 remap */
12730 #define SYSCFG_CFGR4_ADC12_JEXT13_RMP_Pos (7U)
12731 #define SYSCFG_CFGR4_ADC12_JEXT13_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC12_JEXT13_RMP_Pos) /*!< 0x00000080 */
12732 #define SYSCFG_CFGR4_ADC12_JEXT13_RMP SYSCFG_CFGR4_ADC12_JEXT13_RMP_Msk /*!< ADC12 injected channel JEXT13 remap */
12733 #define SYSCFG_CFGR4_ADC34_EXT5_RMP_Pos (8U)
12734 #define SYSCFG_CFGR4_ADC34_EXT5_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC34_EXT5_RMP_Pos) /*!< 0x00000100 */
12735 #define SYSCFG_CFGR4_ADC34_EXT5_RMP SYSCFG_CFGR4_ADC34_EXT5_RMP_Msk /*!< ADC34 regular channel EXT5 remap */
12736 #define SYSCFG_CFGR4_ADC34_EXT6_RMP_Pos (9U)
12737 #define SYSCFG_CFGR4_ADC34_EXT6_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC34_EXT6_RMP_Pos) /*!< 0x00000200 */
12738 #define SYSCFG_CFGR4_ADC34_EXT6_RMP SYSCFG_CFGR4_ADC34_EXT6_RMP_Msk /*!< ADC34 regular channel EXT6 remap */
12739 #define SYSCFG_CFGR4_ADC34_EXT15_RMP_Pos (10U)
12740 #define SYSCFG_CFGR4_ADC34_EXT15_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC34_EXT15_RMP_Pos) /*!< 0x00000400 */
12741 #define SYSCFG_CFGR4_ADC34_EXT15_RMP SYSCFG_CFGR4_ADC34_EXT15_RMP_Msk /*!< ADC34 regular channel EXT15 remap */
12742 #define SYSCFG_CFGR4_ADC34_JEXT5_RMP_Pos (11U)
12743 #define SYSCFG_CFGR4_ADC34_JEXT5_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC34_JEXT5_RMP_Pos) /*!< 0x00000800 */
12744 #define SYSCFG_CFGR4_ADC34_JEXT5_RMP SYSCFG_CFGR4_ADC34_JEXT5_RMP_Msk /*!< ADC34 injected channel JEXT5 remap */
12745 #define SYSCFG_CFGR4_ADC34_JEXT11_RMP_Pos (12U)
12746 #define SYSCFG_CFGR4_ADC34_JEXT11_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC34_JEXT11_RMP_Pos) /*!< 0x00001000 */
12747 #define SYSCFG_CFGR4_ADC34_JEXT11_RMP SYSCFG_CFGR4_ADC34_JEXT11_RMP_Msk /*!< ADC34 injected channel JEXT11 remap */
12748 #define SYSCFG_CFGR4_ADC34_JEXT14_RMP_Pos (13U)
12749 #define SYSCFG_CFGR4_ADC34_JEXT14_RMP_Msk (0x1U << SYSCFG_CFGR4_ADC34_JEXT14_RMP_Pos) /*!< 0x00002000 */
12750 #define SYSCFG_CFGR4_ADC34_JEXT14_RMP SYSCFG_CFGR4_ADC34_JEXT14_RMP_Msk /*!< ADC34 injected channel JEXT14 remap */
12751
12752 /******************************************************************************/
12753 /* */
12754 /* TIM */
12755 /* */
12756 /******************************************************************************/
12757 /******************* Bit definition for TIM_CR1 register ********************/
12758 #define TIM_CR1_CEN_Pos (0U)
12759 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
12760 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
12761 #define TIM_CR1_UDIS_Pos (1U)
12762 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
12763 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
12764 #define TIM_CR1_URS_Pos (2U)
12765 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
12766 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
12767 #define TIM_CR1_OPM_Pos (3U)
12768 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
12769 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
12770 #define TIM_CR1_DIR_Pos (4U)
12771 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
12772 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
12773
12774 #define TIM_CR1_CMS_Pos (5U)
12775 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
12776 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
12777 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
12778 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
12779
12780 #define TIM_CR1_ARPE_Pos (7U)
12781 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
12782 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
12783
12784 #define TIM_CR1_CKD_Pos (8U)
12785 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
12786 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
12787 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
12788 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
12789
12790 #define TIM_CR1_UIFREMAP_Pos (11U)
12791 #define TIM_CR1_UIFREMAP_Msk (0x1U << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
12792 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
12793
12794 /******************* Bit definition for TIM_CR2 register ********************/
12795 #define TIM_CR2_CCPC_Pos (0U)
12796 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
12797 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
12798 #define TIM_CR2_CCUS_Pos (2U)
12799 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
12800 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
12801 #define TIM_CR2_CCDS_Pos (3U)
12802 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
12803 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
12804
12805 #define TIM_CR2_MMS_Pos (4U)
12806 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
12807 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
12808 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
12809 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
12810 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
12811
12812 #define TIM_CR2_TI1S_Pos (7U)
12813 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
12814 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
12815 #define TIM_CR2_OIS1_Pos (8U)
12816 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
12817 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
12818 #define TIM_CR2_OIS1N_Pos (9U)
12819 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
12820 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
12821 #define TIM_CR2_OIS2_Pos (10U)
12822 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
12823 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
12824 #define TIM_CR2_OIS2N_Pos (11U)
12825 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
12826 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
12827 #define TIM_CR2_OIS3_Pos (12U)
12828 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
12829 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
12830 #define TIM_CR2_OIS3N_Pos (13U)
12831 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
12832 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
12833 #define TIM_CR2_OIS4_Pos (14U)
12834 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
12835 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
12836
12837 #define TIM_CR2_OIS5_Pos (16U)
12838 #define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
12839 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
12840 #define TIM_CR2_OIS6_Pos (18U)
12841 #define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
12842 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
12843
12844 #define TIM_CR2_MMS2_Pos (20U)
12845 #define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
12846 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
12847 #define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
12848 #define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
12849 #define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
12850 #define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
12851
12852 /******************* Bit definition for TIM_SMCR register *******************/
12853 #define TIM_SMCR_SMS_Pos (0U)
12854 #define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
12855 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
12856 #define TIM_SMCR_SMS_0 (0x00000001U) /*!<Bit 0 */
12857 #define TIM_SMCR_SMS_1 (0x00000002U) /*!<Bit 1 */
12858 #define TIM_SMCR_SMS_2 (0x00000004U) /*!<Bit 2 */
12859 #define TIM_SMCR_SMS_3 (0x00010000U) /*!<Bit 3 */
12860
12861 #define TIM_SMCR_OCCS_Pos (3U)
12862 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
12863 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
12864
12865 #define TIM_SMCR_TS_Pos (4U)
12866 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
12867 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
12868 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
12869 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
12870 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
12871
12872 #define TIM_SMCR_MSM_Pos (7U)
12873 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
12874 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
12875
12876 #define TIM_SMCR_ETF_Pos (8U)
12877 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
12878 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
12879 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
12880 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
12881 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
12882 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
12883
12884 #define TIM_SMCR_ETPS_Pos (12U)
12885 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
12886 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
12887 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
12888 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
12889
12890 #define TIM_SMCR_ECE_Pos (14U)
12891 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
12892 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
12893 #define TIM_SMCR_ETP_Pos (15U)
12894 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
12895 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
12896
12897 /******************* Bit definition for TIM_DIER register *******************/
12898 #define TIM_DIER_UIE_Pos (0U)
12899 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
12900 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
12901 #define TIM_DIER_CC1IE_Pos (1U)
12902 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
12903 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
12904 #define TIM_DIER_CC2IE_Pos (2U)
12905 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
12906 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
12907 #define TIM_DIER_CC3IE_Pos (3U)
12908 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
12909 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
12910 #define TIM_DIER_CC4IE_Pos (4U)
12911 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
12912 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
12913 #define TIM_DIER_COMIE_Pos (5U)
12914 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
12915 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
12916 #define TIM_DIER_TIE_Pos (6U)
12917 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
12918 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
12919 #define TIM_DIER_BIE_Pos (7U)
12920 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
12921 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
12922 #define TIM_DIER_UDE_Pos (8U)
12923 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
12924 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
12925 #define TIM_DIER_CC1DE_Pos (9U)
12926 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
12927 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
12928 #define TIM_DIER_CC2DE_Pos (10U)
12929 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
12930 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
12931 #define TIM_DIER_CC3DE_Pos (11U)
12932 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
12933 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
12934 #define TIM_DIER_CC4DE_Pos (12U)
12935 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
12936 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
12937 #define TIM_DIER_COMDE_Pos (13U)
12938 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
12939 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
12940 #define TIM_DIER_TDE_Pos (14U)
12941 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
12942 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
12943
12944 /******************** Bit definition for TIM_SR register ********************/
12945 #define TIM_SR_UIF_Pos (0U)
12946 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
12947 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
12948 #define TIM_SR_CC1IF_Pos (1U)
12949 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
12950 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
12951 #define TIM_SR_CC2IF_Pos (2U)
12952 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
12953 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
12954 #define TIM_SR_CC3IF_Pos (3U)
12955 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
12956 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
12957 #define TIM_SR_CC4IF_Pos (4U)
12958 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
12959 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
12960 #define TIM_SR_COMIF_Pos (5U)
12961 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
12962 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
12963 #define TIM_SR_TIF_Pos (6U)
12964 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
12965 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
12966 #define TIM_SR_BIF_Pos (7U)
12967 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
12968 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
12969 #define TIM_SR_B2IF_Pos (8U)
12970 #define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
12971 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */
12972 #define TIM_SR_CC1OF_Pos (9U)
12973 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
12974 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
12975 #define TIM_SR_CC2OF_Pos (10U)
12976 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
12977 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
12978 #define TIM_SR_CC3OF_Pos (11U)
12979 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
12980 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
12981 #define TIM_SR_CC4OF_Pos (12U)
12982 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
12983 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
12984 #define TIM_SR_CC5IF_Pos (16U)
12985 #define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
12986 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
12987 #define TIM_SR_CC6IF_Pos (17U)
12988 #define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
12989 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
12990
12991 /******************* Bit definition for TIM_EGR register ********************/
12992 #define TIM_EGR_UG_Pos (0U)
12993 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
12994 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
12995 #define TIM_EGR_CC1G_Pos (1U)
12996 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
12997 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
12998 #define TIM_EGR_CC2G_Pos (2U)
12999 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
13000 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
13001 #define TIM_EGR_CC3G_Pos (3U)
13002 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
13003 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
13004 #define TIM_EGR_CC4G_Pos (4U)
13005 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
13006 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
13007 #define TIM_EGR_COMG_Pos (5U)
13008 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
13009 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
13010 #define TIM_EGR_TG_Pos (6U)
13011 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
13012 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
13013 #define TIM_EGR_BG_Pos (7U)
13014 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
13015 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
13016 #define TIM_EGR_B2G_Pos (8U)
13017 #define TIM_EGR_B2G_Msk (0x1U << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
13018 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break Generation */
13019
13020 /****************** Bit definition for TIM_CCMR1 register *******************/
13021 #define TIM_CCMR1_CC1S_Pos (0U)
13022 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
13023 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
13024 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
13025 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
13026
13027 #define TIM_CCMR1_OC1FE_Pos (2U)
13028 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
13029 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
13030 #define TIM_CCMR1_OC1PE_Pos (3U)
13031 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
13032 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
13033
13034 #define TIM_CCMR1_OC1M_Pos (4U)
13035 #define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
13036 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
13037 #define TIM_CCMR1_OC1M_0 (0x00000010U) /*!<Bit 0 */
13038 #define TIM_CCMR1_OC1M_1 (0x00000020U) /*!<Bit 1 */
13039 #define TIM_CCMR1_OC1M_2 (0x00000040U) /*!<Bit 2 */
13040 #define TIM_CCMR1_OC1M_3 (0x00010000U) /*!<Bit 3 */
13041
13042 #define TIM_CCMR1_OC1CE_Pos (7U)
13043 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
13044 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
13045
13046 #define TIM_CCMR1_CC2S_Pos (8U)
13047 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
13048 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
13049 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
13050 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
13051
13052 #define TIM_CCMR1_OC2FE_Pos (10U)
13053 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
13054 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
13055 #define TIM_CCMR1_OC2PE_Pos (11U)
13056 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
13057 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
13058
13059 #define TIM_CCMR1_OC2M_Pos (12U)
13060 #define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
13061 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
13062 #define TIM_CCMR1_OC2M_0 (0x00001000U) /*!<Bit 0 */
13063 #define TIM_CCMR1_OC2M_1 (0x00002000U) /*!<Bit 1 */
13064 #define TIM_CCMR1_OC2M_2 (0x00004000U) /*!<Bit 2 */
13065 #define TIM_CCMR1_OC2M_3 (0x01000000U) /*!<Bit 3 */
13066
13067 #define TIM_CCMR1_OC2CE_Pos (15U)
13068 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
13069 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
13070
13071 /*----------------------------------------------------------------------------*/
13072
13073 #define TIM_CCMR1_IC1PSC_Pos (2U)
13074 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
13075 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
13076 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
13077 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
13078
13079 #define TIM_CCMR1_IC1F_Pos (4U)
13080 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
13081 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
13082 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
13083 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
13084 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
13085 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
13086
13087 #define TIM_CCMR1_IC2PSC_Pos (10U)
13088 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
13089 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
13090 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
13091 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
13092
13093 #define TIM_CCMR1_IC2F_Pos (12U)
13094 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
13095 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
13096 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
13097 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
13098 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
13099 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
13100
13101 /****************** Bit definition for TIM_CCMR2 register *******************/
13102 #define TIM_CCMR2_CC3S_Pos (0U)
13103 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
13104 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
13105 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
13106 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
13107
13108 #define TIM_CCMR2_OC3FE_Pos (2U)
13109 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
13110 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
13111 #define TIM_CCMR2_OC3PE_Pos (3U)
13112 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
13113 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
13114
13115 #define TIM_CCMR2_OC3M_Pos (4U)
13116 #define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
13117 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
13118 #define TIM_CCMR2_OC3M_0 (0x00000010U) /*!<Bit 0 */
13119 #define TIM_CCMR2_OC3M_1 (0x00000020U) /*!<Bit 1 */
13120 #define TIM_CCMR2_OC3M_2 (0x00000040U) /*!<Bit 2 */
13121 #define TIM_CCMR2_OC3M_3 (0x00010000U) /*!<Bit 3 */
13122
13123 #define TIM_CCMR2_OC3CE_Pos (7U)
13124 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
13125 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
13126
13127 #define TIM_CCMR2_CC4S_Pos (8U)
13128 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
13129 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
13130 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
13131 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
13132
13133 #define TIM_CCMR2_OC4FE_Pos (10U)
13134 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
13135 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
13136 #define TIM_CCMR2_OC4PE_Pos (11U)
13137 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
13138 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
13139
13140 #define TIM_CCMR2_OC4M_Pos (12U)
13141 #define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
13142 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
13143 #define TIM_CCMR2_OC4M_0 (0x00001000U) /*!<Bit 0 */
13144 #define TIM_CCMR2_OC4M_1 (0x00002000U) /*!<Bit 1 */
13145 #define TIM_CCMR2_OC4M_2 (0x00004000U) /*!<Bit 2 */
13146 #define TIM_CCMR2_OC4M_3 (0x01000000U) /*!<Bit 3 */
13147
13148 #define TIM_CCMR2_OC4CE_Pos (15U)
13149 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
13150 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
13151
13152 /*----------------------------------------------------------------------------*/
13153
13154 #define TIM_CCMR2_IC3PSC_Pos (2U)
13155 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
13156 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
13157 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
13158 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
13159
13160 #define TIM_CCMR2_IC3F_Pos (4U)
13161 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
13162 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
13163 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
13164 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
13165 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
13166 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
13167
13168 #define TIM_CCMR2_IC4PSC_Pos (10U)
13169 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
13170 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
13171 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
13172 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
13173
13174 #define TIM_CCMR2_IC4F_Pos (12U)
13175 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
13176 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
13177 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
13178 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
13179 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
13180 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
13181
13182 /******************* Bit definition for TIM_CCER register *******************/
13183 #define TIM_CCER_CC1E_Pos (0U)
13184 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
13185 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
13186 #define TIM_CCER_CC1P_Pos (1U)
13187 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
13188 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
13189 #define TIM_CCER_CC1NE_Pos (2U)
13190 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
13191 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
13192 #define TIM_CCER_CC1NP_Pos (3U)
13193 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
13194 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
13195 #define TIM_CCER_CC2E_Pos (4U)
13196 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
13197 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
13198 #define TIM_CCER_CC2P_Pos (5U)
13199 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
13200 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
13201 #define TIM_CCER_CC2NE_Pos (6U)
13202 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
13203 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
13204 #define TIM_CCER_CC2NP_Pos (7U)
13205 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
13206 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
13207 #define TIM_CCER_CC3E_Pos (8U)
13208 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
13209 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
13210 #define TIM_CCER_CC3P_Pos (9U)
13211 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
13212 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
13213 #define TIM_CCER_CC3NE_Pos (10U)
13214 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
13215 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
13216 #define TIM_CCER_CC3NP_Pos (11U)
13217 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
13218 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
13219 #define TIM_CCER_CC4E_Pos (12U)
13220 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
13221 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
13222 #define TIM_CCER_CC4P_Pos (13U)
13223 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
13224 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
13225 #define TIM_CCER_CC4NP_Pos (15U)
13226 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
13227 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
13228 #define TIM_CCER_CC5E_Pos (16U)
13229 #define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
13230 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
13231 #define TIM_CCER_CC5P_Pos (17U)
13232 #define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
13233 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
13234 #define TIM_CCER_CC6E_Pos (20U)
13235 #define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
13236 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
13237 #define TIM_CCER_CC6P_Pos (21U)
13238 #define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
13239 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
13240
13241 /******************* Bit definition for TIM_CNT register ********************/
13242 #define TIM_CNT_CNT_Pos (0U)
13243 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
13244 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
13245 #define TIM_CNT_UIFCPY_Pos (31U)
13246 #define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
13247 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy */
13248
13249 /******************* Bit definition for TIM_PSC register ********************/
13250 #define TIM_PSC_PSC_Pos (0U)
13251 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
13252 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
13253
13254 /******************* Bit definition for TIM_ARR register ********************/
13255 #define TIM_ARR_ARR_Pos (0U)
13256 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
13257 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
13258
13259 /******************* Bit definition for TIM_RCR register ********************/
13260 #define TIM_RCR_REP_Pos (0U)
13261 #define TIM_RCR_REP_Msk (0xFFFFU << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
13262 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
13263
13264 /******************* Bit definition for TIM_CCR1 register *******************/
13265 #define TIM_CCR1_CCR1_Pos (0U)
13266 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
13267 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
13268
13269 /******************* Bit definition for TIM_CCR2 register *******************/
13270 #define TIM_CCR2_CCR2_Pos (0U)
13271 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
13272 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
13273
13274 /******************* Bit definition for TIM_CCR3 register *******************/
13275 #define TIM_CCR3_CCR3_Pos (0U)
13276 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
13277 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
13278
13279 /******************* Bit definition for TIM_CCR4 register *******************/
13280 #define TIM_CCR4_CCR4_Pos (0U)
13281 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
13282 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
13283
13284 /******************* Bit definition for TIM_CCR5 register *******************/
13285 #define TIM_CCR5_CCR5_Pos (0U)
13286 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
13287 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
13288 #define TIM_CCR5_GC5C1_Pos (29U)
13289 #define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
13290 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
13291 #define TIM_CCR5_GC5C2_Pos (30U)
13292 #define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
13293 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
13294 #define TIM_CCR5_GC5C3_Pos (31U)
13295 #define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
13296 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
13297
13298 /******************* Bit definition for TIM_CCR6 register *******************/
13299 #define TIM_CCR6_CCR6_Pos (0U)
13300 #define TIM_CCR6_CCR6_Msk (0xFFFFU << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
13301 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
13302
13303 /******************* Bit definition for TIM_BDTR register *******************/
13304 #define TIM_BDTR_DTG_Pos (0U)
13305 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
13306 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
13307 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
13308 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
13309 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
13310 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
13311 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
13312 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
13313 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
13314 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
13315
13316 #define TIM_BDTR_LOCK_Pos (8U)
13317 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
13318 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
13319 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
13320 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
13321
13322 #define TIM_BDTR_OSSI_Pos (10U)
13323 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
13324 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
13325 #define TIM_BDTR_OSSR_Pos (11U)
13326 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
13327 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
13328 #define TIM_BDTR_BKE_Pos (12U)
13329 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
13330 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break1 */
13331 #define TIM_BDTR_BKP_Pos (13U)
13332 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
13333 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break1 */
13334 #define TIM_BDTR_AOE_Pos (14U)
13335 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
13336 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
13337 #define TIM_BDTR_MOE_Pos (15U)
13338 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
13339 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
13340
13341 #define TIM_BDTR_BKF_Pos (16U)
13342 #define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
13343 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */
13344 #define TIM_BDTR_BK2F_Pos (20U)
13345 #define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
13346 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */
13347
13348 #define TIM_BDTR_BK2E_Pos (24U)
13349 #define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
13350 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */
13351 #define TIM_BDTR_BK2P_Pos (25U)
13352 #define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
13353 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
13354
13355 /******************* Bit definition for TIM_DCR register ********************/
13356 #define TIM_DCR_DBA_Pos (0U)
13357 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
13358 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
13359 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
13360 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
13361 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
13362 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
13363 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
13364
13365 #define TIM_DCR_DBL_Pos (8U)
13366 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
13367 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
13368 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
13369 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
13370 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
13371 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
13372 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
13373
13374 /******************* Bit definition for TIM_DMAR register *******************/
13375 #define TIM_DMAR_DMAB_Pos (0U)
13376 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
13377 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
13378
13379 /******************* Bit definition for TIM16_OR register *********************/
13380 #define TIM16_OR_TI1_RMP_Pos (0U)
13381 #define TIM16_OR_TI1_RMP_Msk (0x3U << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000003 */
13382 #define TIM16_OR_TI1_RMP TIM16_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
13383 #define TIM16_OR_TI1_RMP_0 (0x1U << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000001 */
13384 #define TIM16_OR_TI1_RMP_1 (0x2U << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000002 */
13385
13386 /******************* Bit definition for TIM1_OR register *********************/
13387 #define TIM1_OR_ETR_RMP_Pos (0U)
13388 #define TIM1_OR_ETR_RMP_Msk (0xFU << TIM1_OR_ETR_RMP_Pos) /*!< 0x0000000F */
13389 #define TIM1_OR_ETR_RMP TIM1_OR_ETR_RMP_Msk /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
13390 #define TIM1_OR_ETR_RMP_0 (0x1U << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000001 */
13391 #define TIM1_OR_ETR_RMP_1 (0x2U << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000002 */
13392 #define TIM1_OR_ETR_RMP_2 (0x4U << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000004 */
13393 #define TIM1_OR_ETR_RMP_3 (0x8U << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000008 */
13394
13395 /******************* Bit definition for TIM8_OR register *********************/
13396 #define TIM8_OR_ETR_RMP_Pos (0U)
13397 #define TIM8_OR_ETR_RMP_Msk (0xFU << TIM8_OR_ETR_RMP_Pos) /*!< 0x0000000F */
13398 #define TIM8_OR_ETR_RMP TIM8_OR_ETR_RMP_Msk /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */
13399 #define TIM8_OR_ETR_RMP_0 (0x1U << TIM8_OR_ETR_RMP_Pos) /*!< 0x00000001 */
13400 #define TIM8_OR_ETR_RMP_1 (0x2U << TIM8_OR_ETR_RMP_Pos) /*!< 0x00000002 */
13401 #define TIM8_OR_ETR_RMP_2 (0x4U << TIM8_OR_ETR_RMP_Pos) /*!< 0x00000004 */
13402 #define TIM8_OR_ETR_RMP_3 (0x8U << TIM8_OR_ETR_RMP_Pos) /*!< 0x00000008 */
13403
13404 /******************* Bit definition for TIM20_OR register *******************/
13405 #define TIM20_OR_ETR_RMP_Pos (0U)
13406 #define TIM20_OR_ETR_RMP_Msk (0xFU << TIM20_OR_ETR_RMP_Pos) /*!< 0x0000000F */
13407 #define TIM20_OR_ETR_RMP TIM20_OR_ETR_RMP_Msk /*!<ETR_RMP[3:0] bits (TIM20 ETR remap) */
13408 #define TIM20_OR_ETR_RMP_0 (0x1U << TIM20_OR_ETR_RMP_Pos) /*!< 0x00000001 */
13409 #define TIM20_OR_ETR_RMP_1 (0x2U << TIM20_OR_ETR_RMP_Pos) /*!< 0x00000002 */
13410 #define TIM20_OR_ETR_RMP_2 (0x4U << TIM20_OR_ETR_RMP_Pos) /*!< 0x00000004 */
13411 #define TIM20_OR_ETR_RMP_3 (0x8U << TIM20_OR_ETR_RMP_Pos) /*!< 0x00000008 */
13412
13413 /****************** Bit definition for TIM_CCMR3 register *******************/
13414 #define TIM_CCMR3_OC5FE_Pos (2U)
13415 #define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
13416 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
13417 #define TIM_CCMR3_OC5PE_Pos (3U)
13418 #define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
13419 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
13420
13421 #define TIM_CCMR3_OC5M_Pos (4U)
13422 #define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
13423 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
13424 #define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
13425 #define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
13426 #define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
13427 #define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
13428
13429 #define TIM_CCMR3_OC5CE_Pos (7U)
13430 #define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
13431 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
13432
13433 #define TIM_CCMR3_OC6FE_Pos (10U)
13434 #define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
13435 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
13436 #define TIM_CCMR3_OC6PE_Pos (11U)
13437 #define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
13438 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
13439
13440 #define TIM_CCMR3_OC6M_Pos (12U)
13441 #define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
13442 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[2:0] bits (Output Compare 6 Mode) */
13443 #define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
13444 #define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
13445 #define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
13446 #define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
13447
13448 #define TIM_CCMR3_OC6CE_Pos (15U)
13449 #define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
13450 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
13451
13452 /******************************************************************************/
13453 /* */
13454 /* Touch Sensing Controller (TSC) */
13455 /* */
13456 /******************************************************************************/
13457 /******************* Bit definition for TSC_CR register *********************/
13458 #define TSC_CR_TSCE_Pos (0U)
13459 #define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
13460 #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
13461 #define TSC_CR_START_Pos (1U)
13462 #define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */
13463 #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
13464 #define TSC_CR_AM_Pos (2U)
13465 #define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */
13466 #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
13467 #define TSC_CR_SYNCPOL_Pos (3U)
13468 #define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
13469 #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
13470 #define TSC_CR_IODEF_Pos (4U)
13471 #define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
13472 #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
13473
13474 #define TSC_CR_MCV_Pos (5U)
13475 #define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
13476 #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
13477 #define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */
13478 #define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */
13479 #define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */
13480
13481 #define TSC_CR_PGPSC_Pos (12U)
13482 #define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
13483 #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
13484 #define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
13485 #define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
13486 #define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
13487
13488 #define TSC_CR_SSPSC_Pos (15U)
13489 #define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
13490 #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
13491 #define TSC_CR_SSE_Pos (16U)
13492 #define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */
13493 #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
13494
13495 #define TSC_CR_SSD_Pos (17U)
13496 #define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
13497 #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
13498 #define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */
13499 #define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */
13500 #define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */
13501 #define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */
13502 #define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */
13503 #define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */
13504 #define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */
13505
13506 #define TSC_CR_CTPL_Pos (24U)
13507 #define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
13508 #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
13509 #define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
13510 #define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
13511 #define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
13512 #define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
13513
13514 #define TSC_CR_CTPH_Pos (28U)
13515 #define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
13516 #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
13517 #define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
13518 #define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
13519 #define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
13520 #define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
13521
13522 /******************* Bit definition for TSC_IER register ********************/
13523 #define TSC_IER_EOAIE_Pos (0U)
13524 #define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
13525 #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
13526 #define TSC_IER_MCEIE_Pos (1U)
13527 #define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
13528 #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
13529
13530 /******************* Bit definition for TSC_ICR register ********************/
13531 #define TSC_ICR_EOAIC_Pos (0U)
13532 #define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
13533 #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
13534 #define TSC_ICR_MCEIC_Pos (1U)
13535 #define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
13536 #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
13537
13538 /******************* Bit definition for TSC_ISR register ********************/
13539 #define TSC_ISR_EOAF_Pos (0U)
13540 #define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
13541 #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
13542 #define TSC_ISR_MCEF_Pos (1U)
13543 #define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
13544 #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
13545
13546 /******************* Bit definition for TSC_IOHCR register ******************/
13547 #define TSC_IOHCR_G1_IO1_Pos (0U)
13548 #define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
13549 #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
13550 #define TSC_IOHCR_G1_IO2_Pos (1U)
13551 #define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
13552 #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
13553 #define TSC_IOHCR_G1_IO3_Pos (2U)
13554 #define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
13555 #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
13556 #define TSC_IOHCR_G1_IO4_Pos (3U)
13557 #define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
13558 #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
13559 #define TSC_IOHCR_G2_IO1_Pos (4U)
13560 #define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
13561 #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
13562 #define TSC_IOHCR_G2_IO2_Pos (5U)
13563 #define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
13564 #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
13565 #define TSC_IOHCR_G2_IO3_Pos (6U)
13566 #define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
13567 #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
13568 #define TSC_IOHCR_G2_IO4_Pos (7U)
13569 #define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
13570 #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
13571 #define TSC_IOHCR_G3_IO1_Pos (8U)
13572 #define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
13573 #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
13574 #define TSC_IOHCR_G3_IO2_Pos (9U)
13575 #define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
13576 #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
13577 #define TSC_IOHCR_G3_IO3_Pos (10U)
13578 #define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
13579 #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
13580 #define TSC_IOHCR_G3_IO4_Pos (11U)
13581 #define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
13582 #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
13583 #define TSC_IOHCR_G4_IO1_Pos (12U)
13584 #define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
13585 #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
13586 #define TSC_IOHCR_G4_IO2_Pos (13U)
13587 #define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
13588 #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
13589 #define TSC_IOHCR_G4_IO3_Pos (14U)
13590 #define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
13591 #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
13592 #define TSC_IOHCR_G4_IO4_Pos (15U)
13593 #define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
13594 #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
13595 #define TSC_IOHCR_G5_IO1_Pos (16U)
13596 #define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
13597 #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
13598 #define TSC_IOHCR_G5_IO2_Pos (17U)
13599 #define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
13600 #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
13601 #define TSC_IOHCR_G5_IO3_Pos (18U)
13602 #define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
13603 #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
13604 #define TSC_IOHCR_G5_IO4_Pos (19U)
13605 #define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
13606 #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
13607 #define TSC_IOHCR_G6_IO1_Pos (20U)
13608 #define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
13609 #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
13610 #define TSC_IOHCR_G6_IO2_Pos (21U)
13611 #define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
13612 #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
13613 #define TSC_IOHCR_G6_IO3_Pos (22U)
13614 #define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
13615 #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
13616 #define TSC_IOHCR_G6_IO4_Pos (23U)
13617 #define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
13618 #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
13619 #define TSC_IOHCR_G7_IO1_Pos (24U)
13620 #define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
13621 #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
13622 #define TSC_IOHCR_G7_IO2_Pos (25U)
13623 #define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
13624 #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
13625 #define TSC_IOHCR_G7_IO3_Pos (26U)
13626 #define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
13627 #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
13628 #define TSC_IOHCR_G7_IO4_Pos (27U)
13629 #define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
13630 #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
13631 #define TSC_IOHCR_G8_IO1_Pos (28U)
13632 #define TSC_IOHCR_G8_IO1_Msk (0x1U << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
13633 #define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
13634 #define TSC_IOHCR_G8_IO2_Pos (29U)
13635 #define TSC_IOHCR_G8_IO2_Msk (0x1U << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
13636 #define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
13637 #define TSC_IOHCR_G8_IO3_Pos (30U)
13638 #define TSC_IOHCR_G8_IO3_Msk (0x1U << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
13639 #define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
13640 #define TSC_IOHCR_G8_IO4_Pos (31U)
13641 #define TSC_IOHCR_G8_IO4_Msk (0x1U << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
13642 #define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
13643
13644 /******************* Bit definition for TSC_IOASCR register *****************/
13645 #define TSC_IOASCR_G1_IO1_Pos (0U)
13646 #define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
13647 #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
13648 #define TSC_IOASCR_G1_IO2_Pos (1U)
13649 #define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
13650 #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
13651 #define TSC_IOASCR_G1_IO3_Pos (2U)
13652 #define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
13653 #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
13654 #define TSC_IOASCR_G1_IO4_Pos (3U)
13655 #define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
13656 #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
13657 #define TSC_IOASCR_G2_IO1_Pos (4U)
13658 #define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
13659 #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
13660 #define TSC_IOASCR_G2_IO2_Pos (5U)
13661 #define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
13662 #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
13663 #define TSC_IOASCR_G2_IO3_Pos (6U)
13664 #define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
13665 #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
13666 #define TSC_IOASCR_G2_IO4_Pos (7U)
13667 #define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
13668 #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
13669 #define TSC_IOASCR_G3_IO1_Pos (8U)
13670 #define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
13671 #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
13672 #define TSC_IOASCR_G3_IO2_Pos (9U)
13673 #define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
13674 #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
13675 #define TSC_IOASCR_G3_IO3_Pos (10U)
13676 #define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
13677 #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
13678 #define TSC_IOASCR_G3_IO4_Pos (11U)
13679 #define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
13680 #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
13681 #define TSC_IOASCR_G4_IO1_Pos (12U)
13682 #define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
13683 #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
13684 #define TSC_IOASCR_G4_IO2_Pos (13U)
13685 #define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
13686 #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
13687 #define TSC_IOASCR_G4_IO3_Pos (14U)
13688 #define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
13689 #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
13690 #define TSC_IOASCR_G4_IO4_Pos (15U)
13691 #define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
13692 #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
13693 #define TSC_IOASCR_G5_IO1_Pos (16U)
13694 #define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
13695 #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
13696 #define TSC_IOASCR_G5_IO2_Pos (17U)
13697 #define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
13698 #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
13699 #define TSC_IOASCR_G5_IO3_Pos (18U)
13700 #define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
13701 #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
13702 #define TSC_IOASCR_G5_IO4_Pos (19U)
13703 #define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
13704 #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
13705 #define TSC_IOASCR_G6_IO1_Pos (20U)
13706 #define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
13707 #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
13708 #define TSC_IOASCR_G6_IO2_Pos (21U)
13709 #define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
13710 #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
13711 #define TSC_IOASCR_G6_IO3_Pos (22U)
13712 #define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
13713 #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
13714 #define TSC_IOASCR_G6_IO4_Pos (23U)
13715 #define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
13716 #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
13717 #define TSC_IOASCR_G7_IO1_Pos (24U)
13718 #define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
13719 #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
13720 #define TSC_IOASCR_G7_IO2_Pos (25U)
13721 #define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
13722 #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
13723 #define TSC_IOASCR_G7_IO3_Pos (26U)
13724 #define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
13725 #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
13726 #define TSC_IOASCR_G7_IO4_Pos (27U)
13727 #define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
13728 #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
13729 #define TSC_IOASCR_G8_IO1_Pos (28U)
13730 #define TSC_IOASCR_G8_IO1_Msk (0x1U << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
13731 #define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
13732 #define TSC_IOASCR_G8_IO2_Pos (29U)
13733 #define TSC_IOASCR_G8_IO2_Msk (0x1U << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
13734 #define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
13735 #define TSC_IOASCR_G8_IO3_Pos (30U)
13736 #define TSC_IOASCR_G8_IO3_Msk (0x1U << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
13737 #define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
13738 #define TSC_IOASCR_G8_IO4_Pos (31U)
13739 #define TSC_IOASCR_G8_IO4_Msk (0x1U << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
13740 #define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
13741
13742 /******************* Bit definition for TSC_IOSCR register ******************/
13743 #define TSC_IOSCR_G1_IO1_Pos (0U)
13744 #define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
13745 #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
13746 #define TSC_IOSCR_G1_IO2_Pos (1U)
13747 #define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
13748 #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
13749 #define TSC_IOSCR_G1_IO3_Pos (2U)
13750 #define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
13751 #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
13752 #define TSC_IOSCR_G1_IO4_Pos (3U)
13753 #define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
13754 #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
13755 #define TSC_IOSCR_G2_IO1_Pos (4U)
13756 #define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
13757 #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
13758 #define TSC_IOSCR_G2_IO2_Pos (5U)
13759 #define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
13760 #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
13761 #define TSC_IOSCR_G2_IO3_Pos (6U)
13762 #define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
13763 #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
13764 #define TSC_IOSCR_G2_IO4_Pos (7U)
13765 #define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
13766 #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
13767 #define TSC_IOSCR_G3_IO1_Pos (8U)
13768 #define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
13769 #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
13770 #define TSC_IOSCR_G3_IO2_Pos (9U)
13771 #define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
13772 #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
13773 #define TSC_IOSCR_G3_IO3_Pos (10U)
13774 #define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
13775 #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
13776 #define TSC_IOSCR_G3_IO4_Pos (11U)
13777 #define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
13778 #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
13779 #define TSC_IOSCR_G4_IO1_Pos (12U)
13780 #define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
13781 #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
13782 #define TSC_IOSCR_G4_IO2_Pos (13U)
13783 #define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
13784 #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
13785 #define TSC_IOSCR_G4_IO3_Pos (14U)
13786 #define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
13787 #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
13788 #define TSC_IOSCR_G4_IO4_Pos (15U)
13789 #define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
13790 #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
13791 #define TSC_IOSCR_G5_IO1_Pos (16U)
13792 #define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
13793 #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
13794 #define TSC_IOSCR_G5_IO2_Pos (17U)
13795 #define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
13796 #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
13797 #define TSC_IOSCR_G5_IO3_Pos (18U)
13798 #define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
13799 #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
13800 #define TSC_IOSCR_G5_IO4_Pos (19U)
13801 #define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
13802 #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
13803 #define TSC_IOSCR_G6_IO1_Pos (20U)
13804 #define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
13805 #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
13806 #define TSC_IOSCR_G6_IO2_Pos (21U)
13807 #define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
13808 #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
13809 #define TSC_IOSCR_G6_IO3_Pos (22U)
13810 #define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
13811 #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
13812 #define TSC_IOSCR_G6_IO4_Pos (23U)
13813 #define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
13814 #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
13815 #define TSC_IOSCR_G7_IO1_Pos (24U)
13816 #define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
13817 #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
13818 #define TSC_IOSCR_G7_IO2_Pos (25U)
13819 #define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
13820 #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
13821 #define TSC_IOSCR_G7_IO3_Pos (26U)
13822 #define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
13823 #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
13824 #define TSC_IOSCR_G7_IO4_Pos (27U)
13825 #define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
13826 #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
13827 #define TSC_IOSCR_G8_IO1_Pos (28U)
13828 #define TSC_IOSCR_G8_IO1_Msk (0x1U << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
13829 #define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
13830 #define TSC_IOSCR_G8_IO2_Pos (29U)
13831 #define TSC_IOSCR_G8_IO2_Msk (0x1U << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
13832 #define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
13833 #define TSC_IOSCR_G8_IO3_Pos (30U)
13834 #define TSC_IOSCR_G8_IO3_Msk (0x1U << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
13835 #define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
13836 #define TSC_IOSCR_G8_IO4_Pos (31U)
13837 #define TSC_IOSCR_G8_IO4_Msk (0x1U << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
13838 #define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
13839
13840 /******************* Bit definition for TSC_IOCCR register ******************/
13841 #define TSC_IOCCR_G1_IO1_Pos (0U)
13842 #define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
13843 #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
13844 #define TSC_IOCCR_G1_IO2_Pos (1U)
13845 #define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
13846 #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
13847 #define TSC_IOCCR_G1_IO3_Pos (2U)
13848 #define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
13849 #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
13850 #define TSC_IOCCR_G1_IO4_Pos (3U)
13851 #define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
13852 #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
13853 #define TSC_IOCCR_G2_IO1_Pos (4U)
13854 #define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
13855 #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
13856 #define TSC_IOCCR_G2_IO2_Pos (5U)
13857 #define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
13858 #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
13859 #define TSC_IOCCR_G2_IO3_Pos (6U)
13860 #define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
13861 #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
13862 #define TSC_IOCCR_G2_IO4_Pos (7U)
13863 #define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
13864 #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
13865 #define TSC_IOCCR_G3_IO1_Pos (8U)
13866 #define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
13867 #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
13868 #define TSC_IOCCR_G3_IO2_Pos (9U)
13869 #define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
13870 #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
13871 #define TSC_IOCCR_G3_IO3_Pos (10U)
13872 #define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
13873 #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
13874 #define TSC_IOCCR_G3_IO4_Pos (11U)
13875 #define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
13876 #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
13877 #define TSC_IOCCR_G4_IO1_Pos (12U)
13878 #define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
13879 #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
13880 #define TSC_IOCCR_G4_IO2_Pos (13U)
13881 #define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
13882 #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
13883 #define TSC_IOCCR_G4_IO3_Pos (14U)
13884 #define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
13885 #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
13886 #define TSC_IOCCR_G4_IO4_Pos (15U)
13887 #define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
13888 #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
13889 #define TSC_IOCCR_G5_IO1_Pos (16U)
13890 #define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
13891 #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
13892 #define TSC_IOCCR_G5_IO2_Pos (17U)
13893 #define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
13894 #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
13895 #define TSC_IOCCR_G5_IO3_Pos (18U)
13896 #define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
13897 #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
13898 #define TSC_IOCCR_G5_IO4_Pos (19U)
13899 #define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
13900 #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
13901 #define TSC_IOCCR_G6_IO1_Pos (20U)
13902 #define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
13903 #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
13904 #define TSC_IOCCR_G6_IO2_Pos (21U)
13905 #define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
13906 #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
13907 #define TSC_IOCCR_G6_IO3_Pos (22U)
13908 #define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
13909 #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
13910 #define TSC_IOCCR_G6_IO4_Pos (23U)
13911 #define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
13912 #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
13913 #define TSC_IOCCR_G7_IO1_Pos (24U)
13914 #define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
13915 #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
13916 #define TSC_IOCCR_G7_IO2_Pos (25U)
13917 #define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
13918 #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
13919 #define TSC_IOCCR_G7_IO3_Pos (26U)
13920 #define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
13921 #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
13922 #define TSC_IOCCR_G7_IO4_Pos (27U)
13923 #define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
13924 #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
13925 #define TSC_IOCCR_G8_IO1_Pos (28U)
13926 #define TSC_IOCCR_G8_IO1_Msk (0x1U << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
13927 #define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
13928 #define TSC_IOCCR_G8_IO2_Pos (29U)
13929 #define TSC_IOCCR_G8_IO2_Msk (0x1U << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
13930 #define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
13931 #define TSC_IOCCR_G8_IO3_Pos (30U)
13932 #define TSC_IOCCR_G8_IO3_Msk (0x1U << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
13933 #define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
13934 #define TSC_IOCCR_G8_IO4_Pos (31U)
13935 #define TSC_IOCCR_G8_IO4_Msk (0x1U << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
13936 #define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
13937
13938 /******************* Bit definition for TSC_IOGCSR register *****************/
13939 #define TSC_IOGCSR_G1E_Pos (0U)
13940 #define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
13941 #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
13942 #define TSC_IOGCSR_G2E_Pos (1U)
13943 #define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
13944 #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
13945 #define TSC_IOGCSR_G3E_Pos (2U)
13946 #define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
13947 #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
13948 #define TSC_IOGCSR_G4E_Pos (3U)
13949 #define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
13950 #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
13951 #define TSC_IOGCSR_G5E_Pos (4U)
13952 #define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
13953 #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
13954 #define TSC_IOGCSR_G6E_Pos (5U)
13955 #define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
13956 #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
13957 #define TSC_IOGCSR_G7E_Pos (6U)
13958 #define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
13959 #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
13960 #define TSC_IOGCSR_G8E_Pos (7U)
13961 #define TSC_IOGCSR_G8E_Msk (0x1U << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
13962 #define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
13963 #define TSC_IOGCSR_G1S_Pos (16U)
13964 #define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
13965 #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
13966 #define TSC_IOGCSR_G2S_Pos (17U)
13967 #define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
13968 #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
13969 #define TSC_IOGCSR_G3S_Pos (18U)
13970 #define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
13971 #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
13972 #define TSC_IOGCSR_G4S_Pos (19U)
13973 #define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
13974 #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
13975 #define TSC_IOGCSR_G5S_Pos (20U)
13976 #define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
13977 #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
13978 #define TSC_IOGCSR_G6S_Pos (21U)
13979 #define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
13980 #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
13981 #define TSC_IOGCSR_G7S_Pos (22U)
13982 #define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
13983 #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
13984 #define TSC_IOGCSR_G8S_Pos (23U)
13985 #define TSC_IOGCSR_G8S_Msk (0x1U << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
13986 #define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
13987
13988 /******************* Bit definition for TSC_IOGXCR register *****************/
13989 #define TSC_IOGXCR_CNT_Pos (0U)
13990 #define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
13991 #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
13992
13993 /******************************************************************************/
13994 /* */
13995 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
13996 /* */
13997 /******************************************************************************/
13998
13999 /*
14000 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
14001 */
14002
14003 /* Support of 7 bits data length feature */
14004 #define USART_7BITS_SUPPORT
14005
14006 /****************** Bit definition for USART_CR1 register *******************/
14007 #define USART_CR1_UE_Pos (0U)
14008 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
14009 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
14010 #define USART_CR1_UESM_Pos (1U)
14011 #define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
14012 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
14013 #define USART_CR1_RE_Pos (2U)
14014 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
14015 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
14016 #define USART_CR1_TE_Pos (3U)
14017 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
14018 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
14019 #define USART_CR1_IDLEIE_Pos (4U)
14020 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
14021 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
14022 #define USART_CR1_RXNEIE_Pos (5U)
14023 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
14024 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
14025 #define USART_CR1_TCIE_Pos (6U)
14026 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
14027 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
14028 #define USART_CR1_TXEIE_Pos (7U)
14029 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
14030 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
14031 #define USART_CR1_PEIE_Pos (8U)
14032 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
14033 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
14034 #define USART_CR1_PS_Pos (9U)
14035 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
14036 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
14037 #define USART_CR1_PCE_Pos (10U)
14038 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
14039 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
14040 #define USART_CR1_WAKE_Pos (11U)
14041 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
14042 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
14043 #define USART_CR1_M0_Pos (12U)
14044 #define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
14045 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length bit 0 */
14046 #define USART_CR1_MME_Pos (13U)
14047 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
14048 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
14049 #define USART_CR1_CMIE_Pos (14U)
14050 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
14051 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
14052 #define USART_CR1_OVER8_Pos (15U)
14053 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
14054 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
14055 #define USART_CR1_DEDT_Pos (16U)
14056 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
14057 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
14058 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
14059 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
14060 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
14061 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
14062 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
14063 #define USART_CR1_DEAT_Pos (21U)
14064 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
14065 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
14066 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
14067 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
14068 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
14069 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
14070 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
14071 #define USART_CR1_RTOIE_Pos (26U)
14072 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
14073 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
14074 #define USART_CR1_EOBIE_Pos (27U)
14075 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
14076 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
14077 #define USART_CR1_M1_Pos (28U)
14078 #define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
14079 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length bit 1 */
14080 #define USART_CR1_M_Pos (12U)
14081 #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
14082 #define USART_CR1_M USART_CR1_M_Msk /*!< [M1:M0] Word length */
14083
14084 /****************** Bit definition for USART_CR2 register *******************/
14085 #define USART_CR2_ADDM7_Pos (4U)
14086 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
14087 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
14088 #define USART_CR2_LBDL_Pos (5U)
14089 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
14090 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
14091 #define USART_CR2_LBDIE_Pos (6U)
14092 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
14093 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
14094 #define USART_CR2_LBCL_Pos (8U)
14095 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
14096 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
14097 #define USART_CR2_CPHA_Pos (9U)
14098 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
14099 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
14100 #define USART_CR2_CPOL_Pos (10U)
14101 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
14102 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
14103 #define USART_CR2_CLKEN_Pos (11U)
14104 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
14105 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
14106 #define USART_CR2_STOP_Pos (12U)
14107 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
14108 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
14109 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
14110 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
14111 #define USART_CR2_LINEN_Pos (14U)
14112 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
14113 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
14114 #define USART_CR2_SWAP_Pos (15U)
14115 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
14116 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
14117 #define USART_CR2_RXINV_Pos (16U)
14118 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
14119 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
14120 #define USART_CR2_TXINV_Pos (17U)
14121 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
14122 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
14123 #define USART_CR2_DATAINV_Pos (18U)
14124 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
14125 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
14126 #define USART_CR2_MSBFIRST_Pos (19U)
14127 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
14128 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
14129 #define USART_CR2_ABREN_Pos (20U)
14130 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
14131 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
14132 #define USART_CR2_ABRMODE_Pos (21U)
14133 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
14134 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
14135 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
14136 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
14137 #define USART_CR2_RTOEN_Pos (23U)
14138 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
14139 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
14140 #define USART_CR2_ADD_Pos (24U)
14141 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
14142 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
14143
14144 /****************** Bit definition for USART_CR3 register *******************/
14145 #define USART_CR3_EIE_Pos (0U)
14146 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
14147 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
14148 #define USART_CR3_IREN_Pos (1U)
14149 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
14150 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
14151 #define USART_CR3_IRLP_Pos (2U)
14152 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
14153 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
14154 #define USART_CR3_HDSEL_Pos (3U)
14155 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
14156 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
14157 #define USART_CR3_NACK_Pos (4U)
14158 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
14159 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
14160 #define USART_CR3_SCEN_Pos (5U)
14161 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
14162 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
14163 #define USART_CR3_DMAR_Pos (6U)
14164 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
14165 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
14166 #define USART_CR3_DMAT_Pos (7U)
14167 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
14168 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
14169 #define USART_CR3_RTSE_Pos (8U)
14170 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
14171 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
14172 #define USART_CR3_CTSE_Pos (9U)
14173 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
14174 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
14175 #define USART_CR3_CTSIE_Pos (10U)
14176 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
14177 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
14178 #define USART_CR3_ONEBIT_Pos (11U)
14179 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
14180 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
14181 #define USART_CR3_OVRDIS_Pos (12U)
14182 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
14183 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
14184 #define USART_CR3_DDRE_Pos (13U)
14185 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
14186 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
14187 #define USART_CR3_DEM_Pos (14U)
14188 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
14189 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
14190 #define USART_CR3_DEP_Pos (15U)
14191 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
14192 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
14193 #define USART_CR3_SCARCNT_Pos (17U)
14194 #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
14195 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
14196 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
14197 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
14198 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
14199 #define USART_CR3_WUS_Pos (20U)
14200 #define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
14201 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
14202 #define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
14203 #define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
14204 #define USART_CR3_WUFIE_Pos (22U)
14205 #define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
14206 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
14207
14208 /****************** Bit definition for USART_BRR register *******************/
14209 #define USART_BRR_DIV_FRACTION_Pos (0U)
14210 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
14211 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
14212 #define USART_BRR_DIV_MANTISSA_Pos (4U)
14213 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
14214 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
14215
14216 /****************** Bit definition for USART_GTPR register ******************/
14217 #define USART_GTPR_PSC_Pos (0U)
14218 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
14219 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
14220 #define USART_GTPR_GT_Pos (8U)
14221 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
14222 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
14223
14224
14225 /******************* Bit definition for USART_RTOR register *****************/
14226 #define USART_RTOR_RTO_Pos (0U)
14227 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
14228 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
14229 #define USART_RTOR_BLEN_Pos (24U)
14230 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
14231 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
14232
14233 /******************* Bit definition for USART_RQR register ******************/
14234 #define USART_RQR_ABRRQ_Pos (0U)
14235 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
14236 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
14237 #define USART_RQR_SBKRQ_Pos (1U)
14238 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
14239 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
14240 #define USART_RQR_MMRQ_Pos (2U)
14241 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
14242 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
14243 #define USART_RQR_RXFRQ_Pos (3U)
14244 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
14245 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
14246 #define USART_RQR_TXFRQ_Pos (4U)
14247 #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
14248 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
14249
14250 /******************* Bit definition for USART_ISR register ******************/
14251 #define USART_ISR_PE_Pos (0U)
14252 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
14253 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
14254 #define USART_ISR_FE_Pos (1U)
14255 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
14256 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
14257 #define USART_ISR_NE_Pos (2U)
14258 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
14259 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
14260 #define USART_ISR_ORE_Pos (3U)
14261 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
14262 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
14263 #define USART_ISR_IDLE_Pos (4U)
14264 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
14265 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
14266 #define USART_ISR_RXNE_Pos (5U)
14267 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
14268 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
14269 #define USART_ISR_TC_Pos (6U)
14270 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
14271 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
14272 #define USART_ISR_TXE_Pos (7U)
14273 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
14274 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
14275 #define USART_ISR_LBDF_Pos (8U)
14276 #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
14277 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
14278 #define USART_ISR_CTSIF_Pos (9U)
14279 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
14280 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
14281 #define USART_ISR_CTS_Pos (10U)
14282 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
14283 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
14284 #define USART_ISR_RTOF_Pos (11U)
14285 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
14286 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
14287 #define USART_ISR_EOBF_Pos (12U)
14288 #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
14289 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
14290 #define USART_ISR_ABRE_Pos (14U)
14291 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
14292 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
14293 #define USART_ISR_ABRF_Pos (15U)
14294 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
14295 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
14296 #define USART_ISR_BUSY_Pos (16U)
14297 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
14298 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
14299 #define USART_ISR_CMF_Pos (17U)
14300 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
14301 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
14302 #define USART_ISR_SBKF_Pos (18U)
14303 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
14304 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
14305 #define USART_ISR_RWU_Pos (19U)
14306 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
14307 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
14308 #define USART_ISR_WUF_Pos (20U)
14309 #define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
14310 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
14311 #define USART_ISR_TEACK_Pos (21U)
14312 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
14313 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
14314 #define USART_ISR_REACK_Pos (22U)
14315 #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
14316 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
14317
14318 /******************* Bit definition for USART_ICR register ******************/
14319 #define USART_ICR_PECF_Pos (0U)
14320 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
14321 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
14322 #define USART_ICR_FECF_Pos (1U)
14323 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
14324 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
14325 #define USART_ICR_NCF_Pos (2U)
14326 #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
14327 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
14328 #define USART_ICR_ORECF_Pos (3U)
14329 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
14330 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
14331 #define USART_ICR_IDLECF_Pos (4U)
14332 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
14333 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
14334 #define USART_ICR_TCCF_Pos (6U)
14335 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
14336 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
14337 #define USART_ICR_LBDCF_Pos (8U)
14338 #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
14339 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
14340 #define USART_ICR_CTSCF_Pos (9U)
14341 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
14342 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
14343 #define USART_ICR_RTOCF_Pos (11U)
14344 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
14345 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
14346 #define USART_ICR_EOBCF_Pos (12U)
14347 #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
14348 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
14349 #define USART_ICR_CMCF_Pos (17U)
14350 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
14351 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
14352 #define USART_ICR_WUCF_Pos (20U)
14353 #define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
14354 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
14355
14356 /******************* Bit definition for USART_RDR register ******************/
14357 #define USART_RDR_RDR_Pos (0U)
14358 #define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
14359 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
14360
14361 /******************* Bit definition for USART_TDR register ******************/
14362 #define USART_TDR_TDR_Pos (0U)
14363 #define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
14364 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
14365
14366 /******************************************************************************/
14367 /* */
14368 /* USB Device General registers */
14369 /* */
14370 /******************************************************************************/
14371 #define USB_CNTR (USB_BASE + 0x40U) /*!< Control register */
14372 #define USB_ISTR (USB_BASE + 0x44U) /*!< Interrupt status register */
14373 #define USB_FNR (USB_BASE + 0x48U) /*!< Frame number register */
14374 #define USB_DADDR (USB_BASE + 0x4CU) /*!< Device address register */
14375 #define USB_BTABLE (USB_BASE + 0x50U) /*!< Buffer Table address register */
14376 #define USB_LPMCSR (USB_BASE + 0x54U) /*!< LPM Control and Status register */
14377
14378 /**************************** ISTR interrupt events *************************/
14379 #define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
14380 #define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
14381 #define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
14382 #define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
14383 #define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
14384 #define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
14385 #define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
14386 #define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
14387 #define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
14388 #define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
14389 #define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
14390
14391 /* Legacy defines */
14392 #define USB_ISTR_PMAOVRM USB_ISTR_PMAOVR
14393
14394 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
14395 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
14396 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
14397 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
14398 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
14399 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
14400 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
14401 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
14402 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
14403
14404 /* Legacy defines */
14405 #define USB_CLR_PMAOVRM USB_CLR_PMAOVR
14406
14407 /************************* CNTR control register bits definitions ***********/
14408 #define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
14409 #define USB_CNTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
14410 #define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
14411 #define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
14412 #define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
14413 #define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
14414 #define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
14415 #define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
14416 #define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
14417 #define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
14418 #define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
14419 #define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
14420 #define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
14421 #define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
14422 #define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
14423
14424 /* Legacy defines */
14425 #define USB_CNTR_PMAOVRM USB_CNTR_PMAOVR
14426 #define USB_CNTR_LP_MODE USB_CNTR_LPMODE
14427
14428 /*************************** LPM register bits definitions ******************/
14429 #define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
14430 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
14431 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
14432 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
14433
14434 /******************** FNR Frame Number Register bit definitions ************/
14435 #define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
14436 #define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
14437 #define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
14438 #define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
14439 #define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
14440
14441 /******************** DADDR Device ADDRess bit definitions ****************/
14442 #define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */
14443 #define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */
14444
14445 /****************************** Endpoint register *************************/
14446 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
14447 #define USB_EP1R (USB_BASE + 0x04U) /*!< endpoint 1 register address */
14448 #define USB_EP2R (USB_BASE + 0x08U) /*!< endpoint 2 register address */
14449 #define USB_EP3R (USB_BASE + 0x0CU) /*!< endpoint 3 register address */
14450 #define USB_EP4R (USB_BASE + 0x10U) /*!< endpoint 4 register address */
14451 #define USB_EP5R (USB_BASE + 0x14U) /*!< endpoint 5 register address */
14452 #define USB_EP6R (USB_BASE + 0x18U) /*!< endpoint 6 register address */
14453 #define USB_EP7R (USB_BASE + 0x1CU) /*!< endpoint 7 register address */
14454 /* bit positions */
14455 #define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
14456 #define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
14457 #define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
14458 #define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
14459 #define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
14460 #define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
14461 #define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
14462 #define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
14463 #define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
14464 #define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
14465
14466 /* EndPoint REGister MASK (no toggle fields) */
14467 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
14468 /*!< EP_TYPE[1:0] EndPoint TYPE */
14469 #define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
14470 #define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
14471 #define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
14472 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
14473 #define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
14474 #define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
14475
14476 #define USB_EPKIND_MASK ((uint16_t) ~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
14477 /*!< STAT_TX[1:0] STATus for TX transfer */
14478 #define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
14479 #define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
14480 #define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
14481 #define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
14482 #define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
14483 #define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
14484 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
14485 /*!< STAT_RX[1:0] STATus for RX transfer */
14486 #define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
14487 #define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
14488 #define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
14489 #define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
14490 #define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
14491 #define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
14492 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
14493
14494 /******************************************************************************/
14495 /* */
14496 /* Window WATCHDOG */
14497 /* */
14498 /******************************************************************************/
14499 /******************* Bit definition for WWDG_CR register ********************/
14500 #define WWDG_CR_T_Pos (0U)
14501 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
14502 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
14503 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
14504 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
14505 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
14506 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
14507 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
14508 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
14509 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
14510
14511 /* Legacy defines */
14512 #define WWDG_CR_T0 WWDG_CR_T_0
14513 #define WWDG_CR_T1 WWDG_CR_T_1
14514 #define WWDG_CR_T2 WWDG_CR_T_2
14515 #define WWDG_CR_T3 WWDG_CR_T_3
14516 #define WWDG_CR_T4 WWDG_CR_T_4
14517 #define WWDG_CR_T5 WWDG_CR_T_5
14518 #define WWDG_CR_T6 WWDG_CR_T_6
14519
14520 #define WWDG_CR_WDGA_Pos (7U)
14521 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
14522 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
14523
14524 /******************* Bit definition for WWDG_CFR register *******************/
14525 #define WWDG_CFR_W_Pos (0U)
14526 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
14527 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
14528 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
14529 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
14530 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
14531 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
14532 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
14533 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
14534 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
14535
14536 /* Legacy defines */
14537 #define WWDG_CFR_W0 WWDG_CFR_W_0
14538 #define WWDG_CFR_W1 WWDG_CFR_W_1
14539 #define WWDG_CFR_W2 WWDG_CFR_W_2
14540 #define WWDG_CFR_W3 WWDG_CFR_W_3
14541 #define WWDG_CFR_W4 WWDG_CFR_W_4
14542 #define WWDG_CFR_W5 WWDG_CFR_W_5
14543 #define WWDG_CFR_W6 WWDG_CFR_W_6
14544
14545 #define WWDG_CFR_WDGTB_Pos (7U)
14546 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
14547 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
14548 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
14549 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
14550
14551 /* Legacy defines */
14552 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
14553 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
14554
14555 #define WWDG_CFR_EWI_Pos (9U)
14556 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
14557 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
14558
14559 /******************* Bit definition for WWDG_SR register ********************/
14560 #define WWDG_SR_EWIF_Pos (0U)
14561 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
14562 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
14563
14564 /**
14565 * @}
14566 */
14567
14568 /**
14569 * @}
14570 */
14571
14572 /** @addtogroup Exported_macros
14573 * @{
14574 */
14575
14576 /****************************** ADC Instances *********************************/
14577 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
14578 ((INSTANCE) == ADC2) || \
14579 ((INSTANCE) == ADC3) || \
14580 ((INSTANCE) == ADC4))
14581
14582 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
14583 ((INSTANCE) == ADC3))
14584
14585 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) || \
14586 ((INSTANCE) == ADC34_COMMON))
14587
14588 /****************************** CAN Instances *********************************/
14589 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
14590
14591 /****************************** COMP Instances ********************************/
14592 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
14593 ((INSTANCE) == COMP2) || \
14594 ((INSTANCE) == COMP3) || \
14595 ((INSTANCE) == COMP4) || \
14596 ((INSTANCE) == COMP5) || \
14597 ((INSTANCE) == COMP6) || \
14598 ((INSTANCE) == COMP7))
14599
14600 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) (((COMMON_INSTANCE) == COMP12_COMMON) || \
14601 ((COMMON_INSTANCE) == COMP34_COMMON) || \
14602 ((COMMON_INSTANCE) == COMP56_COMMON))
14603
14604
14605 /******************** COMP Instances with window mode capability **************/
14606 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \
14607 ((INSTANCE) == COMP4) || \
14608 ((INSTANCE) == COMP6))
14609
14610 /****************************** CRC Instances *********************************/
14611 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
14612
14613 /****************************** DAC Instances *********************************/
14614 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
14615
14616 #define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
14617 ((((INSTANCE) == DAC1) && \
14618 (((CHANNEL) == DAC_CHANNEL_1) || \
14619 ((CHANNEL) == DAC_CHANNEL_2))))
14620
14621 /****************************** DMA Instances *********************************/
14622 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
14623 ((INSTANCE) == DMA1_Channel2) || \
14624 ((INSTANCE) == DMA1_Channel3) || \
14625 ((INSTANCE) == DMA1_Channel4) || \
14626 ((INSTANCE) == DMA1_Channel5) || \
14627 ((INSTANCE) == DMA1_Channel6) || \
14628 ((INSTANCE) == DMA1_Channel7) || \
14629 ((INSTANCE) == DMA2_Channel1) || \
14630 ((INSTANCE) == DMA2_Channel2) || \
14631 ((INSTANCE) == DMA2_Channel3) || \
14632 ((INSTANCE) == DMA2_Channel4) || \
14633 ((INSTANCE) == DMA2_Channel5))
14634
14635 /****************************** GPIO Instances ********************************/
14636 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
14637 ((INSTANCE) == GPIOB) || \
14638 ((INSTANCE) == GPIOC) || \
14639 ((INSTANCE) == GPIOD) || \
14640 ((INSTANCE) == GPIOE) || \
14641 ((INSTANCE) == GPIOF) || \
14642 ((INSTANCE) == GPIOG) || \
14643 ((INSTANCE) == GPIOH))
14644
14645 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
14646 ((INSTANCE) == GPIOB) || \
14647 ((INSTANCE) == GPIOC) || \
14648 ((INSTANCE) == GPIOD) || \
14649 ((INSTANCE) == GPIOE) || \
14650 ((INSTANCE) == GPIOF) || \
14651 ((INSTANCE) == GPIOG) || \
14652 ((INSTANCE) == GPIOH))
14653
14654 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
14655 ((INSTANCE) == GPIOB) || \
14656 ((INSTANCE) == GPIOC) || \
14657 ((INSTANCE) == GPIOD) || \
14658 ((INSTANCE) == GPIOE) || \
14659 ((INSTANCE) == GPIOF) || \
14660 ((INSTANCE) == GPIOG) || \
14661 ((INSTANCE) == GPIOH))
14662
14663 /****************************** I2C Instances *********************************/
14664 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
14665 ((INSTANCE) == I2C2) || \
14666 ((INSTANCE) == I2C3))
14667
14668 /****************** I2C Instances : wakeup capability from stop modes *********/
14669 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
14670
14671 /****************************** I2S Instances *********************************/
14672 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
14673 ((INSTANCE) == SPI3))
14674 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext) || \
14675 ((INSTANCE) == I2S3ext))
14676
14677 /****************************** OPAMP Instances *******************************/
14678 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
14679 ((INSTANCE) == OPAMP2) || \
14680 ((INSTANCE) == OPAMP3) || \
14681 ((INSTANCE) == OPAMP4))
14682
14683 /****************************** IWDG Instances ********************************/
14684 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
14685
14686 /****************************** RTC Instances *********************************/
14687 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
14688
14689 /****************************** SMBUS Instances *******************************/
14690 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
14691 ((INSTANCE) == I2C2) || \
14692 ((INSTANCE) == I2C3))
14693
14694 /****************************** SPI Instances *********************************/
14695 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
14696 ((INSTANCE) == SPI2) || \
14697 ((INSTANCE) == SPI3) || \
14698 ((INSTANCE) == SPI4))
14699
14700 /******************* TIM Instances : All supported instances ******************/
14701 #define IS_TIM_INSTANCE(INSTANCE)\
14702 (((INSTANCE) == TIM1) || \
14703 ((INSTANCE) == TIM2) || \
14704 ((INSTANCE) == TIM3) || \
14705 ((INSTANCE) == TIM4) || \
14706 ((INSTANCE) == TIM6) || \
14707 ((INSTANCE) == TIM7) || \
14708 ((INSTANCE) == TIM8) || \
14709 ((INSTANCE) == TIM15) || \
14710 ((INSTANCE) == TIM16) || \
14711 ((INSTANCE) == TIM17) || \
14712 ((INSTANCE) == TIM20))
14713
14714 /******************* TIM Instances : at least 1 capture/compare channel *******/
14715 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
14716 (((INSTANCE) == TIM1) || \
14717 ((INSTANCE) == TIM2) || \
14718 ((INSTANCE) == TIM3) || \
14719 ((INSTANCE) == TIM4) || \
14720 ((INSTANCE) == TIM8) || \
14721 ((INSTANCE) == TIM15) || \
14722 ((INSTANCE) == TIM16) || \
14723 ((INSTANCE) == TIM17) || \
14724 ((INSTANCE) == TIM20))
14725
14726 /****************** TIM Instances : at least 2 capture/compare channels *******/
14727 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
14728 (((INSTANCE) == TIM1) || \
14729 ((INSTANCE) == TIM2) || \
14730 ((INSTANCE) == TIM3) || \
14731 ((INSTANCE) == TIM4) || \
14732 ((INSTANCE) == TIM8) || \
14733 ((INSTANCE) == TIM15) || \
14734 ((INSTANCE) == TIM20))
14735
14736 /****************** TIM Instances : at least 3 capture/compare channels *******/
14737 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
14738 (((INSTANCE) == TIM1) || \
14739 ((INSTANCE) == TIM2) || \
14740 ((INSTANCE) == TIM3) || \
14741 ((INSTANCE) == TIM4) || \
14742 ((INSTANCE) == TIM8) || \
14743 ((INSTANCE) == TIM20))
14744
14745 /****************** TIM Instances : at least 4 capture/compare channels *******/
14746 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
14747 (((INSTANCE) == TIM1) || \
14748 ((INSTANCE) == TIM2) || \
14749 ((INSTANCE) == TIM3) || \
14750 ((INSTANCE) == TIM4) || \
14751 ((INSTANCE) == TIM8) || \
14752 ((INSTANCE) == TIM20))
14753
14754 /****************** TIM Instances : at least 5 capture/compare channels *******/
14755 #define IS_TIM_CC5_INSTANCE(INSTANCE)\
14756 (((INSTANCE) == TIM1) || \
14757 ((INSTANCE) == TIM8) || \
14758 ((INSTANCE) == TIM20))
14759
14760 /****************** TIM Instances : at least 6 capture/compare channels *******/
14761 #define IS_TIM_CC6_INSTANCE(INSTANCE)\
14762 (((INSTANCE) == TIM1) || \
14763 ((INSTANCE) == TIM8) || \
14764 ((INSTANCE) == TIM20))
14765
14766 /************************** TIM Instances : Advanced-control timers ***********/
14767
14768 /****************** TIM Instances : Advanced timer instances *******************/
14769 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
14770 (((INSTANCE) == TIM1) || \
14771 ((INSTANCE) == TIM8) || \
14772 ((INSTANCE) == TIM20))
14773
14774 /****************** TIM Instances : supporting clock selection ****************/
14775 #define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
14776 (((INSTANCE) == TIM1) || \
14777 ((INSTANCE) == TIM2) || \
14778 ((INSTANCE) == TIM3) || \
14779 ((INSTANCE) == TIM4) || \
14780 ((INSTANCE) == TIM8) || \
14781 ((INSTANCE) == TIM15) || \
14782 ((INSTANCE) == TIM20))
14783
14784 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
14785 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
14786 (((INSTANCE) == TIM1) || \
14787 ((INSTANCE) == TIM2) || \
14788 ((INSTANCE) == TIM3) || \
14789 ((INSTANCE) == TIM4) || \
14790 ((INSTANCE) == TIM8) || \
14791 ((INSTANCE) == TIM20))
14792
14793 /****************** TIM Instances : supporting external clock mode 2 **********/
14794 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
14795 (((INSTANCE) == TIM1) || \
14796 ((INSTANCE) == TIM2) || \
14797 ((INSTANCE) == TIM3) || \
14798 ((INSTANCE) == TIM4) || \
14799 ((INSTANCE) == TIM8) || \
14800 ((INSTANCE) == TIM20))
14801
14802 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
14803 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
14804 (((INSTANCE) == TIM1) || \
14805 ((INSTANCE) == TIM2) || \
14806 ((INSTANCE) == TIM3) || \
14807 ((INSTANCE) == TIM4) || \
14808 ((INSTANCE) == TIM8) || \
14809 ((INSTANCE) == TIM15) || \
14810 ((INSTANCE) == TIM20))
14811
14812 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
14813 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
14814 (((INSTANCE) == TIM1) || \
14815 ((INSTANCE) == TIM2) || \
14816 ((INSTANCE) == TIM3) || \
14817 ((INSTANCE) == TIM4) || \
14818 ((INSTANCE) == TIM8) || \
14819 ((INSTANCE) == TIM15) || \
14820 ((INSTANCE) == TIM20))
14821
14822 /****************** TIM Instances : supporting OCxREF clear *******************/
14823 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
14824 (((INSTANCE) == TIM1) || \
14825 ((INSTANCE) == TIM2) || \
14826 ((INSTANCE) == TIM3) || \
14827 ((INSTANCE) == TIM4) || \
14828 ((INSTANCE) == TIM8) || \
14829 ((INSTANCE) == TIM20))
14830
14831 /****************** TIM Instances : supporting encoder interface **************/
14832 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
14833 (((INSTANCE) == TIM1) || \
14834 ((INSTANCE) == TIM2) || \
14835 ((INSTANCE) == TIM3) || \
14836 ((INSTANCE) == TIM4) || \
14837 ((INSTANCE) == TIM8) || \
14838 ((INSTANCE) == TIM20))
14839
14840 /****************** TIM Instances : supporting Hall interface *****************/
14841 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
14842 (((INSTANCE) == TIM1) || \
14843 ((INSTANCE) == TIM8) || \
14844 ((INSTANCE) == TIM20))
14845
14846 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\
14847 (((INSTANCE) == TIM1) || \
14848 ((INSTANCE) == TIM8) || \
14849 ((INSTANCE) == TIM20))
14850
14851 /**************** TIM Instances : external trigger input available ************/
14852 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14853 ((INSTANCE) == TIM2) || \
14854 ((INSTANCE) == TIM3) || \
14855 ((INSTANCE) == TIM4) || \
14856 ((INSTANCE) == TIM8) || \
14857 ((INSTANCE) == TIM20))
14858
14859 /****************** TIM Instances : supporting input XOR function *************/
14860 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
14861 (((INSTANCE) == TIM1) || \
14862 ((INSTANCE) == TIM2) || \
14863 ((INSTANCE) == TIM3) || \
14864 ((INSTANCE) == TIM4) || \
14865 ((INSTANCE) == TIM8) || \
14866 ((INSTANCE) == TIM15) || \
14867 ((INSTANCE) == TIM20))
14868
14869 /****************** TIM Instances : supporting master mode ********************/
14870 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
14871 (((INSTANCE) == TIM1) || \
14872 ((INSTANCE) == TIM2) || \
14873 ((INSTANCE) == TIM3) || \
14874 ((INSTANCE) == TIM4) || \
14875 ((INSTANCE) == TIM6) || \
14876 ((INSTANCE) == TIM7) || \
14877 ((INSTANCE) == TIM8) || \
14878 ((INSTANCE) == TIM15) || \
14879 ((INSTANCE) == TIM20))
14880
14881 /****************** TIM Instances : supporting slave mode *********************/
14882 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
14883 (((INSTANCE) == TIM1) || \
14884 ((INSTANCE) == TIM2) || \
14885 ((INSTANCE) == TIM3) || \
14886 ((INSTANCE) == TIM4) || \
14887 ((INSTANCE) == TIM8) || \
14888 ((INSTANCE) == TIM15) || \
14889 ((INSTANCE) == TIM20))
14890
14891 /****************** TIM Instances : supporting synchronization ****************/
14892 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
14893 (((INSTANCE) == TIM1) || \
14894 ((INSTANCE) == TIM2) || \
14895 ((INSTANCE) == TIM3) || \
14896 ((INSTANCE) == TIM4) || \
14897 ((INSTANCE) == TIM6) || \
14898 ((INSTANCE) == TIM7) || \
14899 ((INSTANCE) == TIM8) || \
14900 ((INSTANCE) == TIM15) || \
14901 ((INSTANCE) == TIM20))
14902
14903 /****************** TIM Instances : supporting 32 bits counter ****************/
14904 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
14905 ((INSTANCE) == TIM2)
14906
14907 /****************** TIM Instances : supporting DMA burst **********************/
14908 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
14909 (((INSTANCE) == TIM1) || \
14910 ((INSTANCE) == TIM2) || \
14911 ((INSTANCE) == TIM3) || \
14912 ((INSTANCE) == TIM4) || \
14913 ((INSTANCE) == TIM8) || \
14914 ((INSTANCE) == TIM15) || \
14915 ((INSTANCE) == TIM16) || \
14916 ((INSTANCE) == TIM17) || \
14917 ((INSTANCE) == TIM20))
14918
14919 /****************** TIM Instances : supporting the break function *************/
14920 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
14921 (((INSTANCE) == TIM1) || \
14922 ((INSTANCE) == TIM8) || \
14923 ((INSTANCE) == TIM15) || \
14924 ((INSTANCE) == TIM16) || \
14925 ((INSTANCE) == TIM17) || \
14926 ((INSTANCE) == TIM20))
14927
14928 /****************** TIM Instances : supporting input/output channel(s) ********/
14929 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
14930 ((((INSTANCE) == TIM1) && \
14931 (((CHANNEL) == TIM_CHANNEL_1) || \
14932 ((CHANNEL) == TIM_CHANNEL_2) || \
14933 ((CHANNEL) == TIM_CHANNEL_3) || \
14934 ((CHANNEL) == TIM_CHANNEL_4) || \
14935 ((CHANNEL) == TIM_CHANNEL_5) || \
14936 ((CHANNEL) == TIM_CHANNEL_6))) \
14937 || \
14938 (((INSTANCE) == TIM2) && \
14939 (((CHANNEL) == TIM_CHANNEL_1) || \
14940 ((CHANNEL) == TIM_CHANNEL_2) || \
14941 ((CHANNEL) == TIM_CHANNEL_3) || \
14942 ((CHANNEL) == TIM_CHANNEL_4))) \
14943 || \
14944 (((INSTANCE) == TIM3) && \
14945 (((CHANNEL) == TIM_CHANNEL_1) || \
14946 ((CHANNEL) == TIM_CHANNEL_2) || \
14947 ((CHANNEL) == TIM_CHANNEL_3) || \
14948 ((CHANNEL) == TIM_CHANNEL_4))) \
14949 || \
14950 (((INSTANCE) == TIM4) && \
14951 (((CHANNEL) == TIM_CHANNEL_1) || \
14952 ((CHANNEL) == TIM_CHANNEL_2) || \
14953 ((CHANNEL) == TIM_CHANNEL_3) || \
14954 ((CHANNEL) == TIM_CHANNEL_4))) \
14955 || \
14956 (((INSTANCE) == TIM8) && \
14957 (((CHANNEL) == TIM_CHANNEL_1) || \
14958 ((CHANNEL) == TIM_CHANNEL_2) || \
14959 ((CHANNEL) == TIM_CHANNEL_3) || \
14960 ((CHANNEL) == TIM_CHANNEL_4) || \
14961 ((CHANNEL) == TIM_CHANNEL_5) || \
14962 ((CHANNEL) == TIM_CHANNEL_6))) \
14963 || \
14964 (((INSTANCE) == TIM15) && \
14965 (((CHANNEL) == TIM_CHANNEL_1) || \
14966 ((CHANNEL) == TIM_CHANNEL_2))) \
14967 || \
14968 (((INSTANCE) == TIM16) && \
14969 (((CHANNEL) == TIM_CHANNEL_1))) \
14970 || \
14971 (((INSTANCE) == TIM17) && \
14972 (((CHANNEL) == TIM_CHANNEL_1))) \
14973 || \
14974 (((INSTANCE) == TIM20) && \
14975 (((CHANNEL) == TIM_CHANNEL_1) || \
14976 ((CHANNEL) == TIM_CHANNEL_2) || \
14977 ((CHANNEL) == TIM_CHANNEL_3) || \
14978 ((CHANNEL) == TIM_CHANNEL_4) || \
14979 ((CHANNEL) == TIM_CHANNEL_5) || \
14980 ((CHANNEL) == TIM_CHANNEL_6))))
14981
14982 /****************** TIM Instances : supporting complementary output(s) ********/
14983 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
14984 ((((INSTANCE) == TIM1) && \
14985 (((CHANNEL) == TIM_CHANNEL_1) || \
14986 ((CHANNEL) == TIM_CHANNEL_2) || \
14987 ((CHANNEL) == TIM_CHANNEL_3))) \
14988 || \
14989 (((INSTANCE) == TIM8) && \
14990 (((CHANNEL) == TIM_CHANNEL_1) || \
14991 ((CHANNEL) == TIM_CHANNEL_2) || \
14992 ((CHANNEL) == TIM_CHANNEL_3))) \
14993 || \
14994 (((INSTANCE) == TIM15) && \
14995 ((CHANNEL) == TIM_CHANNEL_1)) \
14996 || \
14997 (((INSTANCE) == TIM16) && \
14998 ((CHANNEL) == TIM_CHANNEL_1)) \
14999 || \
15000 (((INSTANCE) == TIM17) && \
15001 ((CHANNEL) == TIM_CHANNEL_1)) \
15002 || \
15003 (((INSTANCE) == TIM20) && \
15004 (((CHANNEL) == TIM_CHANNEL_1) || \
15005 ((CHANNEL) == TIM_CHANNEL_2) || \
15006 ((CHANNEL) == TIM_CHANNEL_3))))
15007
15008 /****************** TIM Instances : supporting counting mode selection ********/
15009 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
15010 (((INSTANCE) == TIM1) || \
15011 ((INSTANCE) == TIM2) || \
15012 ((INSTANCE) == TIM3) || \
15013 ((INSTANCE) == TIM4) || \
15014 ((INSTANCE) == TIM8) || \
15015 ((INSTANCE) == TIM20))
15016
15017 /****************** TIM Instances : supporting repetition counter *************/
15018 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
15019 (((INSTANCE) == TIM1) || \
15020 ((INSTANCE) == TIM8) || \
15021 ((INSTANCE) == TIM15) || \
15022 ((INSTANCE) == TIM16) || \
15023 ((INSTANCE) == TIM17) || \
15024 ((INSTANCE) == TIM20))
15025
15026 /****************** TIM Instances : supporting clock division *****************/
15027 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
15028 (((INSTANCE) == TIM1) || \
15029 ((INSTANCE) == TIM2) || \
15030 ((INSTANCE) == TIM3) || \
15031 ((INSTANCE) == TIM4) || \
15032 ((INSTANCE) == TIM8) || \
15033 ((INSTANCE) == TIM15) || \
15034 ((INSTANCE) == TIM16) || \
15035 ((INSTANCE) == TIM17) || \
15036 ((INSTANCE) == TIM20))
15037
15038 /****************** TIM Instances : supporting 2 break inputs *****************/
15039 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
15040 (((INSTANCE) == TIM1) || \
15041 ((INSTANCE) == TIM8) || \
15042 ((INSTANCE) == TIM20))
15043
15044 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
15045 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
15046 (((INSTANCE) == TIM1) || \
15047 ((INSTANCE) == TIM8) || \
15048 ((INSTANCE) == TIM20))
15049
15050 /****************** TIM Instances : supporting DMA generation on Update events*/
15051 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
15052 (((INSTANCE) == TIM1) || \
15053 ((INSTANCE) == TIM2) || \
15054 ((INSTANCE) == TIM3) || \
15055 ((INSTANCE) == TIM4) || \
15056 ((INSTANCE) == TIM6) || \
15057 ((INSTANCE) == TIM7) || \
15058 ((INSTANCE) == TIM8) || \
15059 ((INSTANCE) == TIM15) || \
15060 ((INSTANCE) == TIM16) || \
15061 ((INSTANCE) == TIM17) || \
15062 ((INSTANCE) == TIM20))
15063
15064 /****************** TIM Instances : supporting DMA generation on Capture/Compare events */
15065 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
15066 (((INSTANCE) == TIM1) || \
15067 ((INSTANCE) == TIM2) || \
15068 ((INSTANCE) == TIM3) || \
15069 ((INSTANCE) == TIM4) || \
15070 ((INSTANCE) == TIM8) || \
15071 ((INSTANCE) == TIM15) || \
15072 ((INSTANCE) == TIM16) || \
15073 ((INSTANCE) == TIM17) || \
15074 ((INSTANCE) == TIM20))
15075
15076 /****************** TIM Instances : supporting commutation event generation ***/
15077 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
15078 (((INSTANCE) == TIM1) || \
15079 ((INSTANCE) == TIM8) || \
15080 ((INSTANCE) == TIM15) || \
15081 ((INSTANCE) == TIM16) || \
15082 ((INSTANCE) == TIM17) || \
15083 ((INSTANCE) == TIM20))
15084
15085 /****************** TIM Instances : supporting remapping capability ***********/
15086 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
15087 (((INSTANCE) == TIM1) || \
15088 ((INSTANCE) == TIM8) || \
15089 ((INSTANCE) == TIM16) || \
15090 ((INSTANCE) == TIM20))
15091
15092 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
15093 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \
15094 (((INSTANCE) == TIM1) || \
15095 ((INSTANCE) == TIM8) || \
15096 ((INSTANCE) == TIM20))
15097
15098 /****************************** TSC Instances *********************************/
15099 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
15100
15101 /******************** USART Instances : Synchronous mode **********************/
15102 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15103 ((INSTANCE) == USART2) || \
15104 ((INSTANCE) == USART3))
15105
15106 /****************** USART Instances : Auto Baud Rate detection ****************/
15107 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15108 ((INSTANCE) == USART2) || \
15109 ((INSTANCE) == USART3))
15110
15111 /******************** UART Instances : Asynchronous mode **********************/
15112 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15113 ((INSTANCE) == USART2) || \
15114 ((INSTANCE) == USART3) || \
15115 ((INSTANCE) == UART4) || \
15116 ((INSTANCE) == UART5))
15117
15118 /******************** UART Instances : Half-Duplex mode **********************/
15119 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15120 ((INSTANCE) == USART2) || \
15121 ((INSTANCE) == USART3) || \
15122 ((INSTANCE) == UART4) || \
15123 ((INSTANCE) == UART5))
15124
15125 /******************** UART Instances : LIN mode **********************/
15126 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15127 ((INSTANCE) == USART2) || \
15128 ((INSTANCE) == USART3) || \
15129 ((INSTANCE) == UART4) || \
15130 ((INSTANCE) == UART5))
15131
15132 /******************** UART Instances : Wake-up from Stop mode **********************/
15133 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15134 ((INSTANCE) == USART2) || \
15135 ((INSTANCE) == USART3) || \
15136 ((INSTANCE) == UART4) || \
15137 ((INSTANCE) == UART5))
15138
15139 /****************** UART Instances : Hardware Flow control ********************/
15140 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15141 ((INSTANCE) == USART2) || \
15142 ((INSTANCE) == USART3))
15143
15144 /****************** UART Instances : Auto Baud Rate detection *****************/
15145 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15146 ((INSTANCE) == USART2) || \
15147 ((INSTANCE) == USART3))
15148
15149 /****************** UART Instances : Driver Enable ****************************/
15150 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15151 ((INSTANCE) == USART2) || \
15152 ((INSTANCE) == USART3))
15153
15154 /********************* UART Instances : Smard card mode ***********************/
15155 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15156 ((INSTANCE) == USART2) || \
15157 ((INSTANCE) == USART3))
15158
15159 /*********************** UART Instances : IRDA mode ***************************/
15160 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15161 ((INSTANCE) == USART2) || \
15162 ((INSTANCE) == USART3) || \
15163 ((INSTANCE) == UART4) || \
15164 ((INSTANCE) == UART5))
15165
15166 /******************** UART Instances : Support of continuous communication using DMA ****/
15167 #define IS_UART_DMA_INSTANCE(INSTANCE) (1)
15168
15169 /****************************** USB Instances *********************************/
15170 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
15171
15172 /****************************** WWDG Instances ********************************/
15173 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
15174
15175 /**
15176 * @}
15177 */
15178
15179
15180 /******************************************************************************/
15181 /* For a painless codes migration between the STM32F3xx device product */
15182 /* lines, the aliases defined below are put in place to overcome the */
15183 /* differences in the interrupt handlers and IRQn definitions. */
15184 /* No need to update developed interrupt code when moving across */
15185 /* product lines within the same STM32F3 Family */
15186 /******************************************************************************/
15187
15188 /* Aliases for __IRQn */
15189 #define ADC1_IRQn ADC1_2_IRQn
15190 #define SDADC1_IRQn ADC4_IRQn
15191 #define COMP1_2_IRQn COMP1_2_3_IRQn
15192 #define COMP2_IRQn COMP1_2_3_IRQn
15193 #define COMP_IRQn COMP1_2_3_IRQn
15194 #define COMP4_6_IRQn COMP4_5_6_IRQn
15195 #define HRTIM1_FLT_IRQn I2C3_ER_IRQn
15196 #define HRTIM1_TIME_IRQn I2C3_EV_IRQn
15197 #define TIM15_IRQn TIM1_BRK_TIM15_IRQn
15198 #define TIM18_DAC2_IRQn TIM1_CC_IRQn
15199 #define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
15200 #define TIM16_IRQn TIM1_UP_TIM16_IRQn
15201 #define TIM19_IRQn TIM20_UP_IRQn
15202 #define TIM6_DAC1_IRQn TIM6_DAC_IRQn
15203 #define TIM7_DAC2_IRQn TIM7_IRQn
15204 #define TIM12_IRQn TIM8_BRK_IRQn
15205 #define TIM14_IRQn TIM8_TRG_COM_IRQn
15206 #define TIM13_IRQn TIM8_UP_IRQn
15207 #define CEC_IRQn USBWakeUp_IRQn
15208 #define USBWakeUp_IRQn USBWakeUp_RMP_IRQn
15209 #define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
15210 #define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
15211
15212
15213 /* Aliases for __IRQHandler */
15214 #define ADC1_IRQHandler ADC1_2_IRQHandler
15215 #define SDADC1_IRQHandler ADC4_IRQHandler
15216 #define COMP1_2_IRQHandler COMP1_2_3_IRQHandler
15217 #define COMP2_IRQHandler COMP1_2_3_IRQHandler
15218 #define COMP_IRQHandler COMP1_2_3_IRQHandler
15219 #define COMP4_6_IRQHandler COMP4_5_6_IRQHandler
15220 #define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler
15221 #define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler
15222 #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
15223 #define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
15224 #define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
15225 #define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
15226 #define TIM19_IRQHandler TIM20_UP_IRQHandler
15227 #define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
15228 #define TIM7_DAC2_IRQHandler TIM7_IRQHandler
15229 #define TIM12_IRQHandler TIM8_BRK_IRQHandler
15230 #define TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
15231 #define TIM13_IRQHandler TIM8_UP_IRQHandler
15232 #define CEC_IRQHandler USBWakeUp_IRQHandler
15233 #define USBWakeUp_IRQHandler USBWakeUp_RMP_IRQHandler
15234 #define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
15235 #define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
15236
15237
15238 #ifdef __cplusplus
15239 }
15240 #endif /* __cplusplus */
15241
15242 #endif /* __STM32F303xE_H */
15243
15244 /**
15245 * @}
15246 */
15247
15248 /**
15249 * @}
15250 */
15251
15252 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Mercurial Repository: hp34970-firmware

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