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comparison: src/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/system_clock.c

src/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/system_clock.c

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1 /* mbed Microcontroller Library
2 * Copyright (c) 2006-2017 ARM Limited
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 /**
18 * This file configures the system clock as follows:
19 *-----------------------------------------------------------------------------
20 * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
21 * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
22 * | 3- USE_PLL_HSI (internal 8 MHz)
23 *-----------------------------------------------------------------------------
24 * SYSCLK(MHz) | 72
25 * AHBCLK (MHz) | 72
26 * APB1CLK (MHz) | 36
27 * APB2CLK (MHz) | 72
28 * USB capable | YES
29 *-----------------------------------------------------------------------------
30 */
31
32
33 #include "stm32f3xx.h"
34 #include "mbed_error.h"
35
36 // clock source is selected with CLOCK_SOURCE in json config
37 #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
38 #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
39 #define USE_PLL_HSI 0x2 // Use HSI internal clock
40
41 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
42 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
43 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
44
45 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
46 uint8_t SetSysClock_PLL_HSI(void);
47 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
48
49 /**
50 * @brief Setup the microcontroller system
51 * Initialize the FPU setting, vector table location and the PLL configuration is reset.
52 * @param None
53 * @retval None
54 */
55 void SystemInit(void)
56 {
57 /* FPU settings ------------------------------------------------------------*/
58 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
59 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
60 #endif
61
62 /* Reset the RCC clock configuration to the default reset state ------------*/
63 /* Set HSION bit */
64 RCC->CR |= 0x00000001U;
65
66 /* Reset CFGR register */
67 RCC->CFGR &= 0xF87FC00CU;
68
69 /* Reset HSEON, CSSON and PLLON bits */
70 RCC->CR &= 0xFEF6FFFFU;
71
72 /* Reset HSEBYP bit */
73 RCC->CR &= 0xFFFBFFFFU;
74
75 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
76 RCC->CFGR &= 0xFF80FFFFU;
77
78 /* Reset PREDIV1[3:0] bits */
79 RCC->CFGR2 &= 0xFFFFFFF0U;
80
81 /* Reset USARTSW[1:0], I2CSW and TIMs bits */
82 RCC->CFGR3 &= 0xFF00FCCCU;
83
84 /* Disable all interrupts */
85 RCC->CIR = 0x00000000U;
86 }
87
88
89 /**
90 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
91 * AHB/APBx prescalers and Flash settings
92 * @note This function should be called only once the RCC clock configuration
93 * is reset to the default reset state (done in SystemInit() function).
94 * @param None
95 * @retval None
96 */
97
98 void SetSysClock(void)
99 {
100 #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
101 /* 1- Try to start with HSE and external clock */
102 if (SetSysClock_PLL_HSE(1) == 0)
103 #endif
104 {
105 #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
106 /* 2- If fail try to start with HSE and external xtal */
107 if (SetSysClock_PLL_HSE(0) == 0)
108 #endif
109 {
110 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
111 /* 3- If fail start with HSI clock */
112 if (SetSysClock_PLL_HSI() == 0)
113 #endif
114 {
115 {
116 error("SetSysClock failed\n");
117 }
118 }
119 }
120 }
121
122 /* Output clock on MCO2 pin(PC9) for debugging purpose */
123 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
124 }
125
126 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
127 /******************************************************************************/
128 /* PLL (clocked by HSE) used as System clock source */
129 /******************************************************************************/
130 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
131 {
132 RCC_ClkInitTypeDef RCC_ClkInitStruct;
133 RCC_OscInitTypeDef RCC_OscInitStruct;
134 RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
135
136 /* Enable HSE oscillator and activate PLL with HSE as source */
137 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
138 if (bypass == 0) {
139 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
140 } else {
141 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
142 }
143 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
144 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
145 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
146 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
147 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
148 return 0; // FAIL
149 }
150
151 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
152 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
153 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
154 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz
155 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz
156 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz
157 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
158 return 0; // FAIL
159 }
160
161 RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
162 RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
163 if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
164 return 0; // FAIL
165 }
166
167 /* Output clock on MCO1 pin(PA8) for debugging purpose */
168 //if (bypass == 0)
169 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
170 //else
171 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
172
173 return 1; // OK
174 }
175 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
176
177 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
178 /******************************************************************************/
179 /* PLL (clocked by HSI) used as System clock source */
180 /******************************************************************************/
181 uint8_t SetSysClock_PLL_HSI(void)
182 {
183 RCC_ClkInitTypeDef RCC_ClkInitStruct;
184 RCC_OscInitTypeDef RCC_OscInitStruct;
185 RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
186
187 /* Enable HSI oscillator and activate PLL with HSI as source */
188 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
189 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
190 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
191 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
192 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
193 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
194 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
195 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz/1 * 9)
196 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
197 return 0; // FAIL
198 }
199
200 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
201 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
202 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
203 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz
204 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz
205 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz
206 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
207 return 0; // FAIL
208 }
209
210 RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
211 RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
212 if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
213 return 0; // FAIL
214 }
215
216 /* Output clock on MCO1 pin(PA8) for debugging purpose */
217 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
218
219 return 1; // OK
220 }
221 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

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