Mercurial > hp34970-firmware / file comparison

comparison: src/TARGET_HP34970_FP_F303RD/system_clock.c

src/TARGET_HP34970_FP_F303RD/system_clock.c

changeset 30
71be284c66b3
child 32
bc1d6ecbb0cc
equal deleted inserted replaced
29:276195d58a1d 30:71be284c66b3
1 /* mbed Microcontroller Library
2 * Copyright (c) 2006-2017 ARM Limited
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 /**
18 * This file configures the system clock as follows:
19 *-----------------------------------------------------------------------------
20 * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
21 * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
22 * | 3- USE_PLL_HSI (internal 8 MHz)
23 *-----------------------------------------------------------------------------
24 * SYSCLK(MHz) | 72
25 * AHBCLK (MHz) | 72
26 * APB1CLK (MHz) | 36
27 * APB2CLK (MHz) | 72
28 * USB capable | YES
29 *-----------------------------------------------------------------------------
30 */
31
32 #if defined(TARGET_HP34970_FP_F303RE)
33
34 #include "stm32f3xx.h"
35 #include "mbed_error.h"
36
37 // clock source is selected with CLOCK_SOURCE in json config
38 #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
39 #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
40 #define USE_PLL_HSI 0x2 // Use HSI internal clock
41
42 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
43 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
44 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
45
46 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
47 uint8_t SetSysClock_PLL_HSI(void);
48 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
49
50 /**
51 * @brief Setup the microcontroller system
52 * Initialize the FPU setting, vector table location and the PLL configuration is reset.
53 * @param None
54 * @retval None
55 */
56 void SystemInit(void)
57 {
58 /* FPU settings ------------------------------------------------------------*/
59 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
60 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
61 #endif
62
63 /* Reset the RCC clock configuration to the default reset state ------------*/
64 /* Set HSION bit */
65 RCC->CR |= 0x00000001U;
66
67 /* Reset CFGR register */
68 RCC->CFGR &= 0xF87FC00CU;
69
70 /* Reset HSEON, CSSON and PLLON bits */
71 RCC->CR &= 0xFEF6FFFFU;
72
73 /* Reset HSEBYP bit */
74 RCC->CR &= 0xFFFBFFFFU;
75
76 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
77 RCC->CFGR &= 0xFF80FFFFU;
78
79 /* Reset PREDIV1[3:0] bits */
80 RCC->CFGR2 &= 0xFFFFFFF0U;
81
82 /* Reset USARTSW[1:0], I2CSW and TIMs bits */
83 RCC->CFGR3 &= 0xFF00FCCCU;
84
85 /* Disable all interrupts */
86 RCC->CIR = 0x00000000U;
87 }
88
89
90 /**
91 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
92 * AHB/APBx prescalers and Flash settings
93 * @note This function should be called only once the RCC clock configuration
94 * is reset to the default reset state (done in SystemInit() function).
95 * @param None
96 * @retval None
97 */
98
99 void SetSysClock(void)
100 {
101 #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
102 /* 1- Try to start with HSE and external clock */
103 if (SetSysClock_PLL_HSE(1) == 0)
104 #endif
105 {
106 #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
107 /* 2- If fail try to start with HSE and external xtal */
108 if (SetSysClock_PLL_HSE(0) == 0)
109 #endif
110 {
111 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
112 /* 3- If fail start with HSI clock */
113 if (SetSysClock_PLL_HSI() == 0)
114 #endif
115 {
116 {
117 error("SetSysClock failed\n");
118 }
119 }
120 }
121 }
122
123 /* Output clock on MCO2 pin(PC9) for debugging purpose */
124 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
125 }
126
127 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
128 /******************************************************************************/
129 /* PLL (clocked by HSE) used as System clock source */
130 /******************************************************************************/
131 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
132 {
133 RCC_ClkInitTypeDef RCC_ClkInitStruct;
134 RCC_OscInitTypeDef RCC_OscInitStruct;
135 RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
136
137 /* Enable HSE oscillator and activate PLL with HSE as source */
138 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
139 if (bypass == 0) {
140 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
141 } else {
142 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
143 }
144 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
145 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
146 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
147 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
148 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
149 return 0; // FAIL
150 }
151
152 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
153 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
154 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
155 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz
156 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz
157 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz
158 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
159 return 0; // FAIL
160 }
161
162 RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
163 RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
164 if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
165 return 0; // FAIL
166 }
167
168 /* Output clock on MCO1 pin(PA8) for debugging purpose */
169 //if (bypass == 0)
170 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
171 //else
172 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
173
174 return 1; // OK
175 }
176 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
177
178 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
179 /******************************************************************************/
180 /* PLL (clocked by HSI) used as System clock source */
181 /******************************************************************************/
182 uint8_t SetSysClock_PLL_HSI(void)
183 {
184 RCC_ClkInitTypeDef RCC_ClkInitStruct;
185 RCC_OscInitTypeDef RCC_OscInitStruct;
186 RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
187 grr;
188
189 /* Enable HSI oscillator and activate PLL with HSI as source */
190 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
191 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
192 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
193 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
194 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
195 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
196 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
197 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz/1 * 9)
198 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
199 return 0; // FAIL
200 }
201
202 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
203 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
204 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
205 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz
206 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz
207 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz
208 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
209 return 0; // FAIL
210 }
211
212 RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
213 RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
214 if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
215 return 0; // FAIL
216 }
217
218 /* Output clock on MCO1 pin(PA8) for debugging purpose */
219 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
220
221 return 1; // OK
222 }
223 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
224
225 #endif /* TARGET_HP34970_FP_F303RE */

Mercurial Repository: hp34970-firmware

mercurial