Thu, 12 Nov 2020 20:26:35 +0100
Reorganize the display + improvements for dimmed flags
- the whole upper zone is now dediacated to the main character line
- make sure eash flag has a dedicated non-overlaping area
- improve support for dimmed flags (not yet properly functionning since this
dimm state is actually stateful, so some major refactorings are needed to
properly handle this).
30
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
1 | /* mbed Microcontroller Library |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
2 | * Copyright (c) 2006-2017 ARM Limited |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
3 | * |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
5 | * you may not use this file except in compliance with the License. |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
6 | * You may obtain a copy of the License at |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
7 | * |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
8 | * http://www.apache.org/licenses/LICENSE-2.0 |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
9 | * |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
10 | * Unless required by applicable law or agreed to in writing, software |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
11 | * distributed under the License is distributed on an "AS IS" BASIS, |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
13 | * See the License for the specific language governing permissions and |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
14 | * limitations under the License. |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
15 | */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
16 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
17 | /** |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
18 | * This file configures the system clock as follows: |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
19 | *----------------------------------------------------------------------------- |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
20 | * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
21 | * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
22 | * | 3- USE_PLL_HSI (internal 8 MHz) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
23 | *----------------------------------------------------------------------------- |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
24 | * SYSCLK(MHz) | 72 |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
25 | * AHBCLK (MHz) | 72 |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
26 | * APB1CLK (MHz) | 36 |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
27 | * APB2CLK (MHz) | 72 |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
28 | * USB capable | YES |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
29 | *----------------------------------------------------------------------------- |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
30 | */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
31 | |
32
bc1d6ecbb0cc
Update the main code: extract headers and use a CircularBuffer for key events
David Douard <david.douard@sdf3.org>
parents:
30
diff
changeset
|
32 | #if defined(TARGET_HP34970_FP_F303RD) |
30
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
33 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
34 | #include "stm32f3xx.h" |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
35 | #include "mbed_error.h" |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
36 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
37 | // clock source is selected with CLOCK_SOURCE in json config |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
38 | #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
39 | #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
40 | #define USE_PLL_HSI 0x2 // Use HSI internal clock |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
41 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
42 | #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
43 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
44 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
45 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
46 | #if ((CLOCK_SOURCE) & USE_PLL_HSI) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
47 | uint8_t SetSysClock_PLL_HSI(void); |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
48 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
49 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
50 | /** |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
51 | * @brief Setup the microcontroller system |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
52 | * Initialize the FPU setting, vector table location and the PLL configuration is reset. |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
53 | * @param None |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
54 | * @retval None |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
55 | */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
56 | void SystemInit(void) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
57 | { |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
58 | /* FPU settings ------------------------------------------------------------*/ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
59 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
60 | SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
61 | #endif |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
62 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
63 | /* Reset the RCC clock configuration to the default reset state ------------*/ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
64 | /* Set HSION bit */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
65 | RCC->CR |= 0x00000001U; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
66 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
67 | /* Reset CFGR register */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
68 | RCC->CFGR &= 0xF87FC00CU; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
69 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
70 | /* Reset HSEON, CSSON and PLLON bits */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
71 | RCC->CR &= 0xFEF6FFFFU; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
72 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
73 | /* Reset HSEBYP bit */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
74 | RCC->CR &= 0xFFFBFFFFU; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
75 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
76 | /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
77 | RCC->CFGR &= 0xFF80FFFFU; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
78 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
79 | /* Reset PREDIV1[3:0] bits */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
80 | RCC->CFGR2 &= 0xFFFFFFF0U; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
81 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
82 | /* Reset USARTSW[1:0], I2CSW and TIMs bits */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
83 | RCC->CFGR3 &= 0xFF00FCCCU; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
84 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
85 | /* Disable all interrupts */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
86 | RCC->CIR = 0x00000000U; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
87 | } |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
88 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
89 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
90 | /** |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
91 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
92 | * AHB/APBx prescalers and Flash settings |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
93 | * @note This function should be called only once the RCC clock configuration |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
94 | * is reset to the default reset state (done in SystemInit() function). |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
95 | * @param None |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
96 | * @retval None |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
97 | */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
98 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
99 | void SetSysClock(void) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
100 | { |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
101 | #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
102 | /* 1- Try to start with HSE and external clock */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
103 | if (SetSysClock_PLL_HSE(1) == 0) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
104 | #endif |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
105 | { |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
106 | #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
107 | /* 2- If fail try to start with HSE and external xtal */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
108 | if (SetSysClock_PLL_HSE(0) == 0) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
109 | #endif |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
110 | { |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
111 | #if ((CLOCK_SOURCE) & USE_PLL_HSI) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
112 | /* 3- If fail start with HSI clock */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
113 | if (SetSysClock_PLL_HSI() == 0) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
114 | #endif |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
115 | { |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
116 | { |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
117 | error("SetSysClock failed\n"); |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
118 | } |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
119 | } |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
120 | } |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
121 | } |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
122 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
123 | /* Output clock on MCO2 pin(PC9) for debugging purpose */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
124 | //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
125 | } |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
126 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
127 | #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
128 | /******************************************************************************/ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
129 | /* PLL (clocked by HSE) used as System clock source */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
130 | /******************************************************************************/ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
131 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
132 | { |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
133 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
134 | RCC_OscInitTypeDef RCC_OscInitStruct; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
135 | RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
136 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
137 | /* Enable HSE oscillator and activate PLL with HSE as source */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
138 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
139 | if (bypass == 0) { |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
140 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
141 | } else { |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
142 | RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
143 | } |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
144 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
145 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
146 | RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
147 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
148 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
149 | return 0; // FAIL |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
150 | } |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
151 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
152 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
153 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
154 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
155 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
156 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
157 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
158 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
159 | return 0; // FAIL |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
160 | } |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
161 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
162 | RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
163 | RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
164 | if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
165 | return 0; // FAIL |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
166 | } |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
167 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
168 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
169 | //if (bypass == 0) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
170 | // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
171 | //else |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
172 | // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
173 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
174 | return 1; // OK |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
175 | } |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
176 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
177 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
178 | #if ((CLOCK_SOURCE) & USE_PLL_HSI) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
179 | /******************************************************************************/ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
180 | /* PLL (clocked by HSI) used as System clock source */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
181 | /******************************************************************************/ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
182 | uint8_t SetSysClock_PLL_HSI(void) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
183 | { |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
184 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
185 | RCC_OscInitTypeDef RCC_OscInitStruct; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
186 | RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
187 | grr; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
188 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
189 | /* Enable HSI oscillator and activate PLL with HSI as source */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
190 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
191 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
192 | RCC_OscInitStruct.HSEState = RCC_HSE_OFF; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
193 | RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
194 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
195 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
196 | RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
197 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz/1 * 9) |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
198 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
199 | return 0; // FAIL |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
200 | } |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
201 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
202 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
203 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
204 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
205 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
206 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
207 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
208 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
209 | return 0; // FAIL |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
210 | } |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
211 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
212 | RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
213 | RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5; |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
214 | if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
215 | return 0; // FAIL |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
216 | } |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
217 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
218 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
219 | //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
220 | |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
221 | return 1; // OK |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
222 | } |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
223 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ |
71be284c66b3
Update the custom target HP34970_FP_303RD
David Douard <david.douard@sdf3.org>
parents:
diff
changeset
|
224 | |
32
bc1d6ecbb0cc
Update the main code: extract headers and use a CircularBuffer for key events
David Douard <david.douard@sdf3.org>
parents:
30
diff
changeset
|
225 | #endif /* TARGET_HP34970_FP_F303RD */ |